LOCAL ANALOGUE EQUILIBRATING SYSTEM FOR A SET OF DEVICES FOR STORING ELECTRICAL POWER VIA A CAPACITIVE EFFECT, ELECTRICAL INSTALLATION, TRANSPORT VEHICLE AND RECHARGEABLE STORAGE MODULE COMPRISING SUCH A SYSTEM

Abstract

An analogue system for balancing an electrical energy storage assembly having a plurality of capacitive effect electrical energy storage devices connected to one another in series, the system including, for each storage device, a balancing device including: a bypass circuit for the storage device, able to be controlled between a closed state and an open state; a first voltage comparator for controlling an open or closed state of the bypass circuit depending on a balancing voltage; and a second voltage comparator for controlling an open or closed state of the bypass circuit depending on a switch-off voltage.

Claims

1. An analogue system for balancing a rechargeable electrical energy storage assembly comprising a plurality of capacitive-effect storage devices connected to one another in series, said system comprising, for each storage device, a balancing device including: a bypass circuit for said storage device, able to be controlled between a closed state and an open state; and a voltage comparator, called first comparator, arranged to control said bypass circuit into an open or closed state depending on the voltage at the terminals of said storage device and on a predetermined voltage, called balancing voltage; said system including for each storage device, another voltage comparator, called second comparator, designed to control an open or closed state of the bypass circuit for said storage device depending: on the voltage on the terminals of said storage device; and on a predetermined voltage, called switch-off voltage, representative of a closed state of the majority, or of all, of the bypass circuits.

2. The system according to claim 1, characterized in that, for at least one, in particular each, storage device, at least one of the first and second comparators is referenced to the potentials on the terminals of said storage device, and is configured to supply, as output: in a first state: the smallest potential on the terminals of said storage device; and in a second state: the greatest potential on the terminals of said storage.

3. The system according to claim 1, characterized in that it comprises, for at least one, in particular each, storage device: a voltage divider, called first voltage divider, supplying, to the first comparator, a first input voltage that is proportional to and lower than said voltage on the terminals of said storage device; and/or a voltage divider, called second voltage divider, supplying, to the second comparator, a second input voltage that is proportional to and lower than said voltage across the terminals of said storage device.

4. The system according to claim 3, characterized in that, for at least one storage device, the voltage divider(s) is (are) dimensioned such that the first and second comparators perform a comparison of the input voltages at one and the same reference voltage, in particular supplied by one and the same single source.

5. The system according to claim 1, characterized in that at least one of the first and second comparators is a hysteresis comparator.

6. The system according to claim 1, characterized in that at least one, in particular each, bypass circuit comprises two switches in series, one controlled depending on the voltage supplied by the first comparator and the other controlled depending on the voltage supplied by the second comparator.

7. The system according to claim 1, characterized in that at least one, in particular each, bypass circuit comprises a single switch, the balancing device further comprising a means for controlling said single switch depending on the voltages supplied by the first and second comparators.

8. The system according to claim 7, characterized in that the control means comprises: a transistor that is in the blocked state by default, for example an NPN bipolar transistor, in particular when the second comparator is an inverting comparator; or a transistor that is in the on state by default, for example a PNP bipolar transistor, in particular when the second comparator is a non-inverting comparator.

9. The system according to claim 1, characterized in that it further comprises a device for monitoring the operation of said system depending on the voltages supplied by the second comparators of all of the storage devices.

10. The system according to claim 7, characterized in that it comprises a device for monitoring the operation of said system depending on the control voltages of the single switches of all of the bypass circuits.

11. The system according to claim 7, characterized in that it comprises a device for monitoring the operation of said system depending on: the control voltages of all of the single switches, and the voltages supplied by all of the first comparators.

12. A rechargeable electrical energy storage module, comprising: at least one rechargeable electrical energy storage assembly, each comprising a plurality of capacitive-effect electrical energy storage devices connected to one another in series within said assembly; and for at least one, in particular each, storage assembly, a balancing system according to claim 1.

13. An electric or hybrid transport vehicle comprising one or more rechargeable electrical energy storage modules according to claim 12.

14. An electrical installation, such as an electric charging station for electric or hybrid transport vehicles, or a power supply station for a building, for a complex or for an electric/electronic communication device, or a station for regulating or smoothing electrical energy, comprising one or more rechargeable electrical energy storage modules according to claim 12.

Description

DESCRIPTION OF THE FIGURES AND EMBODIMENTS

[0096] Other advantages and features will emerge upon examination of the detailed description of entirely nonlimiting embodiments, and of the appended drawings, in which:

[0097] FIGS. 1a and 1b show basic overviews of two exemplary implementations of a balancing system with controlled resistance according to the prior art;

[0098] FIG. 2 is a depiction of the basic overview of a first exemplary implementation of a balancing system with controlled resistance according to the invention;

[0099] FIG. 3 is a depiction of the basic overview of a second exemplary implementation of a balancing system with controlled resistance according to the invention;

[0100] FIG. 4 is a schematic depiction of a nonlimiting exemplary implementation of a module for monitoring the operation of a system according to the invention;

[0101] FIG. 5 is a schematic depiction of another nonlimiting exemplary implementation of a module for monitoring the operation of a system according to the invention;

[0102] FIG. 6 is a schematic depiction of a nonlimiting exemplary implementation of a storage module according to the invention; and

[0103] FIGS. 7a-7d are nonlimiting exemplary implementations of a capacitive-effect electrical energy storage device.

[0104] It is readily understood that the embodiments that will be described hereinafter are in no way limiting. It will be possible in particular to imagine variants of the invention comprising only a selection of features described hereinafter, in isolation from the other features described, if this selection of features suffices to afford a technical advantage or to differentiate between the invention and the prior art. This selection comprises at least one preferably functional feature without structural detail, or with only a portion of the structural details if this portion alone suffices to afford a technical advantage or to differentiate between the invention and the prior art.

[0105] In the figures, elements common to a plurality of figures retain the same reference.

[0106] In the following examples, but in a manner that is in no way limiting for the invention, all of the storage devices DC.sub.i are considered to be identical and to have the same balancing voltage V.sub.eq. Of course, the invention is not limited to these examples, and it is possible to use storage devices DC.sub.i that are different from one another and that do not have the same balancing voltage.

[0107] FIGS. 1a and 1b are depictions of the basic circuit diagrams of two examples of a balancing system with controlled resistance according to the prior art.

[0108] FIGS. 1a and 1b show a storage assembly 100 comprising n capacitive-effect storage devices DC.sub.1, . . . , DC.sub.n that are connected to one another in series and are identical. The storage device DC.sub.1 is situated on the side of the smallest electrical potential, denoted V.sub.1.sup., of the storage assembly 100, and the storage device DC.sub.n is situated on the side of the greatest electrical potential, denoted V.sub.n.sup.+, of the storage assembly 100. The voltage between the terminals of the storage device DC.sub.i is denoted V.sub.i, and the voltage between the terminals of the storage assembly 100 is denoted V.

[0109] The system shown in FIGS. 1a and 1b comprises a balancing device with controlled resistance that is associated with each storage device DC.sub.i.

[0110] Hereinafter, so as not to overload the drawings, only the balancing device 102.sub.i, associated with the storage device DC.sub.i is shown in FIGS. 1a and 1b. The balancing devices of the other storage devices of the storage assembly 100 are on the same principle as the balancing device 102.sub.i, shown in FIGS. 1a and 1b, and are in particular identical to the balancing device 102.sub.i in the case where the storage devices DC.sub.i have one and the same balancing voltage V.sub.eq.

[0111] The balancing device 102.sub.i comprises a bypass circuit 104.sub.i, connected in parallel to the terminals of the storage device DC.sub.i and including a switch Q.sub.i in series with a balancing resistor R.sub.i.sup.eq.

[0112] The balancing device 102.sub.i also comprises a hysteresis comparator 106.sub.i, called first comparator, for controlling the state of the switch Q.sub.i. The first comparator 106.sub.i is formed by an operational amplifier 108.sub.i and two resistors R and R, the values of which resistors set the width of the hysteresis. The resistors R and R are chosen so as to be large enough for the current that passes through them to be negligible, typically R>10 k and R>10 k.

[0113] The operational amplifier 108.sub.i is referenced to the potentials, V.sub.i.sup.+ and V.sub.i.sup., across the terminals of the storage device DC.sub.i with which the balancing device 102.sub.i is associated.

[0114] In the example shown in FIG. 1a, the positive input (+) of the operational amplifier 108.sub.i is connected to the greatest potential V.sub.i.sup.+ across the terminals of the storage device DC.sub.i with which the balancing device 102.sub.i is associated. The negative input () of the operational amplifier 108.sub.i is connected to a voltage source 110.sub.i that is itself referenced to the smallest potential V.sub.i.sup. across the terminals of the storage device DC.sub.i.

[0115] In the example shown in FIG. 1a, the voltage source 110.sub.i supplies the balancing voltage V.sub.eq at which it is desired to bypass the storage device DC.sub.i.

[0116] In this case, the comparator 106.sub.i directly compares the voltage V.sub.i across the terminals of the storage device DC.sub.i with the balancing voltage V.sub.eq, and operates in the following manner: [0117] if V.sub.i (=V.sub.i.sup.+V.sub.i.sup.)<V.sub.eq, then the voltage supplied by the first comparator 106.sub.i denoted V.sub.i.sup.s, is equal to V.sub.i.sup. (=V.sub.sat local): in other words, if the voltage V.sub.i across the terminals of the storage device DC.sub.i is lower than the balancing voltage V.sub.eq, then V.sub.i.sup.s=V.sub.i.sup.; and [0118] if V.sub.i (=V.sub.i.sup.+V.sub.i.sup.)V.sub.eq, then V.sub.i.sup.s=V.sub.i.sup.+ (=+V.sub.sat local).

[0119] The voltage V.sub.i.sup.s is used to control the switch Q.sub.i into a closed state or into an open state.

[0120] In the example shown in FIG. 1a, the switch Q.sub.i may be an N-channel MOSFET transistor, the gate of which receives the voltage V.sub.i.sup.s: [0121] when V.sub.i.sup.s has the value V.sub.i.sup. (that is, when the voltage V.sub.i across the terminals of the storage device DC.sub.i is lower than the balancing voltage V.sub.eq), then the gate-source voltage is zero and the switch Q.sub.i is in the off state/open: the bypass circuit 104.sub.i is open and does not draw any current; and [0122] when V.sub.i.sup.s has the value V.sub.i.sup.+ (that is, when the voltage V.sub.i across the terminals of the storage device DC.sub.i is greater than or equal to the balancing voltage V.sub.eq), then the gate-source voltage is non-zero and the switch Q.sub.i is in the on state/closed: the bypass circuit 104.sub.i is closed and draws current that flows into the balancing resistor R.sub.i.sup.eq.

[0123] FIG. 1b provides another exemplary implementation of a balancing device with controlled resistance. The balancing device 112.sub.i of FIG. 1b comprises a voltage divider 114.sub.i arranged as a diversion to the terminals of the storage device DC.sub.i and formed by resistors R.sub.e and R.sub.e. The voltage divider 114.sub.i is used to adjust the voltage V.sub.i (V.sub.i=V.sub.i.sup.+V.sub.i.sup.) across the terminals of the storage device DC.sub.i. Indeed, from a practical point of view, the analogue electronic voltage sources have determined and set values. They therefore do not necessarily correspond to the value of the desired balancing voltage V.sub.eq for the storage device DC.sub.i. The comparator 106.sub.i thus receives, as input, not the voltage V.sub.i but an input voltage V.sub.i.sup.E1 such that V.sub.i.sup.E1=V.sub.i/D.sup.1, where D.sup.1 is the coefficient of division applied by the voltage divider 114.sub.i, such that:

[00003]$D^1=\frac{R_e+R_e^{}}{R_e}$

[0124] In this case, the source 110.sub.i supplies not the balancing voltage V.sub.eq, but a reference voltage, denoted V.sub.ref, such that V.sub.ref=V.sub.eq/D.sup.1.

[0125] In other words, we have:

[00004]$\frac{R_e}{R_e+R_e^{}}=\frac{V_{\mathrm{ref}}}{V_{\mathrm{eq}}}$

[0126] In other words, in the exemplary implementation shown, V.sub.refV.sub.eq, and

[00005]$V_{\mathrm{ref}}=V_{\mathrm{eq}}\left(\frac{R_e}{R_e+R_e^{}}\right)$

[0127] The balancing device 112.sub.i, shown in FIG. 1b, moreover comprises all of the elements of the balancing device 102.sub.i of FIG. 1a.

[0128] Unlike the device 102.sub.i of FIG. 1a, in the device 112.sub.i of FIG. 1b, the positive input (+) of the operational amplifier 108.sub.i is connected to said voltage divider 114.sub.i. The resistors R.sub.e and R.sub.e forming the voltage divider are chosen so as to be large enough for the current that passes through them to be negligible, typically R.sub.e>10 k and R.sub.e>10 k.

[0129] In this case, the voltage comparator 106.sub.i performs a comparison: [0130] of the reference voltage V.sub.ref (rather than the voltage V.sub.eq) [0131] with the input voltage V.sub.i.sup.E1, supplied by the voltage divider 114.sub.i.

[0132] In the examples described, the comparator 106.sub.i is a hysteresis comparator. Alternatively, the comparator 106.sub.i might not be a hysteresis comparator.

[0133] FIG. 2 is a depiction of the basic overview of a first non limiting exemplary implementation of a balancing system according to the invention.

[0134] The balancing system 200 of FIG. 2 comprises, for each storage device DC.sub.1, . . . , DC.sub.n, an identical balancing device with controlled resistance, since the storage devices DC.sub.1, . . . , DC.sub.n are identical.

[0135] So as not to overload the drawing, only the balancing device 202.sub.i, associated with the storage device DC.sub.i, is shown in FIG. 2.

[0136] The balancing device 202.sub.i comprises a bypass circuit 204.sub.i for the storage device DC.sub.i comprising the balancing resistor R.sub.i.sup.eq in series with the switch Q.sub.i. The bypass circuit 204.sub.i additionally comprises a second switch Q.sub.i, in series with the first switch Q.sub.i.

[0137] In the same manner as in the balancing device 112.sub.i of FIG. 1b, the first switch Q.sub.i is controlled by the voltage V.sub.i.sup.s supplied by the comparator 106.sub.i, with the use of the voltage divider 114.sub.i.

[0138] The switch Q.sub.i is a switch positioned in an open state/in the off state as long as the voltage across the terminals of the storage device DC.sub.i has not reached the balancing voltage V.sub.eq, and is otherwise closed/in the on state.

[0139] In the system 200 of FIG. 2, each balancing device 202.sub.i furthermore comprises a second switch Q.sub.i in series with the first switch Q.sub.i and the balancing resistor R.sub.i.sup.eq. The switch Q.sub.i is chosen and is controlled such that it remains closed/in the on state as long as the voltage V.sub.i across the terminals of the storage device DC.sub.i has not reached a predetermined switch-off voltage, denoted V.sub.dec, that is greater than the balancing voltage V.sub.eq, and is otherwise open/in the off state.

[0140] Each balancing device 202.sub.i furthermore comprises a second voltage comparator 206.sub.i for controlling the switch Q.sub.i. The comparator 206.sub.i is a hysteresis comparator. In particular, the second comparator 206.sub.i is formed by an operational amplifier 208.sub.i and two resistors R and R, the values of which resistors set the width of the hysteresis. The resistors R and R are chosen so as to be large enough for the current that passes through them to be negligible, typically R>10 k and R>10 k.

[0141] The operational amplifier 208.sub.i is referenced to the potentials, V.sub.i.sup.+ and V.sub.i.sup., across the terminals of the storage device DC.sub.i with which the balancing device 202.sub.i is associated.

[0142] In the example shown in FIG. 2, the positive input (+) of the operational amplifier 208.sub.i receives an input voltage, denoted V.sub.i.sup.E2, that is proportional to the voltage across the terminals of the storage device DC.sub.i through a voltage divider 214.sub.i formed by resistors R.sub.d and R.sub.d. The negative input () of the operational amplifier 208.sub.i is connected to the voltage source 110.sub.i, supplying the reference voltage V.sub.ref, which is itself referenced to the smallest potential, denoted V.sub.i.sup., across the terminals of the storage device DC.sub.i.

[0143] As a result, the second voltage divider 214.sub.i supplies a voltage V.sub.i.sup.E2 such that V.sub.i.sup.E=V.sub.i/D.sup.2, where D.sup.2 is the coefficient of division applied by the voltage divider 214.sub.i, such that:

[00006]$D^2=\frac{R_d+R_d^{}}{R_d}$

[0144] The voltage divider 214.sub.i must be dimensioned such that the coefficient D.sup.2 satisfies the following relationship:

[00007]$D^2=\frac{V_{\mathrm{dec}}}{V_{\mathrm{ref}}}$

[0145] In this case, the second voltage comparator 206.sub.i performs a comparison: [0146] of the reference voltage V.sub.ref delivered by the source 110.sub.i, with the second input voltage V.sub.i.sup.E2, supplied by the voltage divider 214.sub.i.

[0147] Thus, in the exemplary implementation shown in FIG. 2, the reference voltages used by the two comparators 106.sub.i and 206.sub.i are identical. However, for a given voltage across the terminals of the storage device DC.sub.i, the input voltage V.sub.i.sup.E1 used by the first comparator 106.sub.i for the comparison with the reference voltage V.sub.ref is greater than that V.sub.i.sup.E2 used by the second comparator 206.sub.i. Thus, the switch-off level V.sub.dec of the switch Q.sub.i is greater than the switch-on level V.sub.eq of the switch Q.sub.i.

[0148] The second comparator 206 operates in the following manner: [0149] if the second input voltage V.sub.i.sup.E<V.sub.ref, this means that V.sub.i<V.sub.dec: in this case the voltage supplied by the second comparator 206.sub.i, denoted V.sub.c.sup.s, is equal to V.sub.i.sup. (=V.sub.sat local); and [0150] if the second input voltage V.sub.i.sup.E2V.sub.ref, this means that V.sub.iV.sub.dec: in this case the voltage V.sub.c.sup.s supplied by the second comparator 206.sub.i is equal to V.sub.i.sup.+ (=+V.sub.sat local).

[0151] In these conditions, the switch Q.sub.i may be a P-channel MOSFET transistor, the gate of which receives the voltage V.sub.c.sup.s: [0152] when V.sub.c.sup.s has the value V.sub.i.sup., this means that the voltage V.sub.i has not reached the switch-off voltage V.sub.dec, then the gate-source voltage is zero and the switch Q.sub.i is closed/in the on state: the bypass circuit 204.sub.i is closed: the storage device DC.sub.i is bypassed depending on the state of the switch Q.sub.i; and [0153] when V.sub.c.sup.s has the value V.sub.i.sup.+, this means that the voltage V.sub.i has reached the switch-off voltage V.sub.dec, then the gate-source voltage is positive and, as a result, the switch Q.sub.i is in the off state/open: the bypass circuit 204.sub.i is open regardless of the state of the switch Q.sub.i and does not draw current: the storage device DC.sub.i is not bypassed.

[0154] FIG. 3 is a depiction of the basic overview of a second nonlimiting exemplary implementation of a balancing system according to the invention.

[0155] The balancing system 300 of FIG. 3 comprises the first comparator 106.sub.i and the second comparator 206.sub.i of the system 200 of FIG. 2.

[0156] The balancing system 300 furthermore comprises, for each storage device DC.sub.1, . . . , DC.sub.n, an identical active balancing device with controlled resistance.

[0157] So as not to overload the drawing, only the balancing device 302.sub.i, associated with the storage device DC.sub.i, is shown in FIG. 3.

[0158] The balancing device 302.sub.i comprises a bypass circuit 304.sub.i for the storage device DC.sub.i, comprising the balancing resistor R.sub.i.sup.eq in series with a single switch, namely the switch Q.sub.i. In the system 300, the switch Q.sub.i is controlled depending both on the voltage V.sub.i.sup.s supplied by the first comparator 106.sub.i and on the voltage V.sub.c.sup.s supplied by the second comparator 206.sub.i.

[0159] To this end, the balancing device 302.sub.i comprises a control means receiving, on the one hand, the voltage V.sub.i.sup.s supplied by the first comparator 106.sub.i and, on the other hand, the voltage V.sub.c.sup.s supplied by the second comparator 206.sub.i. In particular, the control means is a bipolar transistor, denoted J.sub.i, such as a PNP bipolar transistor that is closed/in the on state by default, and connected such that: [0160] the base of the transistor J.sub.i receives the voltage V.sub.c.sup.s, [0161] the collector of the transistor J.sub.i receives the voltage V.sub.i.sup.s and [0162] the emitter of the transistor J.sub.i controls the switch Q.sub.i, through a control voltage denoted V.sub.i.sup.c.

[0163] As described above, the switch Q.sub.i may be an N-channel MOSFET transistor.

[0164] In these conditions, the switch Q.sub.i of the bypass circuit 304.sub.i is controlled in the following manner: [0165] if the voltage V.sub.i across the terminals of the storage device DC.sub.i has not reached the balancing voltage V.sub.eq, then V.sub.i.sup.s=V.sub.i.sup. and V.sub.c.sup.s=V.sub.i.sup.. As a result, the bipolar transistor J.sub.i is in the on state/closed and the voltage V.sub.i.sup. arrives at the switch Q.sub.i, which is then in the off state/open: the bypass circuit 304.sub.i does not allow the current to flow; [0166] if the voltage V.sub.i across the terminals of the storage device DC.sub.i has reached the balancing voltage V.sub.eq, but not the switch-off voltage V.sub.dec, then V.sub.i.sup.s=V.sub.i.sup.+ and V.sub.c.sup.s=V.sub.i.sup.. As a result, the bipolar transistor J.sub.i is in the on state and the voltage V.sub.i.sup.+ arrives at the switch Q.sub.i, which is then in the on state/closed: the bypass circuit 304.sub.i allows the current to flow and the storage device DC.sub.i is bypassed; and [0167] if the voltage V.sub.i across the terminals of the storage device DC.sub.i has reached the switch-off voltage V.sub.dec, then V.sub.i.sup.s=V.sub.i.sup.+ and V.sub.c.sup.s=V.sub.i.sup.+. As a result, the bipolar transistor J.sub.i is in the off state and the voltage V.sub.i.sup. arrives at the switch Q.sub.i through a resistor R.sub.i.sup.j connecting the gate of the switch Q.sub.i to the potential V.sub.i.sup.. The switch Q.sub.i is then in the off state/open: the bypass circuit 304.sub.i is open and does not allow the current to flow.

[0168] Alternatively to what is described in FIGS. 2 and 3, it is possible to use a second comparator that is not a hysteresis comparator.

[0169] It is also possible to use an individual voltage source for each comparator. The individual voltage sources may supply one and the same reference voltage or different reference voltages.

[0170] According to another alternative, it is possible to use a second comparator that is an inverting comparator. In this case, the second switch Q.sub.i may be for example an N-channel MOSFET transistor and the control means J.sub.i may be an NPN bipolar transistor.

[0171] According to another alternative, it is possible not to use a voltage divider for the first comparator, as shown in FIG. 1a. In this case, the first comparator receives, as input, and compares with one another: [0172] the voltage V.sub.i across the terminals of the storage device DC.sub.i and [0173] the balancing voltage V.sub.eq.

[0174] Alternatively or in addition, it is possible not to use a voltage divider for the second comparator. In this case, the second comparator receives, as input, and compares with one another: [0175] the voltage V.sub.i across the terminals of the storage device DC.sub.i and [0176] the switch-off voltage V.sub.dec.

[0177] FIG. 4 is a schematic depiction of an exemplary implementation of a monitoring module able to be implemented in the system according to the invention, and in particular in the system 200 of FIG. 2.

[0178] The monitoring module 400, shown in FIG. 4, takes as input, for each balancing device 202.sub.i, the control voltage V.sub.c.sup.s supplied by the second comparator 206.sub.i and the voltage V.sub.i.

[0179] It will be recalled that each voltage V.sub.c.sup.s=V.sub.i.sup. when the bypass circuit has not been switched off, and V.sub.c.sup.s=V.sub.i.sup.+ in the opposite case.

[0180] The monitoring module 400 comprises a weighted summer 402 taking a weighted sum of all of the V.sub.c.sup.s.

[0181] The monitoring module 400 also receives the voltage V across the terminals of the storage assembly (V=V.sub.n.sup.+V.sub.1.sup.).

[0182] The monitoring module 400 furthermore comprises a voltage comparator 404 comparing the weighted sum voltage supplied by the weighted summer 402 with the voltage V across the terminals of the storage assembly.

[0183] As long as all of the bypass circuits have not all been switched off, the voltage supplied by the summer 402 will be lower than the voltage V across the terminals of the storage assembly. When all of the bypass circuits are switched off, the voltage supplied by the summer 402 will be equal to the voltage V across the terminals of the storage assembly.

[0184] The output of the comparator 404 may be used to signal the result of the comparison, for example with the aid of an indicator light 406 powered by the output of the comparator 404.

[0185] The comparator 404 may be referenced to the potentials (V.sub.1.sup. and V.sub.n.sup.+) across the terminals of the storage assembly 100.

[0186] Alternatively, the comparator 404 may compare the voltage supplied by the first summer 402 with a threshold voltage V.sub.threshold, taking into account a voltage V representing a safety margin, such that:

V.sub.threshold=VV.

[0187] According to yet another alternative, the voltage V representing a safety margin may be added to the weighted sum supplied by the summer 402, directly in said summer 402, or by another summer arranged in cascade with the summer 402.

[0188] The voltage V representing a safety margin may be greater than or equal to 50 mV, this value typically representing the expected precision of the analogue electronics.

[0189] FIG. 5 is a schematic depiction of another exemplary implementation of a monitoring module able to be implemented in the system according to the invention, and in particular in the system 300 of FIG. 3.

[0190] The monitoring module 500 comprises, for each storage device DC.sub.i, a comparator 502.sub.i, referenced to the potentials V.sub.n.sup.+ and V.sub.1.sup. across the terminals of the storage assembly 100 and receiving: [0191] at its positive input, the voltage V.sub.i.sup.s supplied by the first comparator 106.sub.i associated with said storage device DC.sub.i and [0192] at its negative input, the voltage V.sub.i.sup.c supplied by the control means J.sub.i associated with said storage device DC.sub.i.

[0193] Each comparator 502.sub.i therefore compares the voltages V.sub.i.sup.s and V.sub.i.sup.c such that, if V.sub.i.sup.sV.sub.i.sup.c, the output voltage of the comparator has the value V.sub.1.sup., and, if V.sub.i.sup.s>V.sub.i.sup.c, the output voltage of the comparator has the value V.sub.n.sup.+.

[0194] Each comparator 502.sub.i controls a switch, denoted K.sub.i, which may be for example an NPN bipolar transistor, and which is open by default and which is closed when the voltage supplied by the comparator is equal to V.sub.n.sup.+.

[0195] The switches K.sub.1, . . . , K.sub.n, controlled by the comparators 502.sub.1, . . . , 502.sub.n, respectively, are connected to one another in series and to a resistor R.sub.K, between the potentials V.sub.n.sup.+ and V.sub.1.sup..

[0196] Thus, when there is at least one switch K.sub.i that is open, then no current flows into the resistor R.sub.K, and the voltage V.sub.K at the negative terminal of the resistor R.sub.K has the value V.sub.n.sup.+, this corresponding to a high state (non-zero voltage with respect to V.sub.1.sup.). When all of the switches K.sub.i are closed, then a current flows through the resistor R.sub.K, and the voltage V.sub.K at the negative terminal of the resistor R.sub.K has the value V.sub.1.sup., this corresponding to a low state (zero voltage with respect to V.sub.1.sup.).

[0197] The resistor R.sub.K is an arbitrary resistor with a value that is large enough, for example with a value of greater than 10 k, to limit the current that passes through all of the switches K.sub.1, . . . , K.sub.n.

[0198] This voltage V.sub.K may be used to monitor the operation of the balancing system, for example by turning on an indicator light (not shown in FIG. 5).

[0199] Alternatively, each comparator 502.sub.i may be local to the balancing device 302.sub.i of each storage device DC.sub.i.

[0200] FIG. 6 is a schematic depiction of a non limiting exemplary implementation of a storage module according to the invention.

[0201] The storage module 600, shown in FIG. 6, comprises a plurality of storage assemblies 100.sup.1, . . . , 100.sup.m each comprising a plurality of storage devices connected to one another in series.

[0202] The assemblies 100.sup.1, . . . , 100.sup.m may be connected to one another in series or in parallel.

[0203] In the example shown, each assembly 100.sup.j comprises n storage devices DC.sub.1.sup.j, . . . , DC.sub.n.sup.j.

[0204] A balancing device 302.sub.i.sup.j, such as for example the balancing device 302.sub.i of FIG. 3, is connected to each storage device DC.sub.i.sup.j, 1in and 1jm.

[0205] A monitoring module 400.sup.j, such as for example the monitoring module 400 of FIG. 4, is furthermore associated with each assembly 100.sup.j.

[0206] The storage module 600 may be used in a rechargeable electric or hybrid transport vehicle, which may be a bus, a car, a tram, a boat, a lorry, a cable car, a goods lift, a crane, etc.

[0207] The storage module 600 may also be used in an electrical installation, which may be: [0208] an electric charging station for electric or hybrid transport vehicles, [0209] a power supply station for a building, for a complex or for an electric/electronic communication device, or [0210] a station for regulating, smoothing or buffer storing electrical energy.

[0211] FIGS. 7a-7d are nonlimiting exemplary implementations of a capacitive-effect electrical energy storage device.

[0212] Each storage device DC.sub.i may be any one of the storage devices described with reference to FIGS. 7a-7d.

[0213] The storage device DC.sub.i shown in FIG. 7a comprises a single supercapacitor C. It is this device example that has been considered in the examples described above with reference to FIGS. 1-6.

[0214] Of course, the invention is not limited to this example.

[0215] For example, the storage device DC.sub.i shown in FIG. 7b comprises a plurality of supercapacitors C connected in series.

[0216] The storage device DC.sub.i shown in FIG. 7c comprises a plurality of supercapacitors C connected in parallel.

[0217] The storage device DC.sub.i shown in FIG. 7d comprises a group of one of more supercapacitors C connected in series with a group of at least two supercapacitors connected in parallel with one another.

[0218] Of course, the invention is not limited to the examples described above.