Power controllers and power converters with configurable feedback loop for different nominal output voltages

Abstract

A power controller is in use of a power converter whose output voltage can be regulated at a first nominal output voltage or a second nominal output voltage less than the first nominal output voltage. An ON-time controller controls an ON time of a driving signal provided to a power switch according to a compensation signal. A frequency controller controls, based on the compensation signal and a feedback signal, a switching frequency of the driving signal. If the compensation signal has an input waveform and when the output voltage is regulated at the first or second nominal output voltage, the frequency controller provides first or second settling time to stabilize the switching frequency, respectively. The second settling time is longer than the first settling time.

Claims

1. A power controller for a power converter converting an input voltage into an output voltage, wherein the power converter includes a primary winding, a secondary winding and an auxiliary winding inductively coupled to each other, the power controller comprising: a switch driver for providing a driving signal to a power switch to control an inductor current through the primary winding; and an ON-time controller for controlling an ON time of the driving signal according to a compensation signal, wherein the compensation signal is generated by comparing the output voltage with a first reference voltage; and a frequency controller for controlling a switching frequency of the driving signal based on the compensation signal and a feedback signal at a feedback node coupled to the auxiliary winding, the frequency controller comprising: a low-pass filter for low-pass filtering the compensation signal to generate a delayed compensation signal; a frequency generator for determining the switching frequency according to the delayed compensation signal; and an output voltage detector, for comparing the feedback signal with a second reference voltage, to control the low-pass filter.

2. The power controller as claimed in claim 1, wherein the output voltage detector disables the low-pass filter when the power converter regulates the output voltage at a first nominal output voltage, and enables the low-pass filter when the power converter regulates the output voltage at a second nominal output voltage less than the first nominal output voltage.

3. The power controller as claimed in claim 2, wherein the output voltage detector samples the feedback signal to generate a sample result, and compares the sample result with the second reference voltage.

4. The power controller as claimed in claim 1, wherein the low-pass filter comprises a resistor, a capacitor and a switch controlled by the output voltage detector.

5. The power controller as claimed in claim 4, wherein the switch is connected in parallel with the resistor.

6. The power controller as claimed in claim 4, wherein the switch is connected in series between the resistor and the capacitor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. These drawings are not necessarily drawn to scale. Likewise, the relative sizes of elements illustrated by the drawings may differ from the relative sizes depicted.

(2) The invention can be more fully understood by the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

(3) FIG. 1, according to embodiments of the invention, demonstrates a power converter with a flyback topology, capable of being a USB charger to charge a rechargeable apparatus;

(4) FIG. 2 demonstrates a power controller capable of replacing the power controller in FIG. 1 according to embodiments of the invention;

(5) FIGS. 3A, 3B, 3C and 3D demonstrates four low-pass filters;

(6) FIG. 4 shows frequency curve CV.sub.f;

(7) FIG. 5A shows that compensation signal V.sub.COMP jumps up abruptly from V.sub.COMP1 to V.sub.COMP2 at moment t.sub.STEP;

(8) FIGS. 5B and 5C show the step responses of switching frequency f.sub.SW when output voltage V.sub.OUT is regulated at 20V and 5V respectively;

(9) FIG. 6 demonstrates a power controller capable of replacing the power controller in FIG. 1 according to embodiments of the invention; and

(10) FIG. 7 shows frequency curves CV.sub.f-5V and CV.sub.f-20V.

DETAILED DESCRIPTION

(11) A USB charger is used as an embodiment of the invention, but the invention is not limited to. Embodiments of the invention include other kinds of switching mode power supplies, and the disclosure of this invention is not on purpose to limit the scope of the invention.

(12) FIG. 1, according to embodiments of the invention, demonstrates a power converter 10 with a flyback topology, capable of being a USB charger to charge rechargeable apparatus 13. Bridge rectifier 11 rectifies alternating-current (AC) voltage V.sub.AC to provide an input voltage V.sub.IN and an input ground voltage, which power converter 10 converts to output voltage V.sub.OUT and an output ground voltage. Rechargeable apparatus 13 sends selection signal S.sub.SEL, based on which power converter 10 regulates output voltage V.sub.OUT at one of two or more nominal output voltages. In other words, the nominal output voltage of power converter 10 is configurable, determined by selection signal S.sub.SEL. In this following specification, two nominal output voltages are, but are not limited to be, 20V and 5V respectively.

(13) Based on selection signal S.sub.SEL, reference voltage generator 16 provides reference voltage V.sub.REF1, with which comparator 18 compares output voltage V.sub.OUT to produce compensation voltage V.sub.COMP at compensation node COMP via photo coupler 20, so as to provide feedback control to power controller 12 and to regulate output voltage V.sub.OUT at either 5V or 20V as selection signal S.sub.SEL selects.

(14) Power converter 10 has a transformer with primary winding PRM, secondary winding SEC and auxiliary winding AUX, inductively coupled to each other. Power controller 12 generates driving signal S.sub.DRV, based on compensation signal V.sub.COMP at compensation node COMP, to turn ON or OFF power switch 14, which accordingly conducts or stops inductor current I.sub.PRM flowing through primary winding PRM. Power controller 12 has feedback node FB connected via resistors RA1 and RA2 to auxiliary winding AUX. Feedback signal V.sub.FB at feedback node FB, under some circumstances, represents the voltage drop across auxiliary winding AUX.

(15) According to an embodiment of the invention, power controller 12 controls switching frequency f.sub.SW of driving signal S.sub.DRV based on compensation signal V.sub.COMP and feedback signal V.sub.FB. The relationship between compensation signal V.sub.COMP and switching frequency f.sub.SW can be represented by a frequency curve demonstrated in a V.sub.COMP-to-f.sub.SW chart. When compensation signal V.sub.COMP becomes less than a predetermined fold voltage V.sub.FOLD, the frequency curve in the V.sub.COMP-to-f.sub.SW chart indicates that switching frequency f.sub.SW reduces according to a frequency-reduction slope SL. Power controller 12 at the same time detects output voltage V.sub.OUT of power converter 10 from feedback signal V.sub.FB to determine whether the present nominal output voltage is 20V or 5V. If output voltage V.sub.OUT is determined to be about 20V, power controller 12 determines switching frequency f.sub.SW directly based on compensation signal V.sub.COMP and the frequency curve. If output voltage V.sub.OUT is determined to be about 5V however, compensation signal V.sub.COMP is additionally low-pass filtered before being forwarded to determine switching frequency f.sub.SW. For a steady state, the frequency curve is the same regardless of whether the nominal output voltage is 5V or 20V. Nevertheless, if compensation signal V.sub.COMP varies to have an input waveform, a step input for example, the settling time for switching frequency f.sub.SW being stabilized when nominal output voltage is 5V will be longer than that when nominal output voltage is 20V.

(16) According to another embodiment of the invention, power controller 12 controls switching frequency f.sub.SW of driving signal S.sub.DRV based on compensation signal V.sub.COMP and feedback signal V.sub.FB. The relationship between compensation signal V.sub.COMP and switching frequency f.sub.SW can be represented by a frequency curve demonstrated in a V.sub.COMP-to-f.sub.SW chart. When compensation signal V.sub.COMP becomes less than a predetermined fold voltage V.sub.FOLD, the frequency curve in the V.sub.COMP-to-f.sub.SW chart indicates that switching frequency f.sub.SW reduces according to a frequency-reduction slope SL. Power controller 12 at the same time detects output voltage V.sub.OUT of power converter 10 from feedback signal V.sub.FB to determine whether the present nominal output voltage is 20V or 5V. If output voltage V.sub.OUT is determined to be about 20V, meaning the nominal output voltage is 20V, frequency-reduction slope SL has a first drop-off rate; and if output voltage V.sub.OUT is determined to be about 5V, frequency-reduction slope SL has a second drop-off rate less than the first drop-off rate. In one embodiment of the invention, the predetermined fold voltage V.sub.FOLD is a constant, unchanged even if output voltage V.sub.OUT varies due to the change of the nominal output voltage.

(17) FIG. 2 demonstrates a power controller 12a capable of replacing power controller 12 in FIG. 1 according to embodiments of the invention.

(18) Power controller 12a includes a switch driver 38a, an ON-time controller 31a, a frequency controller 30a and a SR flip-flop 36a.

(19) Switch driver 38a amplifies PWM signal S.sub.PWM to become driving signal S.sub.DRV with suitable voltage and current that drives power switch 14 in FIG. 1. PWM signal S.sub.PWM substantially equals to driving signal S.sub.DRV in view of their logic values, and they might be different in logic voltage levels.

(20) ON-time controller 31a controls an ON time of driving signal S.sub.DRV according to compensation signal V.sub.COMP, and has an attenuator 32a and a comparator 34a. Attenuator 32a generates output V.sub.COMP-SCL by attenuating compensation signal V.sub.COMP. For example, attenuator 32a might include a voltage-divider to attenuate compensation signal V.sub.COMP. When current-sense signal V.sub.CS at current-sense node CS exceeds output V.sub.COMP-SCL, comparator 34a resets SR flip-flop 36a, making PWM signal S.sub.PWM having a logic value of “0” and ending ON time T.sub.ON of power switch 14.

(21) Frequency controller 30a, based upon compensation signal V.sub.COMP and feedback signal V.sub.FB, provides clock signal S.sub.CLK to periodically set SR flip-flop 36a, making PWM signal S.sub.PWM have a logic value of “1” and starting ON time T.sub.ON of power switch 14. Frequency controller 30a includes an output voltage detector 41a, a low-pass filter 40a and a frequency generator 42a.

(22) Output voltage detector 41a, based on the timing provided by PWM signal S.sub.PWM, samples feedback signal V.sub.FB and compares the sample result with reference voltage V.sub.REF2, so as to roughly know whether output voltage V.sub.OUT is 20V or 5V. For example, if output voltage V.sub.OUT is about 20V, the sample result is configured to be higher than reference voltage V.sub.REF2, so signal S.sub.LV from output voltage detector 41a has logic value of “0”, and the present nominal voltage is expected to be 20V. If output voltage V.sub.OUT is about 5V, the sample result is configured to be less than reference voltage V.sub.REF2, so signal S.sub.LV has logic value of “1”, and the present nominal voltage is expected to be 5V.

(23) The filtering function of low-pass filter 40a is configurable, based on the logic value of signal S.sub.LV. Output voltage detector 41a can dis-enable or enable the filtering function of low-pass filter 40a. For example, if signal S.sub.LV is “1” in logic, low-pass filter 40a low-pass filters compensation signal V.sub.COMP to provide delayed signal V.sub.COMP-LP. In the opposite, if the signal S.sub.LV is “0” in logic, low-pass filter 40a stops low-pass filtering, and passes compensation signal V.sub.COMP substantially without delay, such that delayed signal V.sub.COMP-LP is about equal to compensation signal V.sub.COMP. FIGS. 3A, 3B, 3C and 3D demonstrates low-pass filters 40aa, 40ab, 40ac and 40ad, each of which could embody the low-pass filter 40a according to the invention. Each of low-pass filters 40aa and 40ac performs low-pass filtering by using a resistor-capacitor circuit, and each of low-pass filters 40ab and 40ad does by using a switched capacitor circuit. In each of low-pass filters 40aa and 40ab, signal S.sub.LV controls a bypass switch SW.sub.P, which, when being turned ON, directly makes compensation signal V.sub.COMP delayed signal V.sub.COMP-LP, and disables the function of low-pass filtering. Analogously, in each of low-pass filters 40ac and 40ad, signal S.sub.LV controls an isolation switch SW.sub.ISO, which, when being turned OFF, separates a filtering capacitor from the signal path in the respective low-pass filter, so as to disables the function of low-pass filtering.

(24) Low-pass filter 40a according to embodiments of the invention is not limited to have no function of low-pass filtering when the signal S.sub.LV is “0”. For example, when the signal S.sub.LV is “0” low-pass filter 40a could be a low-pass filter weaker than low-pass filter 40a could be when the signal S.sub.LV is “1”. Preferably, the direct current response of low-pass filter 40a does not change if signal S.sub.LV toggles its logic value, but a high-frequency response of low-pass filter 40a weakens when signal S.sub.LV switches from logic “0” to logic “1”.

(25) Frequency generator 42a in FIG. 2 provides clock signal S.sub.CLK according to delayed signal V.sub.COMP-LP. Clock signal S.sub.CLK substantially determines the moment when power switch 14 is turned ON, so as to decide switching frequency f.sub.SW of PWM signal S.sub.PWM and driving signal S.sub.DRV. FIG. 4 shows frequency curve CV.sub.f, which demonstrates the relationship between delayed signal V.sub.COMP-LP and switching frequency f.sub.SW that frequency generator 42a provides. As shown in FIG. 4, frequency generator 42a makes switching frequency f.sub.SW about a constant maximum frequency f.sub.MAX when delayed signal V.sub.COMP-LP exceeds fold voltage V.sub.FOLD. When delayed signal V.sub.COMP-LP decreases to be less than fold voltage V.sub.FOLD, switching frequency f.sub.SW reduces according to a frequency-reduction slope SL, the tilted slope of frequency curve CV.sub.f between fold voltage V.sub.FOLD and light-load voltage V.sub.L in FIG. 4. If delayed signal V.sub.COMP-LP becomes less than light-load voltage V.sub.L, switching frequency f.sub.SW remains at about a constant minimum frequency f.sub.MIN.

(26) FIG. 5A shows that compensation signal V.sub.COMP jumps up abruptly from V.sub.COMP1 to V.sub.COMP2 at moment t.sub.STEP and has an input waveform about representing a step input. FIGS. 5B and 5C show the step responses of switching frequency f.sub.SW when output voltage V.sub.OUT is regulated at 20V and 5V respectively. Shown in FIG. 5B where output voltage V.sub.OUT is about 20V, it, in response to the step input of compensation signal V.sub.COMP in FIG. 5A, costs settling time T.sub.SETTLE1 for frequency controller 30a to stabilize switching frequency f.sub.SW, which begins from first frequency f.sub.1 and finally stabilizes at second frequency f.sub.2. Shown in FIG. 5C where output voltage V.sub.OUT is about 5V, switching frequency f.sub.SW, in response to the step input of compensation signal V.sub.COMP in FIG. 5A, varies from first frequency f.sub.1 and finally stabilizes at second frequency f.sub.2. Settling time T.sub.SETTLE2 in FIG. 5C is longer than settling time T.sub.SETTLE1 in FIG. 5B, nevertheless. As detailed before, low-pass filter 40a in FIG. 2 is enabled when output voltage V.sub.OUT is about 5V, and dis-enabled when output voltage V.sub.OUT is 20V. Therefore, the change in compensation signal V.sub.COMP needs longer signal propagation delay to actually affect frequency generator 42a when output voltage V.sub.OUT is about 5V than it does when output voltage V.sub.OUT is about 20V. Therefore, settling time T.sub.SETTLE2 is longer than settling time T.sub.SETTLE1 as shown in FIGS. 5A, 5B and 5C.

(27) FIGS. 5A, 5B and 5C also show that in response to the step input of compensation signal V.sub.COMP in FIG. 5A, switching frequency f.sub.SW stabilizes finally at second frequency f.sub.2 no matter whether output voltage V.sub.OUT is regulated at 5V or 20V.

(28) The input waveform of compensation signal V.sub.COMP is not limited to be a step input, however. For example, compensation signal V.sub.COMP might have an input waveform representing a unit pulse. In response to that unit pulse, switching frequency f.sub.SW drifts away from an original frequency and, after a settling time, comes back to and settles at the original frequency. The settling time needed when nominal output voltage is 5V is longer than that needed when nominal output voltage is 20V, because longer signal propagation delay is needed when nominal output voltage is 5V.

(29) The low-pass filtering provided when output voltage V.sub.OUT is about 5V slows the response of switching frequency f.sub.SW to the change in compensation signal V.sub.COMP, and therefore possibly stabilizes the feedback control more.

(30) FIG. 6 demonstrates a power controller 12b capable of replacing power controller 12 in FIG. 1 according to embodiments of the invention. The same or similar components commonly shared by power controllers 12b and 12a can be understood in light of the aforementioned teaching regarding to power controller 12a and will not be detailed redundantly for brevity.

(31) Power controller 12b, unlike power controller 12a, has frequency controller 30b with output voltage detector 41a and frequency generator 42b.

(32) Output voltage detector 41a, based on the timing provided by PWM signal S.sub.PWM, detects output voltage V.sub.OUT via feedback node FB and auxiliary winding AUX, so as to roughly know whether output voltage V.sub.OUT is 20V or 5V. For example, if output voltage V.sub.OUT is about 20V, signal S.sub.LV has logic value of “0”, and the present nominal voltage is expected to be 20V. If output voltage V.sub.OUT is about 5V, signal S.sub.LV has logic value of “1”, and the present nominal voltage is expected to be 5V.

(33) Frequency generator 42b provides clock signal S.sub.CLK according to compensation signal V.sub.COMP and signal S.sub.LV. Clock signal S.sub.CLK substantially determines the moment when power switch 14 is turned ON, so as to decide switching frequency f.sub.SW of PWM signal S.sub.PWM and driving signal S.sub.DRV. FIG. 7 shows frequency curves CV.sub.f-5V and CV.sub.f-20V, different relationships between compensation signal V.sub.COMP and switching frequency f.sub.SW that frequency generator 42b provides. Frequency generator 42b employs frequency curve CV.sub.f-5V when output voltage V.sub.OUT is about 5V, and frequency curve CV.sub.f-20V when output voltage V.sub.OUT is about 20V. Take frequency curve CV.sub.f-20V as an example, frequency generator 42b makes switching frequency f.sub.SW about a constant maximum frequency f.sub.MAX when compensation signal V.sub.COMP exceeds fold voltage V.sub.FOLD. When compensation signal V.sub.COMP decreases to be less than fold voltage V.sub.FOLD, switching frequency f.sub.SW reduces according to a frequency-reduction slope SL.sub.20V, the tilted slope of frequency curve CV.sub.f-20V between fold voltage V.sub.FOLD and light-load voltage V.sub.L-20V in FIG. 7. If compensation signal V.sub.COMP becomes less than light-load voltage V.sub.L-20V, switching frequency f.sub.SW remains at about a constant minimum frequency f.sub.MIN. Frequency curve CV.sub.f-5V in FIG. 7, unlike frequency curve CV.sub.f-20V, reduces switching frequency f.sub.SW according to a frequency-reduction slope SL.sub.5V, the tilted slope of frequency curve CV.sub.f-5V between fold voltage V.sub.FOLD and light-load voltage V.sub.L-5V, while, as shown in FIG. 7, frequency-reduction slope SL.sub.5V has a drop-off rate less than frequency-reduction slope SL.sub.20V does. Frequency-reduction slopes SL.sub.20V and SL.sub.5V commonly share fold voltage V.sub.FOLD, and light-load voltage V.sub.L-5V is less than light-load voltage V.sub.L-20V.

(34) In other words, output voltage detector 41a makes frequency generator 42b respond to compensation signal V.sub.COMP to synthesize switching frequency f.sub.SW based on frequency-reduction slop SL.sub.20V when output voltage V.sub.OUT is regulated at about 20V, and based on frequency-reduction slop SL.sub.5V when output voltage V.sub.OUT is regulated at about 5V, where frequency-reduction slop SL.sub.5V, in comparison with frequency-reduction slop SL.sub.20V, has a less drop-off rate.

(35) As frequency-reduction slop SL.sub.5V is less tilted than frequency-reduction slop SL.sub.20V, switching frequency f.sub.SW could less respond to the change in compensation signal V.sub.COMP when output voltage V.sub.OUT is about 5V than it does when output voltage V.sub.OUT is about 20V, to form an adjustable control loop fitting different nominal output voltages.

(36) While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.