SUCCESSIVE APPROXIMATION TYPE AD CONVERTER AND SENSOR DEVICE

Abstract

A successive approximation type AD converter includes an in-phase voltage detection and supply circuit that supplies an in-phase voltage obtained by impedance voltage division of a first input analog signal and a second input analog signal to a first capacitance DA converter and a second capacitance DA converter. The first capacitance DA converter samples the first input analog signal with reference to the in-phase voltage, and the second capacitance DA converter samples the second input analog signal with reference to the in-phase voltage. After the sampling period ends, a comparator compares the output of the first capacitance DA converter and the output of the second capacitance DA converter, output voltages of the first capacitance DA converter and the second capacitance DA converter are changed by the control signal of a successive approximation logic unit on the basis of a comparison result, and comparison processing is repeated.

Claims

1. A successive approximation type AD converter comprising: a first capacitance DA converter that samples a first input analog signal and outputs a voltage corresponding to a sampled value; a second capacitance DA converter that samples a second input analog signal and outputs a voltage corresponding to a sampled value; a comparator that compares an output of the first capacitance DA converter and an output of the second capacitance DA converter; a successive approximation logic unit that supplies a control signal to the first capacitance DA converter and the second capacitance DA converter on the basis of a comparison result of the comparator; and an in-phase voltage detection and supply circuit that, in a sampling period, supplies an in-phase voltage obtained by impedance voltage division of the first input analog signal and the second input analog signal to the first capacitance DA converter and the second capacitance DA converter, wherein the first capacitance DA converter samples the first input analog signal with reference to the in-phase voltage in the sampling period, the second capacitance DA converter samples the second input analog signal with reference to the in-phase voltage, after the sampling period ends, the comparator compares the output of the first capacitance DA converter and the output of the second capacitance DA converter, output voltages of the first capacitance DA converter and the second capacitance DA converter are changed by the control signal of the successive approximation logic unit on the basis of a comparison result, comparison processing is repeated, and thereby, a digital signal of a successive approximation result is output.

2. The successive approximation type AD converter according to claim 1, wherein the first capacitance DA converter and the second capacitance DA converter comprise a plurality of capacitance elements weighted with a constant coefficient, and a switch array that connects each of the capacitance elements and reference voltages according to a control signal of the successive approximation logic unit.

3. The successive approximation type AD converter according to claim 2, wherein the reference voltages to be supplied to the first capacitance DA converter and the second capacitance DA converter are a first reference voltage and a second reference voltage lower than the first reference voltage.

4. The successive approximation type AD converter according to claim 1, wherein the impedance voltage division is performed by using two resistance elements connected between the first input analog signal and the second input analog signal.

5. The successive approximation type AD converter according to claim 1, wherein the first analog input signal and the second analog input signal are signals having an in-phase component and a differential component.

6. The successive approximation type AD converter according to claim 1, wherein the impedance voltage division is performed by using two capacitance elements connected between the first input analog signal and the second input analog signal.

7. The successive approximation type AD converter according to claim 1, further comprising a switch that switches between the in-phase voltage detection and supply circuit and a common voltage, wherein a common voltage can be supplied to the first DA converter and the second DA converter.

8. The successive approximation type AD converter according to claim 1, wherein the in-phase voltage detection and supply circuit includes the first capacitance DA converter and the second capacitance DA converter, and performs impedance voltage division by using a capacitance element of the first capacitance DA converter and a capacitance element of the second capacitance DA converter.

9. The successive approximation type AD converter according to claim 8, wherein the capacitance element of the first capacitance DA converter and the capacitance element of the second capacitance DA converter are charged and discharged at least one time using a DC potential.

10. The successive approximation type AD converter according to claim 8, wherein the capacitance element of the first capacitance DA converter and the capacitance element of the second capacitance DA converter are charged and discharged at least one time using a ground potential.

11. The successive approximation type AD converter according to claim 1, wherein the capacitance elements are further connected to each of output sides of the first capacitance DA converter and the second capacitance DA converter, and a resistance DA converter is connected to the capacitance elements.

12. A successive approximation type AD converter of differential input, the successive approximation type AD converter comprising: a first capacitance DA converter; a second capacitance DA converter; a comparator; a successive approximation logic unit; and an in-phase voltage detection and supply circuit, wherein the in-phase voltage detection and supply circuit performs impedance voltage division with respect to a first input analog signal and a second input analog signal in a sampling period to connect the result to a first terminals of the first capacitance DA converter and the second capacitance DA converter, the first input analog signal and the second input analog signal are connected to second terminals of the first capacitance DA converter and the second capacitance DA converter and sampling is performed, after the sampling period ends, the comparator compares the output of the first capacitance DA converter and the output of the second capacitance DA converter, output values of the first capacitance DA converter and the second capacitance DA converter are changed by the control signal of the successive approximation logic unit on the basis of a comparison result, successive approximation processing is repeated, and thereby, a digital value is output.

13. A sensor device comprising a sensor that outputs a differential detection signal, and a successive approximation type AD converter in which the differential detection signal of the sensor is input, wherein the successive approximation type AD converter comprises: a first capacitance DA converter that samples a first input analog signal and outputs a voltage corresponding to a sampled value; a second capacitance DA converter that samples a second input analog signal and outputs a voltage corresponding to a sampled value; a comparator that compares an output of the first capacitance DA converter and an output of the second capacitance DA converter; a successive approximation logic unit that supplies a control signal to the first capacitance DA converter and the second capacitance DA converter on the basis of a comparison result of the comparator; and an in-phase voltage detection and supply circuit that, in a sampling period, supplies an in-phase voltage obtained by impedance voltage division of the first input analog signal and the second input analog signal to the first capacitance DA converter and the second capacitance DA converter, the first capacitance DA converter samples the first input analog signal with reference to the in-phase voltage in the sampling period, the second capacitance DA converter samples the second input analog signal with reference to the in-phase voltage, after the sampling period ends, the comparator compares the output of the first capacitance DA converter and the output of the second capacitance DA converter, output voltages of the first capacitance DA converter and the second capacitance DA converter are changed by the control signal of the successive approximation logic unit on the basis of a comparison result, comparison processing is repeated, and thereby, a digital signal of a successive approximation result is output.

14. The sensor device according to claim 13, wherein the sensor is a capacitance MEMS sensor, and the sensor device further comprises a C/V conversion amplifier between the capacitance type MEMS sensor and the successive approximation type AD converter.

15. The sensor device according to claim 13, wherein a first reference voltage and a second reference voltage lower than the first reference voltage are supplied to the first capacitance DA converter and the second capacitance DA converter, and a difference between the first reference voltage and the second reference voltage is varied according to amplitude of the differential detection signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a diagram showing an example of a sensor device;

[0011] FIG. 2 is a diagram showing an input signal of an AD converter including no in-phase component;

[0012] FIG. 3 is a diagram showing an input signal of an AD converter including an in-phase component;

[0013] FIG. 4 is a circuit diagram showing a successive approximation type AD converter of a first embodiment;

[0014] FIG. 5 is a diagram showing a clock (switch signal) for driving the successive approximation type AD converter of the first embodiment;

[0015] FIG. 6 is a circuit diagram showing a successive approximation type AD converter of a second embodiment;

[0016] FIG. 7A is a diagram showing a sensor device of a third embodiment;

[0017] FIG. 7B is a diagram showing a modification of the sensor device of the third embodiment;

[0018] FIG. 8A is a diagram showing a C/V conversion amplifier of the third embodiment;

[0019] FIG. 8B is a diagram showing another example of the C/V conversion amplifier of the third embodiment;

[0020] FIG. 9 is a circuit diagram showing a successive approximation type AD converter of a fourth embodiment;

[0021] FIG. 10 is a circuit diagram showing a successive approximation type AD converter of a fifth embodiment; and

[0022] FIG. 11 is a diagram showing a clock (switch signal) for driving the successive approximation type AD converter of the fourth and fifth embodiments.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Embodiments will be described in detail with reference to the drawings. However, the present invention is not construed as being limited to the description of the embodiments described below. Those skilled in the art can easily understand that specific configurations can be changed without departing from the spirit or gist of the present invention.

[0024] In the configuration of the invention described below, the same reference numerals are used for the same parts or parts having similar functions in different drawings, and redundant explanation may be omitted.

[0025] The notations such as first, second and the like in this specification and the like are provided for identifying constituent elements, and do not necessarily limit the number or order. In addition, the number for identifying the constituent element is used for each context, and the number used in one context does not necessarily indicate the same constitution in other contexts. Also, the number does not preclude that the constituent element identified by a certain number doubles as the function of the constituent element identified by another number.

[0026] FIG. 1 shows an example of a sensor device in which a sensor (sensing element) and an AD converter (ADC) are combined. FIG. 1 shows a configuration of a capacitance type MEMS acceleration sensor, which is connected to a differential capacitance type MEMS 200, C/V conversion amplifiers 300a, 300b, and a successive approximation type ADC 100 in this order. In the capacitance type MEMS 200, movable electrodes move due to an inertial force due to an externally applied acceleration signal, so that capacitance values C changes differentially by +AC and AC, respectively. A carrier clock voltage is also applied to the MEMS, so that the change in the capacitance value is converted into a change in charge and amplitude modulated. The change of the amplitude-modulated charge is converted into a voltage change by the C/V conversion amplifiers 300a, 300b connected to the MEMS. The successive approximation type ADC 100 converts the analog signal of the amplified voltage change into a digital value. An in-phase charge component due to charging or discharging of a fixed component C of a capacitance value of the MEMS with a carrier clock voltage is ideally canceled by an in-phase charging and discharging charge by two fixed capacitance elements 400 of capacitance values C inserted between inputs of an inverted carrier clock voltage and the two C/V conversion amplifiers.

[0027] However, when there is a capacity deviation due to manufacturing variations in the MEMS, the capacitance values of the MEMS are expressed as C+C.sub.CM+C.sub.DF+C, C+C.sub.CMC.sub.DFC, respectively. However, C.sub.CM is an in-phase component of the capacitance variation, and C.sub.DF is a differential component.

[0028] Depending on the capacitance deviation of the MEMS, an input analog signal V.sub.INP=V.sub.CM(t)+V.sub.DF(t) on the positive side of the differential input and an input analog signal V.sub.INN=V.sub.CM (t)V.sub.DF(t) on the negative side are input to the ADC. Here, V.sub.CM(t) is an in-phase component, and V.sub.DF(t) is a differential component. Since V.sub.CM=0 is satisfied when C.sub.CM=0, a signal having no in-phase component as shown in FIG. 2 is input to the ADC so that the ADC can convert only the differential component V.sub.DF(t). On the other hand, when C.sub.CM is a value other than zero, a signal having an in-phase component as shown in FIG. 3 is input to the ADC so that the ADC can convert a signal including the in-phase component V.sub.CM(t). At that time, if the in-phase component is large, the comparator inside the ADC malfunctions or noise increases, resulting in a decrease in the resolution of the ADC.

[0029] Embodiments of the present invention for solving this problem and improving in-phase voltage input tolerance will be described below.

First Embodiment

[0030] FIG. 4 is a circuit diagram for explaining a first embodiment of the present invention. FIG. 5 is a diagram showing a clock (switch signal) for driving the successive approximation type AD converter. The successive approximation type AD converter inputs the analog signal V.sub.INP on the positive side of the differential input and the analog signal V.sub.INN on the negative side, and outputs the AD converted digital value. The successive approximation type AD converter of FIG. 4 includes a capacitance digital analog converter (DAC) 50a to which the analog signal V.sub.INP on the positive side is input, a capacitance digital analog converter (DAC) 50b to which the analog signal V.sub.INN on the negative side is input, a comparator 1, a successive approximation logic unit 2, and nodes 17a, 17b. The capacitance DAC 50a includes N capacitance elements 4a (capacitance values C.sub.N-1), . . . , 5a (capacitance value C.sub.1), 6a (capacitance value C.sub.0) weighted with constant coefficients, a node 16a, a switch 3a, and a switch array 60a. In the switch array 60a, on and off of switches 9a, 12a, 15a is controlled by high and low of a clock (switch signal) .sub.1 shown in FIG. 5, on and off of switches 7a, 10a, 13a is controlled by high and low of a clock (switch signal) .sub.2, and on and off of switches 8a, 11a, 14a is controlled by high and low of a clock (switch signal) .sub.2B. On and off of the switch 3a is controlled by high and low of the clock .sub.1. The explanation of the capacitance DAC 50b is similar to the description of the capacitance DAC 50a and will therefore be omitted.

[0031] The in-phase voltage detection and supply circuit 80 is connected to the nodes 16a, 16b, and the in-phase voltage detected by the in-phase voltage detection and supply circuit 80 is supplied. The input analog signals V.sub.INP, V.sub.INN are connected to the in-phase voltage detection and supply circuit 80 via nodes 17a, 17b, impedance voltage division is performed by resistance elements 21a, 21b via switches 20a, 20b, and the divided voltage is generated in a node 25. The node 25 is connected to a fixed potential (AC ground) via the capacitance element 24 and is also connected to the nodes 16a, 16b of the capacitance DACs 50a, 50b via the switch 22. The node 16a and the node 16b have the same potential. The node 16a and the node 16b are connected to a common potential (V.sub.CM) via a switch 23.

[0032] Subsequently, the operation of the successive approximation type AD converter of FIG. 4 will be described. In the capacitance DACs 50a, 50b, the switches 3a, 9a, 12a, 15a and the switches 3b, 9b, 12b, 15b are turned on during a period when .sub.1 is high (sampling period T1), an output voltage of the in-phase voltage detection and supply circuit 80 is connected via the nodes 16a, 16b, and the input analog signals V.sub.INP, V.sub.INN are sampled via the nodes 17a, 17b. Then, the capacitance elements 4a, 5a, 6a and the capacitance elements 4b, 5b, 6b are charged. Next, the switches 3a, 9a, 12a, 15a are turned off during the period when .sub.1 is low (successive approximation period T2), and the switches 8a, 10a, 13a are turned on, so that the capacitance element 4a is connected to V.sub.REFL, the other capacitance elements 5a, 6a are connected to V.sub.REFH, and a voltage value of V.sub.INP+(V.sub.REFH+V.sub.REFL)/2 is generated at the output of the capacitance DAC 50a. In the capacitance DAC 50b, the switches 7b, 11b, 14b are turned on, and a voltage value of V.sub.INN+(V.sub.REFH+V.sub.REFL)/2 is output. The comparator 1 performs positive and negative sign determination of (V.sub.INPV.sub.INN) which is the difference between the output voltage of the capacitance DAC 50a and the output voltage of the capacitance DAC 50b. When V.sub.INPV.sub.INN is positive (nonnegative), the switch 8a is turned off and the switch 7a is turned on, so that the connection of the capacitance element 4a is switched from V.sub.REFL to V.sub.REFH. At this time, the connection of the capacitance on the right side is switched from V.sub.REFH to V.sub.REFL. With respect to the capacitance DAC 50b, operation in which the connection to V.sub.REFH and V.sub.REFL is reversed with respect to the capacitance DAC 50a is performed. As a result, the difference between the output voltage of the capacitance DAC 50a and the output voltage of the capacitance DAC 50b changes to {V.sub.INPV.sub.INN(V.sub.REFHV.sub.REFL)/2}, and the comparator 1 performs positive and negative sign determination thereof. On the other hand, when the V.sub.INPV.sub.INN is negative, the connection of the capacitance element 4a remains V.sub.REFL, and the connection of the capacitance on the right side is switched from V.sub.REFH to V.sub.REFL. With respect to the capacitance DAC 50b, operation in which the connection to V.sub.REFH and V.sub.REFL is reversed with respect to the capacitance DAC 50a is performed. As a result, the difference between the output voltage of the capacitance DAC 50a and the output voltage of the capacitance DAC 50b changes to {V.sub.INPV.sub.INN+(V.sub.REFHV.sub.REFL)/2}, and the comparator 1 performs positive and negative sign determination thereof.

[0033] In the similar manner, while the connection to V.sub.REFH and V.sub.REFL is successively switched with respect to the smaller capacitance element, the comparator 1 successively performs the sign determination of the difference voltage between the output of the capacitance DAC 50a and the output of the capacitance DAC 50b. The above switching is performed by the successive approximation logic unit 2, clocks .sub.2, .sub.2B are generated according to the determination result of the comparator 1, the reference voltage V.sub.REFH or V.sub.REFL is continuously selected, and each determination result is held. These determination results are output from the successive approximation logic unit 2 as a bit string of the AD conversion result.

[0034] Next, the operation of the in-phase voltage detection and supply circuit 80 of FIG. 4 will be described. In the in-phase voltage detection and supply circuit 80, on and off of the switches 20a, 20b, 22 is controlled by high and low of the clock .sub.CM. On and off of the switch 23 is controlled by high and low of the clock .sub.CMB. As shown in FIG. 5, when .sub.CM is high and .sub.CMB is low, the switches 20a, 20b, 22 are turned on and the switch 23 is turned off, impedance voltage division of the in-phase components of the input analog signals V.sub.INP, V.sub.INN is performed by the resistance elements 21a, 21b, and connection is made to the nodes 16a, 16b of the capacitance DACs 50a, 50b via the node 25 and the switch 22.

[0035] Here, the input analog signal of the successive approximation type AD converter can be written as V.sub.INP=V.sub.CM (t)+V.sub.DF (t), V.sub.INN=V.sub.CM (t)V.sub.DF (t) without loss of generality. Here, V.sub.CM(t) is an in-phase component, and V.sub.DF(t) is a differential component. At this time, the voltage V.sub.CMR of the node 25 is impedance voltage divided and

V.sub.CMR=(V.sub.INP+V.sub.INN)/2=V.sub.m(t)

is satisfied. Since the voltage of the node 25 is applied to the nodes 16a, 16b, the voltage obtained by sampling V.sub.INP, V.sub.INN with respect to the common voltage V.sub.CMR satisfies

V.sub.SAMPP=V.sub.INPV.sub.CMR=+V.sub.DF(t)

V.sub.SAMPN=V.sub.INNV.sub.CMR=V.sub.DF(t)

[0036] That is, the in-phase component of the signal input to the comparator 1 is canceled. As a result, the operating potential of the differential input MOS transistor constituting the comparator can be maintained appropriately, so that the comparator can operate normally. Since the noise of the comparator depends on the in-phase potential of the input of the comparator, low noise can be maintained. Thus, even when there is an in-phase component in the input analog signals V.sub.INP, V.sub.INN, the differential component can be AD converted with high resolution.

[0037] The capacitance element 24 may be inserted between the connection point of the resistance element 21a and the resistance element 21b and the ground potential (ground) or fixed potential (AC ground). Assuming that the resistance values of the resistance element 21a and the resistance element 21b are both R and the capacitance value of the capacitance element 24 is C, since the frequency bandwidth of the input in-phase component captured on the node at the connection point of the resistance element 21a and the resistance element 21b is 1/(RC), for example, the value of RC may be selected so as to be about the same as the frequency of the main component included in the input in-phase component. This is because, if the frequency bandwidth is excessively increased, a high-frequency component remains on the node 22, which in turn passes due to parasitic capacitive coupling of the switches 3a, 3b which are turned off in the successive approximation period T2, and the resolution is somewhat lowered due to the mismatch between the switches 3a, 3b of the parasitic capacitive coupling amount.

[0038] Normally, the first reference voltage V.sub.REFH is often the power supply voltage V.sub.DD and the second reference voltage V.sub.REFL is often the ground potential. However, in the MEMS acceleration sensor of the servo configuration, as the servo control progresses, the movable electrode of the MEMS approaches the equilibrium position, and thereby, the AC approaches zero. Therefore, after the servo control has sufficiently converged, the differential components included in the input analog signals V.sub.INP, V.sub.INN of the ADC are small. Since the range in which the differential signal can be input of the ADC is determined by V.sub.REFHV.sub.REFL, the quantization error can be reduced by paying attention to the nature of the signal, and reducing and imparting V.sub.REFHV.sub.REFL, for example, as V.sub.REFH0.75 V.sub.DD, V.sub.REFL0.25 V.sub.DD. This is because the quantization error is proportional to V.sub.REFHV.sub.REFL. However, at this time, since the differential component is small, there is a problem that the SN ratio after the AD conversion lowers by being affected by the in-phase component included in the input signals V.sub.INP, V.sub.INN. However, by using the configuration of the present invention, it is possible to suppress the influence of the in-phase component and obtain a preferable SN ratio.

[0039] In order to perform the similar operation to the conventional successive approximation type AD converter, .sub.CM is set low and .sub.CMB is set high, so that the common voltage V.sub.CM is connected to the nodes 16a, 16b via the switch 23.

[0040] By controlling .sub.CM and .sub.CMB, it is possible to control on and off of the in-phase voltage detection and supply function of this configuration at an arbitrary timing regardless of the operation state of the successive approximation type AD converter. When the in-phase voltage detection and supply function of this configuration is turned on, at the completion of sampling, that is, at the moment when the switches 3a and 3b are turned off, noise is generated due to a slight mismatch between charges emitted from the switch 3a toward the capacitance elements 4a, 5a, 6a (charge injection and clock feedthrough) and charges emitted from the switch 3b toward the capacitance elements 4b, 5b, 6b, and the resolution is slightly reduced. Therefore, when extremely high resolution is desired to be obtained, the in-phase voltage detection and supply function may be turned off so that the conventional operation is performed.

[0041] According to the present embodiment, the in-phase components of the input analog signals V.sub.INP, V.sub.INN are impedance voltage divided by the resistance element and the result is supplied to the capacitance DACs 50a, 50b via a switch. Therefore, even when an in-phase component is included in a signal input to the AD converter, the differential component can be AD converted with high resolution. Thus, it is possible to realize a successive approximation type AD converter with low power consumption and improved in-phase voltage input tolerance without using an active element such as an operational amplifier.

Second Embodiment

[0042] FIG. 6 is a circuit diagram for explaining a second embodiment of the present invention. In the configuration of FIG. 6, unlike the configuration of FIG. 4, capacitance elements 31a, 31b and a resistance digital analog converter (RDAC) 30 are provided in addition to the capacitance DACs 50a, 50b. The capacitance elements 31a, 31b have the same value as the capacitance value C.sub.0 of the capacitance elements 6a, 6b of the least significant bit of the capacitance DACs 50a, 50b. The resistance DAC 30 is configured to be a resistor string type or an R-2R ladder type. In addition to converting the high-order bits by the capacitance DACs 50a, 50b, the low-order bits are converted by the resistance DAC 30, so that the resolution of the AD converter can be increased. For example, such operation is disclosed in U.S. Pat. No. 8,395,538. Also in this configuration, the configuration and operation of the in-phase voltage detection and supply circuit 80 are similar to those in the first embodiment.

[0043] According to the present embodiment, in addition to the effect of the first embodiment, resolution of the successive approximation type AD converter can be enhanced by converting the low-order bits by the resistance DA converter.

Third Embodiment

[0044] The third embodiment of the present invention is a sensor device in which a sensor that outputs a differential signal and the successive approximation type AD converter of the present invention are combined. FIG. 7A shows a sensor device of the third embodiment.

[0045] The sensor device includes the capacitance type MEMS 200 that outputs a differential signal, the C/V conversion amplifiers 300a, 300b that convert the capacitance change into a voltage change, and the successive approximation type AD converter 100 described in the first embodiment or the second embodiment that outputs a digital value obtained by inputting the amplified signal and AD converting the signal. In the differential capacitance type MEMS, a fixed electrode and a movable electrode are provided, the movable electrode moves due to an inertial force due to an externally applied acceleration, so that capacitance values C between the movable electrode and the fixed electrode changes differentially by +AC and AC, respectively. At this time, since the capacitance value of the MEMS electrode 1 of the capacitance type MEMS 200 is Ca+C and the capacitance value of the MEMS electrode 2 is CbC, there is an in-phase component of (Ca+Cb)/2. An in-phase charge component due to charging or discharging of a fixed component C of a capacitance value of the MEMS with a carrier clock voltage is ideally canceled by an in-phase charging and discharging charge by two fixed capacitance elements (400) of capacitance values C inserted between inputs of an inverted carrier clock voltage and the two C/V conversion amplifiers. However, in reality, (Ca+Cb)/2 is deviated from C due to manufacturing variations or the like, so that an in-phase charge component proportional to the difference is generated. Therefore, in addition to the amplitude-modulated differential charge signal proportional to the change AC of the capacitance value, there is the in-phase charge component. The differential charge signal and the in-phase charge component are converted into a voltage change by the C/V conversion amplifiers 300a, 300b connected to the MEMS. The analog signal V.sub.INP on the positive side and the analog signal V.sub.INN on the negative side of the differential input having an in-phase component are input to the successive approximation type AD converter 100 described in the first embodiment or the second embodiment, so that in-phase component can be suppressed, the voltage signal proportional to the differential capacitance change can be AD converted, and a digital value can be output. The detection circuit including the capacitance type MEMS and the successive approximation type AD converter may be formed as an integrated semiconductor element. In FIG. 7A, the capacitance type MEMS 200 is configured as a differential type. However, the present invention is also effective in the case of a fixed capacitance in which capacitance is not changed by an acceleration signal on one side.

[0046] FIG. 7B shows a modification of the sensor device of the present embodiment. In this modification, the differential capacitance type MEMS 200 is used in a pair. The capacitance value of the MEMS electrode 1 is Ca+C, the capacitance value of the MEMS electrode 2 is CbC, and the charge amount generated by applying a carrier clock and an inverted carrier clock to each of the electrodes is proportional to (CaCb)+2AC. The capacitance value of the MEMS electrode 3 is CcC, the capacitance value of the MEMS electrode 4 is Cd+C, and a carrier clock and an inverted carrier clock are applied to each of the electrodes, and the generated charge amount is proportional to (CcCd)2AC. Ideally, since Ca=Cb=Cc=Cd=C is satisfied, this configuration substantially cancels the charge due to the fixed capacitance and doubles the differential component. However, in reality, due to variations in MEMS manufacturing, or the like, the in-phase component of (CaCb+CcCd)/2 is generated. The analog signal V.sub.INP on the positive side and the analog signal V.sub.INN on the negative side of the differential input having an in-phase component are input to the successive approximation type AD converter 100 described in the first embodiment or the second embodiment, so that in-phase component can be suppressed and AD converted, and a digital value can be output.

[0047] FIG. 8A shows an example of the C/V conversion amplifiers 300a, 300b. The C/V conversion amplifier 300a is a configuration of a capacitance type so-called operational amplifier inverting amplifier, the input capacitance is the variable capacitance of the MEMS, and the feedback capacitance is a capacitance element 82 having the fixed capacitance value. However, a high-resistance feedback resistor 83 is inserted in parallel in a feedback path. The reason for this is to secure a direct current feed path for compensating an input leakage current of the operational amplifier 81, or the like. On the other hand, a reset switch may be used in place of the feedback resistor 83. However, in that case, due to the influence of the sampling noise due to the reset switch, the noise is larger than that in the case of the feedback resistor. The thermal noise due to the feedback resistor 83 of the high resistance value can be suppressed by the low pass filter characteristic of the feedback resistor 83 and the feedback capacitor 82. The configuration and operation of the C/V conversion amplifier 300b are similar to those of the C/V conversion amplifier 300a.

[0048] FIG. 8B shows an example of another configuration of the C/V conversion amplifier. The difference from FIG. 8A is that one complete differential operational amplifier 87 is used. Other configurations and operations themselves are similar to those described in FIG. 8A.

[0049] In this embodiment, the capacitance type MEMS acceleration sensor has been described as an example. However, the present invention can be generally used as a sensor that outputs a differential signal as a sensing element.

Fourth Embodiment

[0050] FIG. 9 shows a fourth embodiment of the present invention. In the present embodiment, the resistance elements 21a, 21b in FIG. 4 are replaced by capacitance elements 91a, 91b. In the first embodiment, the in-phase components of the input analog signals V.sub.INP, V.sub.INN are generated by impedance voltage division by the resistance elements 21a, 21b. In this embodiment, the in-phase components are generated by impedance voltage division by the in-phase voltage detection and supply and the capacitance elements 91a, 91b of a charge amount setting circuit 900.

[0051] Since the basic operation is similar to that of the first embodiment, different points will be described below. In the present embodiment, it is preferable that the capacitance element 24 in FIG. 4 is not provided. This is because, when the capacitance element 24 is provided, the voltage generated at the connection point between the capacitance element 91a and the capacitance element 91b deviates from the in-phase components of the input analog signals V.sub.INP and V.sub.INN. In the present embodiment, since the input in-phase component of the entire frequency band is captured on the node at the connection point between the capacitance element 91a and the capacitance element 91b, the size of the switch 3a and the switch 3b are designed to be relatively small in order to suppress the passing of the captured input in-phase component due to the parasitic capacitance coupling at the off time and the reduction in resolution accompanying the passing.

[0052] In the present embodiment, a switch 92, a switch 93a, and a switch 93b are further provided. In the absence of these switches, the nodes 16a, 16b are electrically isolated from each other when the in-phase voltage detection and supply function is turned on (.sub.cm=high, .sub.CMB=low). In order to generate the in-phase components of the input analog signals V.sub.INP, V.sub.INN by the impedance voltage division, the total charge amount on the electrodes of all the capacitance elements connected to the nodes 16a, 16b (that is, the capacitance elements 91a, 91b, 4a, 5a, 6a, 4b, 5b, 6b) needs to be zero (or a constant value). In the present embodiment, when the in-phase voltage detection and supply function is turned on, the switch 92 inserted between the connection point of the capacitance element 91a and the capacitance element 91b and the ground or AC ground (fixed potential) is turned on, the switch 93a inserted between the node 17a and the ground or AC ground is turned on, the switch 93b inserted between the node 17b and the ground or AC ground is turned on, and the switch 3a, the switch 3b, the switch 9a, the switch 12a, the switch 15a, the switch 9b, the switch 12b, and the switch 15b are turned on, so that short-circuit between both electrodes of the capacitance elements 91a, 91b, 4a, 5a, 6a, 4b, 5b, 6b occurs, and the total charge amount on the electrodes of all the capacitance elements connected to the nodes 16a, 16b can be set to zero.

[0053] The switch 92, the switch 93a, and the switch 93b are turned on in a period in which .sub.RST is high. In the present embodiment, as shown in the timing chart of FIG. 11, for example, at the end of the successive approximation period T2, that is, after the determination of all the bits is completed, .sub.RST is made high, and .sub.1 is made high in order to turn the switch 3a, the switch 3b, the switch 9a, the switch 12a, the switch 15a, the switch 9b, the switch 12b, and the switch 15b on, so that the total charge amount is periodically set to zero in every AD conversion. This makes it possible to suppress the total charge amount from transitioning from zero due to a leakage current via each switch in the off state, an input leakage current of the comparator, or the like. Since short circuit of V.sub.INP, V.sub.INN occurs by the ground or AC ground when .sub.RST is made high, a switch may be inserted before the input of the AD converter, and the switch is turned off when .sub.RST is high, so that the output of a circuit such as an amplifier in the preceding stage of the AD converter is not shorted by the ground or the AC ground.

Fifth Embodiment

[0054] FIG. 10 shows a fifth embodiment of the present invention. The present embodiment is configured by a charge amount setting circuit 1000 in which the capacitance elements 91a, 91b and the switches 20a, 20b, 22 in the fourth embodiment are removed. In the present embodiment, the impedance voltage division for generating the in-phase component of the input analog signals V.sub.INP, V.sub.INN is performed using the capacitance elements 4a, 5a, 6a and the capacitance elements 4b, 5b, 6b. That is, the total capacitance value of the capacitance elements 4a, 5a, 6a is used instead of the capacitance element 91a in the fourth embodiment, and the total capacitance value of the capacitance elements 4b, 5b, 6b is used instead of the capacitance element 91b. As a result, similarly to the fourth embodiment, the input in-phase components of the entire frequency band are captured in the node 16a and the node 16b. Therefore, it is possible to obtain the similar effect by similar operation to that in the first embodiment and the fourth embodiment. Also in the present embodiment, since V.sub.INP, V.sub.INN are short circuited by the ground or AC ground when .sub.RST is made high, a switch is inserted before the input of the AD converter, and the switch is turned off when .sub.RST is high, so that the output of a circuit such as an amplifier in the preceding stage of the AD converter is not short circuited by the ground or the AC ground.

[0055] Also in the present embodiment, for example, operation in the timing chart shown in FIG. 11 can be performed. At the end of the successive approximation period T2, that is, after the determination of all bits is completed, .sub.RST is set to high and .sub.1 is set to high, so that the total charge amount on the electrodes of all the capacitance elements connected to the nodes 16a, 16b (that is, capacitance elements 4a, 5a, 6a, 4b, 5b, 6b) is set to zero. Next, .sub.1 is kept to be high and .sub.RST is set to low, so that the input analog signals V.sub.INP, V.sub.INN are applied to the capacitance elements 4a, 5a, 6a, 4b, 5b, 6b, and a this time, the in-phase components of the input analog signals V.sub.INP, V.sub.INN are generated in the node 16a and the node 16b due to impedance voltage division by the capacitance elements 4a, 5a, 6a and the capacitance elements 4b, 5b, 6b. Therefore, as described in the first embodiment, the charges charged in the capacitance elements 4a, 5a, 6a, 4b, 5b, 6b do not include the in-phase components of the input analog signals V.sub.INP, V.sub.INN as similar to the case of the first and fourth embodiments. Therefore, as similar to the first embodiment and the fourth embodiment, a successive approximation type AD converter with improved in-phase voltage input tolerance can be realized.

[0056] As a successive approximation type AD converter, there is also known a circuit for connecting V.sub.INP to the node 16a, connecting V.sub.INN to the node 16b, connecting the node 17a and the node 17b with the common potential V.sub.cm, and sampling in FIG. 4. Also in this circuit, the resistance element 21a or the capacitance element 91a are connected to the node 16a, the resistance element 21b or the capacitance element 91b is connected to the node 16b, and the connection point between the resistance element 21a and the resistance element 21b, or the connection point between the capacitance element 91a and the capacitance element 91b is connected to the node 17a and the node 17b, so that similar operation to that in the first embodiment and the fourth embodiment is performed and similar effect can be obtained. At that time, the switch 93a and the switch 93b in FIG. 9 may be connected to the node 16a and the node 16b, respectively. In order to perform operation corresponding to the fifth embodiment, in FIG. 10, in the circuit in which V.sub.INP is connected to the node 16a and V.sub.INN is connected to the node 16b, the switch 93a and the switch 93b are connected to the node 16a and the node 16b, respectively, and the node 17a and the node 17b are short circuited and connected to the switch 92. As a result, it is possible to obtain the similar effect by similar operation to that in the fifth embodiment.