Isolated semiconductor layer stacks for a semiconductor device

Abstract

In one aspect, a method of forming a semiconducting device can comprise forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.

Claims

1. A method of forming a semiconducting device, the method comprising: forming, on a substrate surface, a stack comprising semiconductor material sheets and a bottom semiconductor nanosheet in the form of a fin; forming a trench through the stack vertically down through the bottom semiconductor nanosheet, thereby separating the stack into two substacks; selectively removing at least a part of the bottom semiconductor nanosheet, thereby forming a bottom space extending under the substacks; and filling the bottom space and the trench with a dielectric material to provide a bottom isolation and formation of a dielectric wall between the substacks.

2. The method according to claim 1, wherein the bottom semiconductor nanosheet comprises SiGe having a Ge content of over 50%.

3. The method according to claim 2, wherein the bottom semiconductor nanosheet is a Si.sub.0.35Ge.sub.0.65 sheet.

4. The method according to claim 2, wherein the semiconductor material sheets comprise SiGe sheets having a Ge content of below 40%.

5. The method according to claim 1, wherein forming the stack further comprises forming an upper insulator layer above the semiconductor material sheets.

6. The method according to claim 5, wherein the upper insulator layer comprises Si.sub.3N.sub.4.

7. The method according to claim 5, wherein forming the stack further comprises forming a top oxide layer above the semiconductor material sheets.

8. The method according to claim 5, wherein forming the stack further comprises lining sidewalls of the stack with an insulator material and depositing a shallow trench isolation (STI) oxide on the lined sidewalls of the stack, such that the stack is held together by the STI oxide during selectively removing at least a part of the bottom semiconductor nanosheet.

9. The method according to claim 8, further comprising: planarizing the formed structure after depositing the STI oxide such that the upper insulator layer above the semiconductor material sheets is the uppermost layer of the stack; and forming a patterned photoresist layer over the upper insulator layer such that an opening in the photoresist layer is positioned vertically over the stack, wherein forming the trench through the stack vertically down through the bottom semiconductor nanosheet comprises forming the trench at the position of the opening, thereby separating the stack into the substacks.

10. The method according to claim 8, further comprising: planarizing the formed structure after depositing the STI oxide such that the upper insulator layer above the semiconductor material sheets is the uppermost layer of the stack; removing the upper insulator layer such that the deposited STI oxide forms vertically extending sidewalls at sides of the stack; and depositing a spacer material over the stack and at the vertically extending sidewalls, thereby defining a horizontal gap over the stack, wherein forming the trench through the stack vertically down through the bottom semiconductor nanosheet is at a position corresponding to the horizontal gap, thereby separating the stack into the substacks.

11. The method according to claim 8, wherein forming the stack further comprises trimming sidewalls of the upper insulator layer such that the upper insulator layer has a width that is smaller than a width of the semiconductor material sheets of the stack, the trimming being performed before lining the stack with the insulator material.

12. The method according to claim 7, wherein the top oxide layer comprises SiO.sub.2.

13. The method according to claim 1, wherein the dielectric material is selected from the group consisting of Si.sub.3N.sub.4, SiCO, and SiO.sub.2.

14. The method according to claim 1, wherein the method further comprises planarizing the substacks.

15. The method according to claim 1, wherein the method further comprises forming gates at least partly around the substacks.

16. The method according to claim 15, wherein forming the gates comprises forming a p-gate at least partly around a first one of the substacks and an n-gate at least partly around a second one of the substacks.

17. The method according to claim 1, wherein the stack comprises a channel material and a sacrificial material.

18. The method according to claim 17, wherein the channel material and the sacrificial material comprise one of silicon, silicon germanium, germanium, a material from group III in the periodic table, or a material from group V in the periodic table.

19. The method according to claim 1, further comprising: forming a p-type effective work function metal on first and second substacks of the substacks; selectively removing the p-type effective work function metal from the second substack; and forming an n-type effective work function metal on the second substack.

20. The method according to claim 19, further comprising forming a first gate electrode in contact with the first substack and a second gate electrode in contact with the second substack.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above, as well as additional objects, features and advantages of the disclosed technology, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.

(2) FIGS. 1A and 1B are general illustrations of various intermediate structures of an approach of the disclosed technology of wall formation and bottom isolation.

(3) FIGS. 2A-2K illustrate various intermediate structures of a method according to some embodiments of forming a semiconductor device.

(4) FIGS. 3A-3K illustrate various intermediate structures of a method according to some embodiments of forming a semiconductor device.

(5) FIGS. 4A-4L illustrate various intermediate structures of a method according to some embodiments of forming a semiconductor device.

(6) FIGS. 5A-5C illustrate an example semiconductor device with different thickness of the fins.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

(7) The disclosed technology is mainly being described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed herein are equally possible within the scope of the inventive concept, as defined by the appended claims.

(8) FIGS. 1A and 1B show the general approach of the disclosed technology of wall formation and bottom isolation of a semiconductor device 1. As seen in FIG. 1A, the semiconductor device can comprise a stack 2 of horizontally extending nanosheets on a substrate surface 20. The method can comprise a step of forming a trench 3 in the stack, thereby dividing the stack 2 into two substacks 21, 22, and also selectively removing a bottom sheet to create a bottom space 4. During this procedure, the stack may be attached to e.g., an STI oxide 8. Thereafter, as illustrated in FIG. 1B, the trench 3 and the bottom space 4 may be filled (e.g., simultaneously) with dielectric material 13 (e.g., the same dielectric material). In various implementations, the formation of the wall between substacks and the bottom isolation may be performed while using STI oxide to hold the fins of the stack 2, for example, instead of performing the isolation during e.g., subsequent gate patterning.

(9) FIGS. 2A-2K illustrate a method according to some embodiments of forming a semiconductor device according to the disclosed technology.

(10) The method can comprise a step a) of forming a stack 2 of horizontally extending nanosheets on a substrate surface 20 of silicon (Si). The stack 2 can comprise semiconductor material sheets 2b and a bottom semiconductor nanosheet 2a. In some examples, the bottom semiconductor nanosheet 2a is a Si.sub.0.35Ge.sub.0.65 sheet, whereas the other semiconductor nanosheets 2b of the stack 2 comprises SiGe sheets having a Ge content of below 40%.

(11) Between the SiGe sheets in the stack 2b, there may be sheets of a semiconductor material that form the final channel material in the formed semiconductor device. In some implementations, the SiGe sheets may be sacrificial sheets that are subsequently removed. For example, the stack of semiconductor material sheets formed in step a) may comprise alternating SiGe sheets and sheets of another material.

(12) As an example, the channel material of the stack 2b may be Si, and the sacrificial material may be SiGe.

(13) Such a combination of materials may allow for selective removal of the sacrificial material while leaving the channel material.

(14) Alternatively, the channel material of the stack 2b may be silicon germanium (SiGe) and the sacrificial material may be silicon (Si).

(15) Further, the channel material of the stack 2b may be silicon germanium with a first concentration of germanium Si.sub.1-xGe.sub.x and the sacrificial material may be silicon germanium with a second concentration of germanium, different from the first concentration Si.sub.1-yGe.sub.y.

(16) Another combination may be germanium (Ge) as the channel material, and silicon germanium (SiGe) as the sacrificial material.

(17) Further, some embodiments may comprise a combination of channel/sacrificial materials wherein one material is from group (or family) III in the periodic table, and the other material is from group (or family) V in the periodic table. For example, the channel material may be from group III, also known as the boron group, which comprises boron (B), aluminum (Al), gallium (Ga), and indium (In). The sacrificial material may be from group V, also known as the nitrogen group or pnictogens, which comprises nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb). Alternatively, the channel material may be selected from group V and the sacrificial material selected from group III.

(18) Furthermore, the stack 2 formed in step a) can comprise an upper insulator layer 5 above the semiconductor material sheets 2b. This upper insulator layer 5 may for example be a Si.sub.3N.sub.4 layer, and may originate from the formation and patterning of the stack 2 on the substrate 20. A top oxide layer 6 can also be formed as the uppermost layer, which also may originate from the formation of the stack 2, e.g., during lithography. The top oxide layer 6 may for example be a SiO.sub.2 layer. Both the upper insulator layer 5 and the top oxide layer 6 may be a Si.sub.3N.sub.4 layer and/or a SiO.sub.2 layer.

(19) As illustrated in FIG. 2B, in the method according to some embodiments, step a) further can comprise lining the stack 2 with an insulator material 7. This may for example be performed using ALD. The stack 2 may for example be lined with Si.sub.3N.sub.4. The lining of the stack 2 may reduce and/or prevent oxidation in some instances. Moreover, as illustrated in FIG. 2C, step a) may further comprise the deposition of the STI oxide 8 and (e.g., subsequent) planarization using e.g., CMP. The STI oxide 8 may be deposited to the lined sidewalls 2c of the stack 2 such that the stack 2 may be held together by the STI oxide 8 during a (e.g., simultaneous) bottom isolation and wall formation of step c). After STI deposition, the formed structure can be planarized. In some examples, it is planarized such that the upper insulator layer 5 is the uppermost layer of the stack 2.

(20) As illustrated in FIGS. 2D-2F, a patterned photoresist layer 9 can be formed atop of the stack such that an opening 10 in the photoresist layer 9 is positioned vertically over the stack 2. The width of the opening 10 can determine the width of the trench that is subsequently formed to divide the stack 2 into the two substacks. In some embodiments, the step of forming the opening 10 can comprise depositing a hardmask layer 14, such as SiO.sub.2, on top of the stack 2, and depositing a patterning stack which is used to pattern. As an example, the patterning stack may comprise a SoC layer 15, a SoG layer 16 and an upper photoresist 9 over the hardmask 14, which can be patterned using any suitable photomask. The SoG and the SoC layers can be etched at the position of the opening 10 after removal of the photoresist layer, as illustrated in FIG. 2F.

(21) In various implementations, the hardmask 14 and the upper insulator layer 5 can be etched using a suitable hard-mask open (HMO), as illustrated in FIG. 2G, e.g., before etching the trench 3 that divides the stack 2 into two substacks 21, 22, as illustrated in FIG. 2H. The etch through the stacks may be performed using any suitable anisotropic (top-down) etch, and divides the stack 2 into two substacks 21, 22.

(22) Some embodiments as illustrated in FIGS. 2A-2H, step b) can comprise the steps of b11) planarizing the formed structure after STI oxide deposition such that the upper insulator layer 5 above the semiconductor material sheets 2b is the uppermost layer of the stack 2;

(23) b12) forming a patterned photoresist layer 9 over the upper insulator layer 5 such that an opening 10 in the photoresist layer 9 is positioned vertically over the stack 2; and b13) forming a trench 3 through the stack vertically down through the bottom semiconductor nanosheet 2a at the position of the opening 10; thereby separating the stack into two substacks 21,22.

(24) After forming the trench 3, the bottom semiconductor nanosheet 2a can be selectively removed from the stack 2 in a step c) using e.g., etching based on an ammonia hydroxide-hydrogen peroxide-water mixture (APM). This is illustrated in FIG. 2I. After removal of at least a part of the bottom layer 2a, a bottom space 4 is formed under the stack 2, which can extend under both of the substacks 21, 22. As illustrated in FIG. 2J, the bottom space 4 and the trench 3 are filled (e.g., simultaneously in some instances) in a step d) with dielectric material 13 (e.g., the same dielectric material in some instances) to provide a bottom isolation 4a and formation of a dielectric wall 3a between the substacks 21,22. The bottom isolation 4a can be at the filled bottom space 4 and the dielectric wall 3a can be at the position of the previous trench 3. The dielectric material 13 that is deposited to form the bottom isolation 4a and the wall 3a may be selected from the group consisting of Si.sub.3N.sub.4, SiCO, and SiO.sub.2. The deposited dielectric material 13 may be planarized, as illustrated in FIG. 2K. In some implementations, both substacks 21,22 may be planarized such that the upper dielectric material 5 is the uppermost layer of the stack 2.

(25) The formation of the trench 3 in some embodiments discussed in relation to FIGS. 2A-2K can be formed by using lithography. However, other methods may be used to form the trench 3. FIGS. 3A-3K illustrate some embodiments with “self-aligned” wall formation. As illustrated in FIGS. 3A-3D, an STI oxide 8 may be deposited after lining the stack with an oxide 7, as discussed in relation to FIGS. 2B and 2C above. In some implementations, before formation of the trench 3, the upper dielectric material 5, such as Si.sub.3N.sub.4, may be removed using e.g., phosphoric acid (H.sub.3PO.sub.4), as seen in FIG. 3E. In this way, vertically extending sidewalls 8a of the STI oxide 8 can be formed around the remaining stack 2. Spacer material 11 can be deposited (e.g., conformally deposited in some instances) over the stack 2 and the vertically extending sidewalls, as illustrated in FIG. 3F. The spacer material 11 can be deposited using e.g., plasma enhanced atomic layer deposition (PEALD) to an extent such that a horizontal gap 12 is formed between the sidewalls 8a. This gap 12 can be arranged vertically above the stack 2 and can provide and/or define the position of the trench 3 that is subsequently formed through the stack. The deposited spacer material 11 may be etched-back, as seen in FIG. 3G, and a trench may be formed by etching the stack 2 at the position of the gap 12 formed between the deposited spacer material at the sidewalls 8a of the STI oxide 8, as seen in FIG. 3H.

(26) Some embodiments as illustrated in FIGS. 3A-3K, step b) can comprise b21) planarizing the formed structure after STI oxide 8 deposition such that the upper insulator layer 5 above the semiconductor material sheets 2b is the uppermost layer of the stack 2; b22) removing the upper insulator layer 5 such that the deposited STI oxide 8 forms vertically extending sidewalls 8a at the side of the stack 2; b23) depositing spacer material 11 over the stack 2 and at the vertically extending sidewalls 8a, thereby defining a horizontal gap 12 over the stack 2; and b24) forming a trench 3 through the stack vertically down through the bottom semiconductor nanosheet 2a at the position of the horizontal gap 12, thereby separating the stack into two substacks.

(27) As illustrated in FIGS. 3I-3K, the bottom layer 2a may be selectively removed and the trench and the bottom space 4 may be filled with dielectric material as discussed in relation to FIGS. 2I and 2J above. The formed structure may be planarized, as illustrated in FIG. 3K.

(28) In order to increase the aspect-ratio of the dielectric wall between the two sub stacks, the upper insulator layer may be trimmed before depositing of the STI oxide. Such an embodiment is illustrated in FIGS. 4A-4L, which shows a similar method of forming the trench and the isolation as discussed in relation to FIGS. 3A-3K above, but with an additional step of trimming the upper insulator layer 5, such as an upper Si.sub.3N.sub.4, layer, as illustrated in FIG. 4B, before lining the stack with e.g., a Si.sub.3N.sub.4 liner, in FIG. 4C. The trimming of the upper insulator layer may be performed using liquid phase or gas phase isotropic etch, such as a dry gas chemical reaction with e.g., hydrofluoric acid (HF) and ammonia (NH.sub.3).

(29) The effect of such a trimming operation is that the subsequent lining with the insulator material 7 (FIG. 4C), deposition of STI oxide 8 (FIG. 4D) and removal of the top insulator layer 5 (FIG. 4E) can result in vertically extending sidewalls 8a of the STI oxide that are arranged closer to each other in the horizontal direction compared to if no trimming is performed, as illustrated in FIG. 4F.

(30) When depositing spacer material 11 over the stack 2 and at the vertically extending sidewalls 8a, as illustrated in FIG. 4G, a thinner spacer in the horizontal direction can be used to define the horizontal gap 12 over the stack 2, as illustrated in FIGS. 4G and 4H.

(31) In some implementations, the trimming operation may be used if the stack is wide, e.g., has a larger extension in the horizontal direction. With a wide stack and no trimming, the gap 12 formed after depositing spacer material at the sidewalls may be larger if depositing the same amount of spacer material. Thus, with no trimming, the trench 3 and subsequent wall separating the two substacks may be wider. In some implementations, using a trimming operation of the upper insulator layer 5, a thinner gap 12 and trench 3 may be formed. This can be further illustrated in FIGS. 5A-5C. The width of a substack 21, 22 is the width of the STI oxide over a substack (L.sub.ox)+ the width of the deposited spacer (L.sub.sp). L.sub.ox may be adjusted by the trimming operation, e.g., the more the upper insulator layer is trimmed, illustrated by L.sub.trim in FIG. 5A, the larger L.sub.ox becomes after STI deposition. A thin stack is illustrated in FIG. 5B and a wider stack is illustrated in FIG. 5C. In order to maintain the same wall thickness L.sub.w for the larger stack of FIG. 5C with the same spacer thickness L.sub.sp, a different trimming operation can be performed to increase L.sub.trim and thus also L.sub.ox2. Thus, with a different trimming, the width of the STI oxide over a substack L.sub.ox2 of the wider stack becomes larger than the width of the STI oxide over a substack L.sub.ox1 of the thinner stack, as illustrated in FIGS. 5B and 5C.

(32) As shown in FIGS. 4I-4L, formation of trench 3 (FIG. 4I), selective removal of bottom sheet to form bottom space 4 (FIG. 4J), isolation (e.g., simultaneous isolation in various instances) of trench 3 and bottom space 4 with dielectric material 13 (FIG. 4K) and planarization (FIG. 4L) may be performed as discussed in relation to the previous embodiments above.

(33) In various implementations shown in FIGS. 4A-4L, step a) can further comprise trimming the sidewalls 5a of the upper insulator layer 5 such that the upper insulator layer 5 has a width that is smaller than the width of the semiconductor material sheets 2b of the stack 2, e.g., the trimming being performed before lining the stack 2 with an insulator material 7.

(34) While methods and processes may be depicted in the drawings and/or described in a particular order, it is to be recognized that the steps need not be performed in the particular order shown or in sequential order, or that all illustrated steps be performed, to achieve desirable results. Further, other steps that are not depicted may be incorporated in the example methods and processes that are schematically illustrated. For example, one or more additional steps may be performed before, after, simultaneously, or between any of the illustrated steps. Additionally, the steps may be rearranged or reordered in other embodiments.