OPERATIONAL AMPLIFIER CIRCUIT CAPABLE OF IMPROVING LINEARITY RELATION BETWEEN LOADING CURRENT AND INPUT VOLTAGE DIFFERENCE

Abstract

An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.

Claims

1. An operational amplifier circuit, comprising: a differential input stage circuit, comprising: a first input circuit, comprising: a first input transistor, having a first terminal, a second terminal, and a control terminal for receiving a first input signal; and a second input transistor, having a first terminal, a second terminal, and a control terminal for receiving a second input signal; and a first voltage maintaining circuit, comprising: a first tracking transistor having a first terminal, a second terminal coupled to the first terminal of the first input transistor, and a control terminal coupled to the control terminal of the first input transistor; and a second tracking transistor having a first terminal, a second terminal coupled to the first terminal of the second input transistor, and a control terminal coupled to the control terminal of the second input transistor; a first current source, coupled to the second terminals of the first input transistor and the second input transistor; and a loading stage circuit, for generating a first stage output, wherein the first terminal of the first tracking transistor and the first terminal of the second tracking transistor are respectively coupled to the loading stage circuit.

2. The operational amplifier circuit according to claim 1, wherein a first loading current flows from the loading stage circuit to the first input circuit through the first tracking transistor; and a second loading current flows from the loading stage circuit to the first input circuit through the second tracking transistor, wherein the loading stage circuit generates the first stage output based on the first loading current and the second loading current.

3. The operational amplifier circuit according to claim 2, wherein the first loading current and the second loading current flow from the first input circuit to the first current source.

4. The operational amplifier circuit according to claim 1, wherein a first loading current flows from the first input circuit to the loading stage circuit through the first tracking transistor, and a second loading current flows from the first input circuit to the loading stage circuit through the second tracking transistor, wherein the loading stage circuit generates the first stage output based on the first loading current and the second loading current.

5. The operational amplifier circuit according to claim 4, wherein the first loading current and the second loading current flow from the first current source to the first input circuit.

6. The operational amplifier circuit according to claim 1, wherein the first voltage maintaining circuit further comprises: a third tracking transistor having a first terminal coupled to the first terminal of the first tracking transistor, a second terminal coupled to the first terminal of the first input transistor, and a control terminal coupled to the control terminal of the second input transistor; and a fourth tracking transistor having a first terminal coupled to the first terminal of the second tracking transistor, a second terminal coupled to the first terminal of the second input transistor, and a control terminal coupled to the control terminal of the first input transistor.

7. The operational amplifier circuit according to claim 6, wherein a first loading current flows from the loading stage circuit to the first input circuit through the first tracking transistor and the third tracking transistor; and a second loading current flows from the loading stage circuit to the first input circuit through the second tracking transistor and the fourth tracking transistor, wherein the loading stage circuit generates the first stage output based on the first loading current and the second loading current.

8. The operational amplifier circuit according to claim 7, wherein the first loading current and the second loading current flow from the first input circuit to the first current source.

9. The operational amplifier circuit according to claim 6, wherein a first loading current flows from the first input circuit to the loading stage circuit through the first tracking transistor and the third tracking transistor, and a second loading current flows from the first input circuit to the loading stage circuit through the second tracking transistor and the fourth tracking transistor, wherein the loading stage circuit generates the first stage output based on the first loading current and the second loading current.

10. The operational amplifier circuit according to claim 9, wherein the first loading current and the second loading current flow from the first current source to the first input circuit.

11. The operational amplifier circuit according to claim 6, wherein a size of the first input transistor is substantially equal to a size of the second input transistor, a size of the first tracking transistor is substantially equal to a size of the third tracking transistor, and a size of the second tracking transistor is substantially equal to a size of the fourth tracking transistor.

12. The operational amplifier circuit according to claim 6, wherein the first input transistor, the second input transistor, the first tracking transistor, the second tracking transistor, the third tracking transistor, and the fourth tracking transistor are NMOS transistors.

13. The operational amplifier circuit according to claim 6, wherein the first input transistor, the second input transistor, the first tracking transistor, the second tracking transistor, the third tracking transistor, and the fourth tracking transistor are PMOS transistors.

14. The operational amplifier circuit according to claim 1, wherein the differential input stage circuit further comprises: a second input circuit, comprising: a third input transistor, having a first terminal, a second terminal, and a control terminal for receiving a third input signal; and a fourth input transistor, having a first terminal, a second terminal, and a control terminal for receiving a fourth input signal; and a second current source, coupled to the second terminals of the third input transistor and the fourth input transistor.

15. The operational amplifier circuit according to claim 14, wherein the first input signal and the third input signal are identical.

16. The operational amplifier circuit according to claim 14, wherein the second input signal and the fourth input signal are identical.

17. The operational amplifier circuit according to claim 14, wherein the differential input stage circuit further comprises: a second voltage maintaining circuit, comprising: a fifth tracking transistor having a first terminal, a second terminal coupled to the first terminal of the third input transistor, and a control terminal coupled to the control terminal of the third input transistor and a sixth tracking transistor having a first terminal, a second terminal coupled to the first terminal of the fourth input transistor, and a control terminal coupled to the control terminal of the fourth input transistor, wherein the first terminal of the fifth tracking transistor and the first terminal of the sixth tracking transistor are respectively coupled to the loading stage circuit.

18. The operational amplifier circuit according to claim 17, wherein the second voltage maintaining circuit further comprises: a seventh tracking transistor having a first terminal coupled to the first terminal of the fifth tracking transistor, a second terminal coupled to the first terminal of the third input transistor, and a control terminal coupled to the control terminal of the fourth input transistor; and a eighth tracking transistor having a first terminal coupled to the first terminal of the sixth tracking transistor, a second terminal coupled to the first terminal of the fourth input transistor, and a control terminal coupled to the control terminal of the third input transistor.

19. The operational amplifier circuit according to claim 14, wherein the first input transistor and the third input transistor are complement; the second input transistor and the fourth input transistor are complement; and the first voltage maintaining circuit and the second voltage maintaining circuit are complement.

20. The operational amplifier circuit according to claim 1, further comprising: an output stage circuit, coupled to the loading stage circuit, for receiving the first stage output and generating a second stage output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 (prior art) shows a block diagram of an example operational amplifier.

[0028] FIG. 2A (prior art) shows a circuit diagram of an example differential input stage circuit.

[0029] FIG. 2B (prior art) shows a diagram illustrating a transconductance of the differential input stage circuit shown in FIG. 2A.

[0030] FIG. 2C (prior art) shows a diagram illustrating a relation between loading currents versus input voltage difference of the differential input stage circuit shown in FIG. 2A.

[0031] FIG. 3A shows an operational amplifier circuit having a linearity enhancement circuit according to one embodiment of the invention.

[0032] FIG. 3B is a schematic diagram illustrating a bias control circuit is used as the linearity enhancement circuit according to an embodiment of the invention.

[0033] FIG. 3C is a schematic diagram illustrating a voltage maintaining circuit is used as the linearity enhancement circuit according to another embodiment of the invention.

[0034] FIG. 4A shows an operational amplifier circuit having a bias control circuit and an NMOS differential pair according to an embodiment of the invention.

[0035] FIG. 4B shows a diagram illustrating a transconductance of the differential input stage circuit shown in FIG. 4A.

[0036] FIG. 5 shows an operational amplifier circuit having a bias control circuit and a PMOS differential pair according to an embodiment of the invention.

[0037] FIG. 6 shows a rail-to-rail operational amplifier circuit having bias control circuits according to an embodiment of the invention.

[0038] FIG. 7 shows an example implementation of the loading stage circuit and the output stage circuit together with the rail-to-rail architecture shown in FIG. 6.

[0039] FIG. 8A shows an operational amplifier circuit having a voltage maintaining circuit and an NMOS differential pair according to an embodiment of the invention.

[0040] FIG. 8B shows a diagram illustrating the loading currents versus input voltage difference of the differential input stage circuit shown in FIG. 8A.

[0041] FIG. 9 shows an operational amplifier circuit having a voltage maintaining circuit and a PMOS differential pair according to an embodiment of the invention.

[0042] FIG. 10 shows a rail-to-rail operational amplifier circuit having voltage maintaining circuits according to an embodiment of the invention.

[0043] FIG. 11 shows an example implementation of the loading stage circuit and the output stage circuit together with the rail-to-rail architecture shown in FIG. 10.

[0044] FIG. 12 shows an operational amplifier circuit having a voltage maintaining circuit and an NMOS differential pair according to another embodiment of the invention.

[0045] FIG. 13 shows an operational amplifier circuit having a voltage maintaining circuit and a PMOS differential pair according to another embodiment of the invention.

[0046] FIG. 14 shows a rail-to-rail operational amplifier circuit having voltage maintaining circuits according to another embodiment of the invention.

[0047] FIG. 15 shows an example implementation of the loading stage circuit and the output stage circuit together with the rail-to-rail architecture shown in FIG. 14.

[0048] FIG. 16 shows an operational amplifier circuit including multiple differential pairs according to one embodiment of the invention.

[0049] FIG. 17A shows a differential input stage circuit with voltage interpolation function according to one embodiment of the invention.

[0050] FIG. 17B shows the voltage levels of signals shown in FIG. 17A.

[0051] FIG. 18A shows a differential input stage circuit with voltage interpolation function according to one embodiment of the invention.

[0052] FIG. 18B shows the voltage levels of signals shown in FIG. 18A.

[0053] FIG. 19A shows a differential input stage circuit with voltage interpolation function according to another embodiment of the invention.

[0054] FIG. 19B shows the voltage levels of signals shown in FIG. 19A.

[0055] In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

DETAILED DESCRIPTION

[0056] FIG. 3A shows an operational amplifier circuit having a linearity enhancement circuit according to one embodiment of the invention. The operational amplifier circuit 20 includes a differential input stage circuit 211, a loading stage circuit 212 and an output stage circuit 231. In addition to an input circuit 211a for receiving the first input signal V.sub.in1 and the second input signal V.sub.in2 and a current source 211c, the differential input stage circuit 211 according to an embodiment of the present disclosure further includes a linearity enhancement circuit 211b being coupled to the input circuit 211a.

[0057] According to an embodiment of the present disclosure, one of the input circuit 211a and the linearity enhancement circuit 211b is coupled to the loading stage circuit 212 through a first loading terminal NId1 and a second loading terminal NId2, and the other of the input circuit 211a and the linearity enhancement circuit 211b is coupled to the current source 211c.

[0058] The linearity enhancement circuit 211b can be implemented in different manner, for example, a bias control circuit, a voltage maintaining circuit and so forth. More details regarding implementation of the bias control circuit and the voltage maintaining circuit are used are illustrated below.

[0059] The operational amplifier circuit 20 may be used in a display device. For example, the output terminal of the loading stage circuit 212 may be coupled to an output stage circuit 231. The output stage circuit 31 may include power MOSFETs to provide sufficient driving capability. In one embodiment, the output stage circuit 231 is configured to provide a single-ended voltage signal (second stage output V.sub.O2) for driving a display panel.

[0060] FIG. 3B is a schematic diagram illustrating a bias control circuit is used as the linearity enhancement circuit according to an embodiment of the invention. In a case that the linearity enhancement circuit 211b is a bias control circuit 251b, the input circuit 251a is coupled to the first loading terminal NId1 and the second loading terminal NId2, and the bias control circuit 251b is coupled to the current source 251c. FIGS. 4A, 4B, 5, 6 and 7 are schematic diagrams related to the embodiment that the differential input stage includes the bias control circuit.

[0061] FIG. 3C is a schematic diagram illustrating a voltage maintaining circuit is used as the linearity enhancement circuit according to another embodiment of the invention. In a case that the linearity enhancement circuit 211b is a voltage maintaining circuit 281b, the voltage maintaining circuit 281b is coupled to the first loading terminal NId1 and the second loading terminal NId2, and the input circuit 281a is coupled to the current source 281c. Moreover, both the voltage maintaining circuit 281b and the input circuit 281a receive the first input signal V.sub.in1 and the second input signal V.sub.in2.

[0062] As shown in FIG. 3C, the voltage maintaining circuit 281b further includes a first branch circuit 282 and a second branch circuit 283. The first branch circuit 282 receives the first input signal V.sub.in1 and generates the first loading current i.sub.1; and the second branch circuit 283 receives the second input signal V.sub.in2 and generates the second loading current i.sub.2. FIGS. 8A, 8B, 9, 10, 11 are schematic diagrams showing that the differential input stage includes a first type of the voltage maintaining circuit, and FIGS. 12, 13, 14 and 15 are diagrams showing that the differential input stage includes a second type of the voltage maintaining circuit.

[0063] In the following embodiments, PMOS transistors and NMOS transistors are used for illustration purpose. In practical applications, NMOS transistors may be replaced by NPN-type BJTs, and PMOS transistors may be replaced by PNP-type BJTs. In still another embodiment, other types of transistors such as junction gate field-effect transistor (JFET) may be used instead, or different types of transistors may be used in combination in one differential pair.

[0064] FIG. 4A shows an operational amplifier circuit having a bias control circuit and an NMOS differential pair according to an embodiment of the invention. The operational amplifier circuit 30 includes a differential input stage circuit 301 and a loading stage circuit 302. The differential input stage circuit 101 includes a current source I.sub.N, an input circuit 301a and a bias control circuit 301b. The input circuit 301a further includes input transistors Min1, Min2, and the bias control circuit 301b further includes transistors Mb1 and Mb2.

[0065] The control terminal of the input transistor Min1 receives a first input signal V.sub.in1. The control terminal of the input transistor Min2 receives a second input signal V.sub.in2. The first and the second input signals V.sub.in1, V.sub.in2 jointly form a pair of differential signal. Transistor Mb1 has a first terminal coupled to the second terminal of the input transistor Min1, a second terminal coupled to the current source I.sub.N, and a control terminal coupled to the control terminal of transistor Min2. Transistor Mb2 has a first terminal coupled to the second terminal of transistor Min2, a second terminal coupled to the current source I.sub.N, and a control terminal coupled to the control terminal of the input transistor Min1. The loading stage circuit 302 is coupled to the first terminal of the input transistor Min1 and the first terminal of the input transistor Min2, for generating an output signal V.sub.O at an output terminal of the operational amplifier circuit 11b.

[0066] In the example shown in FIG. 4A, transistors Min1, Min2, Mb1 and Mb2 are NMOS transistors. The first terminal, the second terminal, and the control terminal of an NMOS transistor may correspond to the drain terminal, the source terminal, and the gate terminal, respectively.

[0067] In one embodiment, the sizes (gate width W and gate length L) of the input transistors Min1 and Min2 are substantially equal (represented as

[00011]${\left(\frac{W}{L}\right)}_1$

in the following formulas). The sizes of transistors Mb1 and Mb2 are substantially equal (represented as

[00012]${\left(\frac{W}{L}\right)}_3$

in the following formulas).

[0068] As can be seen in FIG. 4A, the bias voltage of transistor Mb1 is a variable voltage. Similarly, the bias voltage of transistor Mb2 is also a variable voltage. The differential pair shown in FIG. 4 uses a variable bias control mechanism. In this circuit, the input transistors Min1 and Min2 operate in the saturation region. Transistors Mb1 and Mb2 operate in the triode region, acting as variable resistors. Transistors Mb1 and Mb2 are degeneration devices for the input transistors Min1 and Min2 respectively. Transistors Mb1 and Mb2 constitute a feedback loop at the second terminal (source terminal) of the input transistors Min1 and Min2, effectively extending the linear range of the operational amplifier circuit 301.

[0069] Refer to FIG. 4A, when the input voltage difference V.sub.in (V.sub.in=V.sub.in1V.sub.in2) is small, transistors Mb1 and Mb2 operate in the triode region. Taking transistor Mb1 for example, the resistance value between its drain terminal and its source terminal is controlled by the second input signal V.sub.in2. Similarly, the resistance value between the drain terminal and the source terminal of transistor Mb2 is controlled by the first input signal V.sub.in1. Consider the situation when the voltage of the first input signal V.sub.in1 increases and the voltage of the second input signal V.sub.in2 decreases, the loading current i.sub.1 will increase, and the loading current i.sub.2 will decrease. Because the resistance value between the drain terminal and the source terminal of transistor Mb1 increases (caused by decreased V.sub.in2), the increased loading current i.sub.1 will increase the voltage across the drain terminal and the source terminal of transistor Mb1. Because of such negative feedback, the increment (the amount that the voltage increases) of the gate-to-source voltage of the input transistor Min1 will be smaller than the increment of the first input signal V.sub.in1. Therefore, the increment of the loading current i.sub.1 decreases. On the other hand, the resistance value between the drain terminal and the source terminal of the input transistor Mb2 decreases (caused by increased V.sub.in1), the decreased loading current i.sub.2 will decrease the voltage across the drain terminal and the source terminal of transistor Mb2. The decrement of the gate-to-source voltage of transistor Min2 will be smaller than the decrement of the second input signal V.sub.in2. Therefore, the loading current i.sub.2 will not decrease rapidly. As described above, when the voltage of the first input signal V.sub.in1 increases and the voltage of the second input signal V.sub.in2 decreases, the change in the loading currents i.sub.t and i.sub.2 can be kept small, resulting in an improved linear range for the differential pair. The detailed analyses for current and voltage of the circuit shown in FIG. 4A are provided below.

Loading current i.sub.1 being calculated by current flowing through transistor Min1: i.sub.1=k.sub.1(V.sub.in1V.sub.S1V.sub.t1).sup.2
Loading current i.sub.t being calculated by current flowing through transistor Mb1: i.sub.1=k.sub.3(V.sub.in2V.sub.SV.sub.t3)(V.sub.S1V.sub.S)
Loading current i.sub.2 being calculated by current flowing through transistor Min2: i.sub.2=k.sub.2(V.sub.in2V.sub.S2V.sub.t2).sup.2
Loading current i.sub.2 being calculated by current flowing through transistor Mb2: i.sub.2=k.sub.4(V.sub.in1V.sub.SV.sub.t4)(V.sub.S2V.sub.S)
where i.sub.1+i.sub.2=I;

[00013]$k_1=k_2={}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_1;$$k_3=k_4={}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_3;$

V.sub.S is the source voltage of transistor Mb1 and Mb2; V.sub.S1 and V.sub.S2 are the source voltages of transistors Min1 and Min2 respectively.

[0070] When the input voltage difference V.sub.in is small, transistors Mb1 and Mb2 operate in the triode region, and the source voltages of these four transistors Min1, Min2, Mb1, Mb2 are close. In addition, the threshold voltages of these four transistors Min1, Min2, Mb1, Mb2 are also close. In addition, V.sub.t1=V.sub.t2=V.sub.t3=V.sub.t4=V.sub.t may be substituted in the above formulas. After formula manipulation and simplification, the loading currents i.sub.1, i.sub.2 may be expressed as:

[00014]$\begin{array}{cc}{i}_1\frac{I}{2}+\sqrt{{}_n.Math.{C_{\mathrm{ox}}\left(W.Math.\text{/}.Math.L\right)}_1.Math.I}\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right].Math.\left(\frac{.Math..Math.v_{\mathrm{in}}}{2}\right)\sqrt{1-{\frac{{}_n.Math.{C_{\mathrm{ox}}\left(W.Math.\text{/}.Math.L\right)}_1}{I}\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right]}^2.Math.{\left(\frac{.Math..Math.v_{\mathrm{in}}}{2}\right)}^2}& \left(\mathrm{Eq}..Math.10.Math.A\right)\\ i_2\frac{I}{2}-\sqrt{{}_n.Math.{C_{\mathrm{ox}}\left(W.Math.\text{/}.Math.L\right)}_1.Math.I}\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right].Math.\left(\frac{.Math..Math.v_{\mathrm{in}}}{2}\right)\sqrt{1-{\frac{{}_n.Math.{C_{\mathrm{ox}}\left(W.Math.\text{/}.Math.L\right)}_1}{I}\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right]}^2.Math.{\left(\frac{.Math..Math.v_{\mathrm{in}}}{2}\right)}^2}& \left(\mathrm{Eq}..Math.10.Math.B\right)\end{array}$

[0071] Based on Eq. 10A and Eq. 10B,

[00015]$\begin{array}{cc}\frac{.Math..Math.v_{\mathrm{in}}}{2}\frac{\sqrt{I.Math.\text{/}.Math.{}_n.Math.{C_{\mathrm{ox}}\left(W.Math.\text{/}.Math.L\right)}_1}}{1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}}& \left(\mathrm{Eq}..Math.11\right)\end{array}$

the loading currents i.sub.1 and i.sub.2 may be approximately represented as a linear relation as follows:

[00016]$\begin{array}{cc}{i}_1\frac{I}{2}+\sqrt{{}_n.Math.{C_{\mathrm{ox}}\left(W.Math.\text{/}.Math.L\right)}_1.Math.I}\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right].Math.\left(\frac{.Math..Math.v_{\mathrm{in}}}{2}\right)& \left(\mathrm{Eq}..Math.12.Math.A\right)\\ i_2\frac{I}{2}-\sqrt{{}_n.Math.{C_{\mathrm{ox}}\left(W.Math.\text{/}.Math.L\right)}_1.Math.I}\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right].Math.\left(\frac{.Math..Math.v_{\mathrm{in}}}{2}\right)& \left(\mathrm{Eq}..Math.12.Math.B\right)\end{array}$

[0072] That is, when the condition in Eq. 11 is satisfied, the relation between the loading current i.sub.1 and the input voltage difference V.sub.in is linear. The transconductance Gm of the input stage circuit 301 shown in FIG. 4A is:

[00017]$\begin{array}{cc}{G}_m=\frac{i_1}{.Math..Math.v_{\mathrm{in}}.Math.\text{/}.Math.2}=\sqrt{{}_n.Math.{C_{\mathrm{ox}}\left(W.Math.\text{/}.Math.L\right)}_1.Math.I}\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right]& \left(\mathrm{Eq}..Math.13\right)\end{array}$

[0073] Comparing Eq. 13 with Eq. 4, the transconductance Gm of the differential pair (four transistor architecture, 4T) as shown in FIG. 4A is

[00018]$\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right]$

times of the transconductance Gm of the differential pair (two transistor architecture, 2T) as shown in FIG. 2A (the transconductance Gm is reduced). However, comparing Eq. 11 with Eq. 2, the linear range of the 4T differential pair is

[00019]$\left[1-\frac{3.Math.{\left(W.Math.\text{/}.Math.L\right)}_1}{2\left[{\left(W.Math.\text{/}.Math.L\right)}_1+{\left(W.Math.\text{/}.Math.L\right)}_3\right]}\right]$

times of the linear range of the 2T differential pair. In other words, the proposed differential input stage circuit shown in FIG. 4A is able to extend the linear range for the input voltage difference V.sub.in. In addition, a desired linear range can be designed by appropriately adjusting the size of the four transistors Mb1, Mb2, Min1, Min2 (adjusting

[00020]${\left(\frac{W}{L}\right)}_1.Math..Math.\mathrm{and}.Math..Math.{\left(\frac{W}{L}\right)}_3)$

based on the formula

[00021]$\frac{1}{\left[1-\frac{3.Math.{\left(W/L\right)}_1}{2\left[{\left(W/L\right)}_1+{\left(W/L\right)}_3\right]}\right]}.$

[0074] FIG. 4B shows a diagram illustrating a transconductance of the differential input stage circuit shown in FIG. 4A. The horizontal axis is the input voltage difference V.sub.in. When the input voltage difference V.sub.in exceeds +V2 (or less than V2), the transconductance Gm becomes 0, and hence the differential pair does not worker properly under such input voltage condition. Compare FIG. 4B with FIG. 2B, the input voltage range that results in a stable transconductance Gm is enlarged in FIG. 4B. V2>V1, and hence the linear range of the differential pair is greatly enhanced.

[0075] In the above embodiment NMOS transistors are used in the differential input stage circuit 301. In another embodiment, the differential input stage circuit 351 may include PMOS transistors instead. FIG. 5 shows an operational amplifier circuit having a bias control circuit and a PMOS differential pair according to an embodiment of the invention. The current source I.sub.P is coupled to a supply voltage Vdd. The connection topology and the operation are similar to those in FIG. 4A and thus are not repeated herein. In this embodiment, transistors Min1, Min2, Mb1, Mb2 are PMOS transistors. The first terminal, the second terminal, and the control terminal of a PMOS transistor may correspond to the drain terminal, the source terminal, and the gate terminal, respectively.

[0076] FIG. 6 shows a rail-to-rail operational amplifier circuit having bias control circuits according to an embodiment of the invention. In addition to transistors Min1a, Min2a, Mb1a, Mb2a in which interconnections are similar to the ones shown in FIG. 4A, the differential input stage circuit 401b in FIG. 6 also includes a first complementary current source I.sub.P and complementary transistors Min1b, Min2b, Mb1b and Mb2b. The complementary transistor Min1b has a first terminal, a second terminal, and a control terminal for receiving the first input signal V.sub.in1. The complementary transistor Min2b has a first terminal, a second terminal, and a control terminal for receiving the second input signal V.sub.in2. The complementary transistor Mb1b has a first terminal coupled to the second terminal of the complementary transistor Min1b, a second terminal coupled to the first complementary current source I.sub.P, and a control terminal coupled to the control terminal of the complementary transistor Min2b. The complementary transistor Mb2b has a first terminal coupled to the second terminal of the complementary transistor Min2b, a second terminal coupled to the first complementary current source I.sub.P, and a control terminal coupled to the control terminal of the complementary transistor Min1b. The loading stage circuit 402 is coupled to the first terminal of the complementary transistor Min1b and the first terminal of the complementary transistor Min2b.

[0077] The gate terminal of transistor Min1a and the gate terminal of the complementary transistor Min1b are coupled together. The gate terminal of transistor Min2a and the gate terminal of the complementary transistor Min2b are also coupled together. The connection relation between complementary transistors Min1b, Min2b, Mb1b, Mb2b is similar to that shown in FIG. 5. The rail-to-rail operational amplifier circuit 4 is able to provide a wider dynamic range for input signals and output signals.

[0078] In one embodiment, the sizes of the complementary transistors MP1 and MP2 are substantially equal. The sizes of the complementary transistors MP3 and MP4 are substantially equal.

[0079] FIG. 7 shows an example implementation of the loading stage circuit and the output stage circuit together with the rail-to-rail architecture shown in FIG. 6. The loading stage circuit 102 in this example includes the NMOS transistors Mln1, Mln2 and PMOS transistors Mlp1, M1p2. The output stage circuit 103 in this example includes the NMOS transistor Mon and PMOS transistor Mop. FIG. 7 shows merely an exemplary implementation. The circuit architecture for different applications may be modified correspondingly based on the design constraints, such as the voltage gain and bandwidth requirements.

[0080] According to another embodiment of the present disclosure, a voltage maintaining circuit is provided for tracking an input common mode voltage Vcm of the differential input pair so that the differential pair operates at the boundary of the triode region and the saturation region. The input common mode voltage Vcm of the differential input pair is equivalent to an average of the fist input signal V.sub.in1 and the second input signal Vin2.

[0081] FIG. 8A shows an operational amplifier circuit having a voltage maintaining circuit and an NMOS differential pair according to an embodiment of the invention. The control terminal of the first input transistor Min1 receives a first input signal V.sub.in1. The control terminal of the second input transistor Min2 receives a second input signal V.sub.in2. The first and the second input signals V.sub.in1, V.sub.in2 jointly form a pair of the differential input signals V.sub.in1, V.sub.in2.

[0082] The first branch circuit includes transistors Mt11 (first tracking transistor) and Mt12 (second tracking transistor), and the second branch circuit includes transistors Mt21 (third tracking transistor) and Mt22 (fourth tracking transistor).

[0083] The first terminals of transistors Mt11, Mt12, Mt21 and Mt22 are coupled to the loading stage circuit. The control terminals of transistors Mt11 and Mt21 are coupled to the control terminal of the first input transistor Min1. The control terminals of transistors Mt12 and Mt22 are coupled to the control terminal of the second input transistor Min2. The second terminals of transistors Mt11 and Mt12 are coupled to the first terminal of the first input transistor Min1. The second terminals of transistors Mt21 and Mt22 are coupled to the first terminal of the second input transistor Min2.

[0084] The loading stage circuit 502 is coupled to the first terminals of the transistors Mt11, Mt12, Mt21, Mt22, for generating an output signal V.sub.O at an output terminal of the operational amplifier circuit 50.

[0085] In the example shown in FIG. 8A, transistors Min1, Min2, Mb1 and Mb2 are NMOS transistors. The first terminal, the second terminal, and the control terminal of an NMOS transistor may correspond to the drain terminal, the source terminal, and the gate terminal, respectively.

[0086] In one embodiment, the sizes (gate width W and gate length L) of the input transistors Min1 and Min2 are substantially equal (represented as

[00022]${\left(\frac{W}{L}\right)}_1$

in the following formulas). The sizes of transistors Mt11 and Mt12 are substantially equal (represented as

[00023]${\left(\frac{W}{L}\right)}_3$

in the following formulas). The sizes of transistors Mt21 and Mt22 are substantially equal (represented as

[00024]${\left(\frac{W}{L}\right)}_5$

in the following formulas).

[0087] Refer to FIG. 8A, when the input voltage difference V.sub.in (V.sub.in=V.sub.in1V.sub.in2) is small, voltages of the second terminal of transistors Mt11 and Mt12 basically remain constant due to the characteristic of the differential pair. That is, a virtual ground phenomenon exists at the first terminals of the first input transistor Min1 and the second input transistor Min2. Due to the virtual ground phenomenon, voltages of the first terminals of the first and the second input transistors, that is, Vd1 and Vd2, can be remained constantly. The voltage of the first terminal Vd1 of the first input transistor Min1 can be obtained by subtracting the gate-to-source voltage Vgs of the first input transistor Min1 from an input common mode voltage Vcm. Similarly, the voltage of the first terminal Vd2 of the second input transistor Min2 can be obtained by subtracting the gate-to-source voltage Vgs of the second input transistor Min2 from the input common mode voltage Vcm.

[0088] Based on the constant voltages at their first terminals, both the first input transistor Min1 and the second input transistor Min2 are controlled to operate at the boundary of the triode region and the saturation region. Because both the first input transistor Min1 and the second input transistor Min2 operate in the triode region and the saturation region, the linearity of the differential input pair is better. Therefore, the design of the voltage maintaining circuit can improve linearity of the differential pair.

[0089] By assuming threshold voltages of all transistors in FIG. 8A are equivalent, the current and voltage of the circuit shown in FIG. 8A is provided below.

[0090] Firstly, the first input transistor Min1 operates in the triode region, and the loading current i1 can be calculated by the current flowing through the first input transistor Min1 as represented below, in which

[00025]$k_1={}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_1$

Loading current i.sub.1 being calculated by current flowing through transistor Min1: i.sub.1=k.sub.1(V.sub.in1V.sub.SV.sub.t)(V.sub.d1V.sub.S)

[0091] For the first branch circuit, the first branch current Ib1 is equivalent to summation of the first part of loading current i.sub.d11 as the current flowing through transistor Mt11 and the second part of loading current i.sub.d12 as the current flowing through transistor Mt12, that is, i.sub.b1=i.sub.d11+i.sub.d12. Transistors Mt11 and Mt12 operate in the saturation region, and the currents flowing through transistors Mt11 and Mt12 are shown below, together with the first branch current Ib1. In the following formulas,

[00026]$k_3={}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_3,\mathrm{and}.Math..Math.k_5={}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_5.$

First part of loading current i.sub.d11 being calculated by current flowing through transistor Mt11: i.sub.d11=k.sub.3(V.sub.in1V.sub.d1V.sub.t).sup.2
Second part of loading current i.sub.d12 being calculated by current flowing through transistor Mt12: i.sub.d12=k.sub.5(V.sub.in2V.sub.d1V.sub.t).sup.2
Loading current i.sub.b1 being calculated by current flowing through the first branch circuit: i.sub.b1=i.sub.d11+i.sub.d12=k.sub.3(V.sub.in1V.sub.d1V.sub.t).sup.2+k.sub.5(V.sub.in2V.sub.d1V.sub.t).sup.2

[0092] Similarly, the second input transistor Min2 operates in the triode region, and the drain current of the second input transistor Min2 can be represented below, in which

[00027]$k_2={}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_1$

Loading current being calculated by current flowing through transistor Min2: i.sub.2=k.sub.2(V.sub.in2V.sub.SV.sub.t)(V.sub.d2V.sub.5)

[0093] For the second branch circuit, the second branch current i.sub.b2 is equivalent to summation of the first part of loading current i.sub.d21 as the current flowing through transistor Mt21 and the second part of loading current i.sub.d22 as the current flowing through transistor Mt22, that is, i.sub.b2=i.sub.d21+i.sub.d22 The currents flowing through transistors Mt11 and Mt12 are shown below, together with the first branch current i.sub.b1. In the following formulas,

[00028]$k_4={}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_3,\mathrm{and}.Math..Math.k_5={}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_5.$

First part of loading current i.sub.d21 being calculated by current flowing through transistor Mt21: i.sub.d21=k.sub.4(V.sub.in1V.sub.d2V.sub.t).sup.2
Second part of loading current i.sub.d22 being calculated by current flowing through transistor Mt22: i.sub.d22=k.sub.6(V.sub.in2V.sub.d2V.sub.t).sup.2
Loading current i.sub.b2 being calculated by current flowing through the second branch circuit: i.sub.b2=i.sub.d21+i.sub.d22=k.sub.4(V.sub.in1V.sub.d2V.sub.t).sup.2+k.sub.6(V.sub.in2V.sub.d2V.sub.t).sup.2

[0094] In one embodiment, the sizes of transistors Min1a and Min2a are substantially equal. The sizes of transistors Mt11a, Mt12a, Mt21a and Mt22a are substantially equal.

[00029]$\begin{array}{cc}{i}_1=\frac{1}{2}+\frac{K}{2}.Math.\sqrt{k_1.Math.I}.Math.\left(\frac{.Math..Math.V_{\mathrm{in}}}{2}\right).Math.\sqrt{1-\frac{{\left(.Math..Math.v_{\mathrm{in}}/2\right)}^2}{4.Math.I/K^2.Math.k_1}}& \left(\mathrm{Eq}..Math.14.Math.A\right)\\ i_2=\frac{1}{2}-\frac{K}{2}.Math.\sqrt{k_1.Math.I}.Math.\left(\frac{.Math..Math.V_{\mathrm{in}}}{2}\right).Math.\sqrt{1-\frac{{\left(.Math..Math.v_{\mathrm{in}}/2\right)}^2}{4.Math.I/K^2.Math.k_1}}& \left(\mathrm{Eq}..Math.14.Math.B\right)\end{array}$

[0095] In Eq. 14A and Eq. 14B, K is less than 1 and can be represented by k1, k2, k3, k4, and k5, as shown by Eq. 15.

[00030]$\begin{array}{cc}K=\frac{k_1^2+2.Math.k_3^2+3.Math.k_1.Math.k_3-3.Math.k_1.Math.k_5}{k_1^2+k_3^2+k_5^2+2.Math.k_1.Math.k_3+2.Math.k_1.Math.k_5+2.Math.k_3.Math.k_5}& \left(\mathrm{Eq}..Math.15\right)\end{array}$

[0096] Based on Eq. 14A and Eq. 14B, when

[00031]$\begin{array}{cc}\frac{.Math..Math.v_{\mathrm{in}}}{2}.Math.\frac{2}{K}.Math.\sqrt{\frac{1}{k.Math..Math.1}}=\frac{2}{K}.Math.\sqrt{\frac{I}{{}_n.Math.{C_{\mathrm{ox}}\left(\frac{W}{L}\right)}_1}},& \left(\mathrm{Eq}..Math.16\right)\end{array}$

the drain currents i1 and i2 may be approximately represented as a linear relation as follows:

[00032]$\begin{array}{cc}{i}_1\frac{1}{2}+\frac{K}{2}.Math.\sqrt{k_1.Math.I}.Math.\left(\frac{.Math..Math.V_{\mathrm{in}}}{2}\right)& \left(\mathrm{Eq}..Math.17.Math.A\right)\\ i_2\frac{1}{2}-\frac{K}{2}.Math.\sqrt{k_1.Math.I}.Math.\left(\frac{.Math..Math.V_{\mathrm{in}}}{2}\right)& \left(\mathrm{Eq}..Math.17.Math.B\right)\end{array}$

[0097] That is, when the condition in Eq. 16 is satisfied, the relation between the drain currents and the input voltage difference V.sub.in is linear. The transconductance (Gm) of the differential input pair shown in FIG. 8A is:

[00033]$\begin{array}{cc}{G}_m=\frac{i_1}{.Math..Math.v_{\mathrm{in}}/2}=\frac{K}{2}.Math.\sqrt{k_1.Math.I}=\frac{K}{2}.Math.\sqrt{{}_n.Math.{C_{\mathrm{OX}}\left(W/L\right)}_1.Math.I}& \left(\mathrm{Eq}..Math.18\right)\end{array}$

[0098] Comparing Eq. 17 with Eq. 4, the transconductance Gm of the differential pair (six transistor architecture, 6T) as shown in FIG. 8A is K/2 times of the transconductance Gm of the differential pair (two transistor architecture, 2T) as shown in FIG. 2A (the transconductance Gm in FIG. 8A is reduced to less than half of the transconductance Gm in FIG. 2A). As defined in Eq. 15, K is always smaller than 1. Based on the scheme shown in FIG. 8A, range of the input voltage difference V.sub.in can be increased to 2/K times under the circumstance that the differential input pair having same linearity. As K is smaller than 1, the multiple 2/K is greater than 2, which implies that range of the input voltage difference V.sub.in is increased by at least two times. In addition, a desired linear range can be designed by appropriately adjusting aspect ratios of transistors Min1, Min2, Mt11, Mt12, Mt21, Mt22.

[0099] FIG. 8B shows a diagram illustrating the loading currents versus input voltage difference of the differential input stage circuit shown in FIG. 8A. The horizontal axis is the input voltage difference V.sub.in. When the input voltage difference V.sub.in exceeds +V2 (or less than V2), the loading currents i.sub.1, i.sub.2 become constant, and hence the differential pair does not worker properly under such input voltage condition. Compare FIG. 8B with FIG. 2C, the input voltage range that results in a relation corresponding to a constant slope is enlarged in FIG. 8B. V2>V1, and hence the linear range of the differential pair is greatly enhanced.

[0100] In the above embodiment NMOS transistors are used in the differential input stage circuit 501.

[0101] FIG. 9 shows an operational amplifier circuit having a voltage maintaining circuit and a PMOS differential pair according to an embodiment of the invention. The connection topology and the operation are similar to those in FIG. 8A and thus are not repeated herein. In this embodiment, transistors Min1, Min2, Mt11, Mt12, Mt21 and Mt22 are PMOS transistors. The first terminal, the second terminal, and the control terminal of a PMOS transistor may correspond to the drain terminal, the source terminal and the gate terminal, respectively.

[0102] In one embodiment, the sizes of the input transistors Min1a and Min2a are substantially equal. The sizes of transistors Mt11a, Mt12a, Mt21a and Mt22a are substantially equal.

[0103] FIG. 10 shows a rail-to-rail operational amplifier circuit having voltage maintaining circuits according to an embodiment of the invention. The rail-to-rail operational amplifier circuit 60 is able to provide a wider dynamic range for input signals and output signals. As shown in FIG. 10, the differential input stage includes two complement portions, that is, a first potion and a second portion. In FIG. 10, the first portion and the second portion are assumed to be the lower part and the upper part of the differential input stage circuit, respectively.

[0104] In FIG. 10, the first portion of the differential input stage is similar to the circuit shown in FIG. 8A and includes a first input circuit, a first voltage maintaining circuit, and a current source. The first input circuit includes the input transistors Min1a and Min2a, the first voltage maintaining circuit includes transistors Mt11a, Mt12a, Mt21a and Mt22a.

[0105] In FIG. 10, the second portion of the differential input stage is similar to the circuit shown in FIG. 9 and includes a second input circuit, a second voltage maintaining circuit, and a second current source. The second input circuit includes the input transistors Min1b and Min2b, and the second voltage maintaining circuit includes transistors Mt11b, Mt12b, Mt21b and Mt22b.

[0106] FIG. 11 shows an example implementation of the loading stage circuit and the output stage circuit together with the rail-to-rail architecture shown in FIG. 10. The loading stage circuit 102 in this example includes the NMOS transistors Mln1, Mln2 and PMOS transistors MPlp1, Mlp26. The output stage circuit 103 in this example includes the NMOS transistor Mon and PMOS transistor Mop. FIG. 11 shows merely an exemplary implementation. The circuit architecture for different applications may be modified correspondingly based on the design constraints, such as the voltage gain and bandwidth requirements.

[0107] In order to reduce the amount of transistors in the voltage maintaining circuit, the circuit shown in FIG. 8A and be modified to obtain FIG. 12. FIG. 12 shows an operational amplifier circuit having a voltage maintaining circuit and an NMOS differential pair according to another embodiment of the invention.

[0108] The first branch circuit includes a transistor Mt1 (as a first tracking transistor) and the second branch circuit includes a transistor Mt2 (as a second tracking transistor). The first terminals of transistors Mt1 and Mt2 are coupled to the loading stage circuit 702. The control terminal of transistor Mt1 is coupled to the control terminal of the first input transistor Min1. The control terminal of transistor Mt2 is coupled to the control terminal of the second input transistor Min2. The second terminal of transistor Mt1 is coupled to the first terminal of the first input transistor Min1. The second terminal of transistor Mt2 is coupled to the first terminal of the second input transistor Min2.

[0109] In FIG. 12, the voltage of the first terminal of first input transistor (Min1) Vd1 can be obtained by subtracting the gate-to-source voltage Vgs of the first input transistor Mt1 from the first input signal Vin1, and the voltage of the first terminal of the second input transistor (Min2) Vd2 can be obtained by subtracting the gate-to-source voltage Vgs of the second input transistor Mt2 from the second input signal Vin2.

[0110] When the input voltage changes, difference between the first input signal V.sub.in1 and the drain terminal of the first input transistor Min1 is the gate-to-source voltage Vgs of transistor Mt1, which implies that the first input transistor Min1 operates at the boundary of the triode region and the saturation region. Similarly, difference between the second input signal V.sub.in2 and the drain terminal of the second input transistor Min2 is the gate-to-source voltage Vgs of transistor Mt2, and the second input transistor Min2 operates at the boundary of the triode region and the saturation region as well. Because both the first input transistor Min1 and the second input transistor Min2 operate at he the triode region and the saturation region, the linearity of FIG. 12 is better, compared with the ones in FIG. 2A.

[0111] FIG. 13 shows an operational amplifier circuit having a voltage maintaining circuit and a PMOS differential pair according to another embodiment of the invention. The connection topology and the operation are similar to those in FIG. 12 and thus are not repeated herein. In this embodiment, transistors Min1, Min2, Mt11, Mt1 and Mt2 are PMOS transistors. The first terminal, the second terminal, and the control terminal of a PMOS transistor may correspond to the drain terminal, the source terminal, and the gate terminal, respectively.

[0112] FIG. 14 shows a rail-to-rail operational amplifier circuit having voltage maintaining circuits according to another embodiment of the invention. The rail-to-rail operational amplifier circuit 80 is able to provide a wider dynamic range for input signals and output signals. As shown in FIG. 14, the differential input stage includes two complement portions, that is, a first potion and a second portion. In FIG. 14, the first portion and the second portion are assumed to be the lower part and the upper part of the differential input stage circuit, respectively.

[0113] In FIG. 14, the first portion of the differential input stage circuit is similar to the circuit shown in FIG. 12 and includes a first input circuit, a first voltage maintaining circuit, and a current source. The first input circuit includes the input transistors Min1a and Min2a, the first voltage maintaining circuit includes transistors Mt1a, Mt2b.

[0114] In FIG. 14, the second portion of the differential input stage is similar to the circuit shown in FIG. 13 and includes a second input circuit, a second voltage maintaining circuit, and a second current source. The second input circuit includes the input transistors Min1b and Min2b, and the second voltage maintaining circuit includes transistors Mt1b, Mt2b.

[0115] FIG. 15 shows an example implementation of the loading stage circuit and the output stage circuit together with the rail-to-rail architecture shown in FIG. 14. The loading stage circuit 802 in this example includes the NMOS transistors Mln1, Mln2 and PMOS transistors Mlp1, Mlp2. The output stage circuit 103 in this example includes the NMOS transistor Mon and PMOS transistor Mop. FIG. 15 shows merely an exemplary implementation. The circuit architecture for different applications may be modified correspondingly based on the design constraints, such as the voltage gain and bandwidth requirements.

[0116] In LCD driver applications, an operational amplifier circuit may include multiple differential pairs to achieve voltage interpolation function. Such circuit design can reduce chip area and production cost. In some applications, more differential pairs may be accommodated. The loading stage circuit is not illustrated in following figures for simplicity reason.

[0117] FIG. 16 shows an operational amplifier circuit including multiple differential pairs according to one embodiment of the invention. In this example, the differential input stage circuit 90 includes four differential pairs 931-934. Note that the number of total differential pairs may be other numbers, four differential pairs illustrated in this example is just exemplary rather than limiting. The first differential pair 931 receives an input signal V.sub.G1 and the output signal V.sub.O fed back from the loading stage circuit 102. Similarly, the second differential pair 932 receives another input signal V.sub.G2 and the output signal V.sub.O. The output signal V.sub.O is an interpolation result of the input signals V.sub.G1-V.sub.G4. By adopting the above mentioned 4T and/or 6T architecture in the differential pairs 931-934, the extended linear range helps to reduce the output error of the operational amplifier circuit 9.

[0118] According to the embodiments given above, the operational amplifier circuit can effectively extend the linear range for the input voltage difference V.sub.in. The extended linear range can be designed to a desired value by appropriately adjusting the transistor size. In addition, the operational amplifier circuit can include multiple 4T and/or 6T differential pairs to achieve voltage interpolation function.

[0119] To further illustrate the concept that how differential pairs in the differential input stage circuit are placed in parallel, two differential pairs are illustrated in the examples shown in FIG. 17A, 18A and FIG. 19A.

[0120] FIG. 17A is corresponding the case regarding the differential input stage circuit uses the bias control circuit. FIGS. 18A and 19A are corresponding to the cases regarding the differential input stage circuit uses the first type and the second type of the voltage maintaining circuit, respectively.

[0121] FIG. 17A shows a differential input stage circuit with voltage interpolation function according to one embodiment of the invention. The differential input stage circuit 901a includes a first differential pair 931a and a second differential pair 932a. The differential input stage circuit 901a is utilized for interpolating input signals V.sub.G1 and V.sub.G2 to generate the output signal V.sub.Out according to a superposition principle. The output signal V.sub.Out of the differential operational amplifier is fed back to the differential input stage circuit 901a in this example.

[0122] The transconductance of the first differential pair 931a is Gm1, and the transconductance of the second differential pair 932a is Gm2. By the superposition principle, the output signal V.sub.Out may be expressed as:

[00034]$\begin{array}{cc}{V}_{\mathrm{Out}}=\frac{\mathrm{Gm}.Math..Math.1V_{G.Math..Math.1}+\mathrm{Gm}.Math..Math.2V_{G.Math..Math.2}}{\mathrm{Gm}.Math..Math.1+\mathrm{Gm}.Math..Math.2}& \left(\mathrm{Eq}..Math.19\right)\end{array}$

[0123] Gm1=Gm2 in an ideal case (V.sub.O=0.5V.sub.G1+0.5V.sub.G2). However, refer to FIGS. 2A and 2B, the linear range of the 2T differential pair is relatively small. Consequently, Gm1Gm2 when the voltage difference between the input signals V.sub.G1 and V.sub.G2 is large. Therefore the real output signal V.sub.Out deviates from the ideal value. FIG. 17B shows the voltage levels of signals shown in FIG. 17A. There is an error V3 between the ideal output and the real output signal.

[0124] FIG. 18A shows a differential input stage circuit with voltage interpolation function according to one embodiment of the invention. The differential input stage circuit 901b includes two subsets, a first subset including a current source Is, and transistors Min11, Min12, Mb11, Mb12, and a second subset including a current source I.sub.S2 and transistors Min21, Min22, Mb21, Mb22. All components and interconnections in both the first and the second subsets are connected as the ones shown in FIG. 4A.

[0125] In FIG. 18A, the control terminal of transistor Min2l receives the input signal V.sub.G2, and the control terminal of transistor Min22 receives the output signal V.sub.Out. In FIG. 18A, the control terminals of the input transistors Min12 and Min22 are assumed to be coupled together to accomplish the voltage interpolation function. Accordingly, the output signal V.sub.Out is an interpolation result of the input signals V.sub.G1 and V.sub.G2. The interpolation formula has been shown in the example of FIG. 17A.

[0126] In one embodiment, transistors Min21, Min22, Mb21, Mb22 are NMOS transistors, which are of the same type as transistors Min11, Min12, Mb11, Mb12. In one embodiment, the sizes of transistors Min2l and Min22 are substantially equal. The size of transistors Mb21 and Mb22 are substantially equal.

[0127] Because 6T differential pairs are used in the example in FIG. 18A, the linear range for input voltage difference V.sub.in is extended. As a result, the difference between the transconductance Gm1 of the first differential pair 931b and the transconductance Gm2 of the second differential pair 932b becomes smaller. The real output signal V.sub.Out(Real) will be closer to the ideal output signal V.sub.Out(Ideal).

[0128] FIG. 18B shows the voltage levels of signals shown in FIG. 18A. There is an error V4 between the ideal output and the real output signal. As compared to FIG. 17B, V4<V3. The extended linear range for the differential pair improves the accuracy of the voltage interpolation result.

[0129] FIG. 19A shows a differential input stage circuit with voltage interpolation function according to another embodiment of the invention. The differential input stage circuit 901c includes two subsets, a first subset including a current source I.sub.S1 and transistors Min11, Min12, Mt11a, Mt11b, Mt12a, Mt12b, and a second subset including a current source I.sub.S2 and transistors Min21, Min22, Mt21a, Mt21b, Mt22a, Mt22b. All components and interconnections in both the first and the second subsets are connected as the ones shown in FIG. 8A.

[0130] In FIG. 19A, the control terminals of transistors Min2l and Mt21a receives the input signal V.sub.G2, and the control terminals of transistors Min22, Mt22b receives the output signal V.sub.Out. In FIG. 19A, the control terminals of the input transistors Min12 and Min22 are assumed to be coupled together to accomplish the voltage interpolation function. Accordingly, the output signal V.sub.Out is an interpolation result of the input signals V.sub.G1 and V.sub.G2. The interpolation formula has been shown in the example of FIG. 17A.

[0131] In one embodiment, transistors Min2l, Min22, Mt21a, Mt21b, Mt22a, Mt22b are NMOS transistors, which are of the same type as transistors Min11, Min12, Mt11a, Mt11b, Mt12a, Mt12b. In one embodiment, the sizes of transistor Min2l and Min22 are substantially equal. The sizes of transistors Mt21a, Mt21b, Mt22a and Mt22b are substantially equal.

[0132] Because 6T differential pairs are used in the example in FIG. 19A, the linear range for input voltage difference V.sub.in is extended. As a result, the difference between the transconductance Gm1 of the first differential pair 931c and the transconductance Gm2 of the second differential pair 932c becomes smaller. The real output signal will be closer to the ideal output signal.

[0133] FIG. 19B shows the voltage levels of signals shown in FIG. 19A. There is an error V5 between the ideal output and the real output signal. As compared to FIG. 17B, V5<V3. The extended linear range for the differential pair improves the accuracy of the voltage interpolation result.

[0134] In LCD driver applications, the operational amplifier circuit is often preceded by a digital-to-analog converter (DAC). The proposed operational amplifier circuit adopts different structures to allow a larger range for the input voltage difference. Therefore the resolution requirement for the preceding DAC can be relaxed. In other words, the hardware cost for the DAC circuit can be effectively reduced because of the extended linear range of the proposed operational amplifier circuit.

[0135] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.