Receiver unit

Abstract

A receiver unit having an optically operated voltage source, the voltage source including a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in the shape of a stack, and having a second electrical terminal contact on the upper side of the first stack and a first electrical terminal contact on an underside of the non-Si substrate, a voltage generated with the aid of the incidence of light onto the upper side of the first stack being present between the two terminal contacts, and including a second stack having a MOS transistor structure having III-V semiconductor layers and including a control terminal and a drain terminal and a source terminal. The MOS transistor structure being designed as a depletion field effect transistor.

Claims

1. A receiver unit having an optically operated voltage source, the receiver unit comprising: a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in a shape of a stack; a first electrical terminal contact disposed on an underside of the non-Si substrate, a second electrical terminal contact disposed on the upper side of the first stack, a voltage being generated via incident light on the upper side of the first stack that is disposed between the two terminal contacts; and a second stack having a FET transistor structure comprising III-V semiconductor layers that include a control terminal and a drain terminal and a source terminal, wherein the FET transistor structure is a depletion field effect transistor, wherein the control terminal is connected to one of the two terminal contacts, and the drain terminal is connected to the other of the two terminal contacts, and wherein the field effect transistor short-circuits the two terminal contacts if the generated voltage drops below a threshold value.

2. The receiver unit according to claim 1, wherein the drain terminal is connected to the first terminal contact, and the control terminal is connected to the second terminal contact.

3. The receiver unit according to claim 1, wherein the field effect transistor is designed as an N-channel depletion FET transistor or as a P-channel depletion FET transistor.

4. The receiver unit according to claim 1, wherein the first terminal contact is connected to a first output terminal, and wherein the source terminal is connected to a second output terminal.

5. The receiver unit according to claim 1, wherein the FET structure is a second stack having an upper side and an underside in a partial area on the upper side of the first stack, and wherein the III-V semiconductor layers of the two stacks are monolithically integrated.

6. The receiver unit according to claim 1, wherein the first stack has a quadrilateral shape and the side surfaces of the first stack are recessed on the upper side of the non-Si substrate so that a first circumferential, stepped shoulder is formed.

7. The receiver unit according to claim 1, wherein the second stack is recessed from an edge on the upper side of the first stack so that a second circumferential, stepped shoulder is formed, the second stack having an essentially smaller base surface than the first stack and being disposed asymmetrically on the surface of the first stack.

8. The receiver unit according to claim 1, wherein an opaque layer is disposed on the FET transistor structure to protect the FET transistor structure against the incidence of light, and wherein a first III-V insulation layer is formed on the underside of the second stack to electrically insulate the FET transistor structure from the voltage source.

9. The receiver unit according to claim 1, wherein the FET transistor structure includes a first transistor layer designed as a channel layer and disposed above the insulation layer, and wherein a second transistor layer is formed above the channel layer.

10. The receiver unit according to claim 1, wherein the voltage source includes multiple p-n diodes, wherein a tunnel diode is formed between each of two consecutive p-n diodes, and wherein the p-n diodes each have a same band gap.

11. The receiver unit according to claim 1, wherein the second terminal contact is connected to a second output terminal.

12. The receiver unit according to claim 1, wherein the control terminal and the source terminal are short-circuited with respect to each other.

13. The receiver unit according to claim 1, wherein a Schottky diode is looped in between the control terminal and the source terminal.

14. The receiver unit according to claim 1, wherein the first stack is disposed on the second stack, wherein the first stack is recessed from an edge so that a second circumferential, stepped shoulder is formed, and wherein the second stack has a smaller base surface than the first stack.

15. The receiver unit according to claim 1, wherein the first stack is disposed laterally next to the second stack, and wherein a filled trench is formed between the two stacks.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:

(2) FIG. 1 shows a receiver unit according to an embodiment;

(3) FIG. 2 shows an equivalent diagram, including an N-channel FET transistor, of a receiver unit, with the addition of a Schottky diode;

(4) FIG. 3 shows a voltage curve of the receiver unit;

(5) FIG. 4 shows an equivalent diagram, including a P-channel FET transistor, of a receiver unit, to which a Schottky is added;

(6) FIG. 5 shows an equivalent diagram of a receiver unit, including the N-channel FET transistor without a Schottky diode;

(7) FIG. 6 shows an equivalent diagram of a receiver unit, including the P-channel FET transistor without a Schottky diode;

(8) FIG. 7 shows a receiver unit in an embodiment;

(9) FIG. 8 shows a receiver unit in an embodiment.

DETAILED DESCRIPTION

(10) The illustration in FIG. 1 shows a receiver unit EM in an embodiment. A receiver unit EM of this type is preferably integrated together with a transmitter into a shared housing as part of an optocoupler.

(11) Receiver unit EM comprises an optically operated voltage source SP in a first stack SP1, formed on the basis of III-V semiconductor layers arranged in the shape of a stack. First stack SP1 has an upper side OSP1 and an underside USP1 and is disposed with underside USP1 on an upper side OS1 of a non-Si substrate NSSUB.

(12) Voltage source SP has a first electrical terminal contact K1 on an underside US1 of non-Si substrate NSSUB. A second electrical terminal contact K2 is formed on an upper side OSP1 of the stack of the III-V semiconductor layers. An incidence of light L takes place only on upper side OSP1 of the stack.

(13) Voltage source SP includes a first diode D1 and a second diode D2 supported on the non-Si substrate. A tunnel diode T1 is formed between first diode D1 and second diode D2. The two diodes D1 and D2 are connected in series with the aid of tunnel diode T1. In other words, the partial voltages of the two diodes D1 and D2 add up.

(14) Upon an incidence of light L onto the upper side of first stack SP1, a voltage generated with the aid of light L is present between the two terminal contacts K1 and K2.

(15) To avoid short-circuits on the side surfaces, in particular, the layers of voltage source SP, i.e. of first stack SP1, are recessed on all sides with respect to non-Si substrate NSSUB, so that an first circumferential, stepped shoulder STU1 forms.

(16) A second stack SP2, which includes a FET transistor structure FET1 having III-V semiconductor layers, is formed on upper side OSP1 of first stack SP2. Second stack SP2 has an upper side OSP2 and an underside USP2.

(17) FET transistor structure FET1, which in the present case is designed as an N-channel depletion field-effect transistor, includes a control terminal G1 and a drain terminal DR1 and a source terminal S1.

(18) Second stack SP2 has a much smaller base surface than does first stack SP1 and is disposed asymmetrically on upper side OSP1 of first stack SP1, i.e. it is situated at a different distance from the edge of upper side OSP1.

(19) Second stack SP2 is thus recessed on all sides with respect to the edge of first stack SP1, so that a second circumferential, stepped shoulder STU2 forms.

(20) A III-V insulation layer ISO1 is formed on the underside of second stack SP2 to electrically insulate FET transistor structure FET1 from voltage source SP.

(21) A first transistor layer TS1, designed as a channel layer, is disposed above insulation layer ISO1. A second transistor layer RS1 is formed above the channel layer.

(22) Drain terminal DR1 is connected to first terminal contact K1 and to first output terminal OUT1. Control terminal G1 and source terminal S1 are connected to second terminal contact K2 and to a second output terminal OUT2.

(23) A Schottky diode SKYD1 is looped between control terminal G1 and source terminal S1.

(24) The field effect transistor short-circuits the two terminal contacts K1 and K2 or the two output terminals OUT1 and OUT2, if the generated voltage drops below a threshold value, i.e. below the threshold voltage of the field effect transistor.

(25) The illustration in FIG. 2 shows an equivalent diagram of a receiver unit EM according to the first specific embodiment. Only the differences from the specific embodiment illustrated in FIG. 1 are explained below.

(26) Schottky diode SKYD1 is looped between control terminal G1 and source terminal S1 to bias the potential at control terminal G1 with respect to source terminal S1, i.e. if the operating voltage is present at voltage source SP, the field effect transistor is blocked.

(27) By looping in Schottky diode SKYD1, the potential at second output terminal OUT2 is reduced compared to the potential at second terminal contact K2 by a small voltage drop, since Schottky diode SKYD1 is polarized in the forward direction during operation.

(28) The illustration in FIG. 3 shows a voltage curve of receiver unit EM according to the first specific embodiment. Only the differences from the specific embodiment illustrated in FIG. 1 are explained below.

(29) The time profile of the voltage of voltage source SP is plotted. At a point in time t.sub.on, upper side OSP1 of first stack SP1 is irradiated with light L, and at a point in time t.sub.off, light L is turned off.

(30) It is apparent that the voltage rapidly increases to a maximum value at point in time t.sub.on and, after deactivation, has a decay curve AF1 without the field effect transistor and a decay curve AF2 with the field effect transistor. In other words, the decay behavior of the voltage source is greatly improved with the aid of the field effect transistor.

(31) The illustration in FIG. 4 shows an equivalent diagram of a receiver unit, including a P-channel FET transistor, to which a Schottky diode is added. Only the differences from the specific embodiment illustrated in FIG. 1 are explained below.

(32) In the present case, FET transistor structure FET1 is designed as a p-channel depletion field effect transistor.

(33) Control terminal G1 is connected to first terminal contact K1, and source terminal S1 is connected to first output terminal OUT1.

(34) Schottky diode SKYD1 is looped in between control terminal G1 and source terminal S1 to bias the potential at control terminal G1 with respect to source terminal S1, i.e. if the operating voltage is present at voltage source SP, the field effect transistor is blocked.

(35) By looping in Schottky diode SKYD1, the potential at first output terminal OUT1 is reduced compared to the potential at second terminal contact K2 by a small voltage drop, since Schottky diode SKYD1 is polarized in the forward direction during operation.

(36) Drain terminal DR1 is connected to second terminal contact K2 and to second output terminal OUT2.

(37) The field effect transistor short-circuits the two terminal contacts K1 and K2 and the two output terminals OUT1 and OUT2, if the generated voltage drops below a threshold value, i.e. below the threshold voltage of the field effect transistor.

(38) The illustration in FIG. 5 shows an equivalent diagram of a receiver unit EM, including the N-channel FET transistor, without a Schottky diode. Only the differences from the specific embodiment illustrated in FIG. 2 are explained below.

(39) Schottky diode SKYD1 is omitted between control terminal G1 and source terminal S1 of N-channel FET transistor FET1, i.e. the potential at control terminal G1 is not biased with respect to source terminal S1. If the operating voltage is present at voltage source SP, the field effect transistor is nevertheless blocked in that one part of the channel remains closed between drain terminal DR1 and control terminal G1 with the aid of the operating voltage present there.

(40) The illustration in FIG. 6 shows an equivalent diagram of a receiver unit EM, including the P-channel FET transistor, without the Schottky diode illustrated in FIG. 4. Only the differences from the specific embodiment illustrated in FIG. 4 are explained below.

(41) Schottky diode SKYD1 is omitted between control terminal G1 and source terminal S1 of P-channel FET transistors FET1, i.e. the potential at control terminal G1 is not biased with respect to source terminal S1. If the operating voltage is present at voltage source SP, the field effect transistor is nevertheless blocked in that one part of the channel remains closed between drain terminal DR1 and control terminal G1 with the aid of the operating voltage present there.

(42) The illustration in FIG. 7 shows a receiver unit EM in a second specific embodiment. Only the differences from the specific embodiment illustrated in FIG. 1 are explained below.

(43) First stack SP1 of receiver unit EM is disposed on second stack SP2. The second stack is disposed on non-Si substrate NSSUB.

(44) Second stack SP2 is designed to be laterally larger than first stack SP1 and comprises a preferably semi-insulating III-V semiconductor layer EGA formed on the non-Si substrate. In particular, III-V semiconductor layer EGA includes or is made up of GaAs.

(45) A channel layer CHL, which covers the entire surface, is formed above III-V semiconductor layer EGA. A laterally structured, electrically conductive III-V transistor layer TS3 is formed on channel layer CHL. Drain terminal DR1 and source terminal S1 are formed on transistor layer TS3. Control terminal G is formed between drain terminal DR1 and source terminal S1 on channel layer CHL. In an embodiment, an insulation layer, preferably comprising a dielectric such as Hf oxide and/or Si oxide and/or Si nitride, is formed beneath control terminal G1 in the area between drain terminal DR1 and source terminal S1.

(46) The illustration in FIG. 8 shows a receiver unit EM in a third specific embodiment. Only the differences from the specific embodiment shown in FIG. 1 and FIG. 7 are explained below.

(47) First stack SP1 of receiver unit EM is disposed laterally next to second stack SP2, the sequence of layers beneath second stack SP2 corresponds to the sequence of layers of first stack SP1. Both stacks SP1 and SP2 are each disposed on a shared non-Si substrate NSSUB.

(48) A trench ISOG is formed between the two stacks SP1 and SP2, trench ISOG being filled with an electrically insulating material. The material preferably comprises a dielectric, for example Hf oxide and/or Si oxide and/or Si nitride. Second terminal contact K2 is connected to either source terminal S1 or drain terminal DR1 with the aid of a printed conductor. First terminal contact K1 is disposed laterally next to first stack SP1 directly on the surface of the non-Si substrate.