Method of manufacturing light emitting device

Abstract

Shown is a method of manufacturing a light emitting device capable of efficiently heating a device at the time of DPP annealing and suppressing heat generation of the device at the time of driving. In the method of manufacturing the light emitting device, a first p-type electrode is formed on a low-concentration portion having a low p-type dopant concentration formed under a first region of the p-type semiconductor portion, a second p-type electrode is formed on a high-concentration portion having a high p-type dopant concentration formed under a second region of the p-type semiconductor portion, and a predetermined forward bias voltage is applied between the first p-type electrode and a first n-type electrode formed on an n-type semiconductor portion at the time of DPP annealing.

Claims

1. A method of manufacturing a light emitting device comprising: a device formation process of forming a device in which boron is ion-implanted in a concentration range of 110.sup.19 particles/cm.sup.3 or more and 110.sup.21 particles/cm.sup.3 or less into one surface in a thickness direction of a substrate formed of single-crystal silicon in which n-type dopants consisting of one or more of arsenic and antimony are uniformly diffused in a concentration range of 110.sup.14 particles/cm.sup.3 or more and 110.sup.16 particles/cm.sup.3 or less so that a p-type semiconductor portion in which diffusion is made to have a higher p-type dopant concentration than an n-type dopant concentration is formed on the one surface side, an n-type semiconductor portion in which n-type dopants are diffused is formed on the other surface side facing the one surface, and a pn junction portion is formed at a boundary portion between the p-type semiconductor portion and the n-type semiconductor portion; a first low resistance portion formation process of polishing a second region excluding a first region on the one surface or ion-implanting p-type dopants into the second region so that a p-type dopant concentration of the p-type semiconductor portion under the second region is 110.sup.19 particles/cm.sup.3 or more; a first electrode formation process of forming a first p-type electrode in the first region, a second p-type electrode independent from the first p-type electrode in the second region, and a first n-type electrode on the other surface; and a DPP annealing process of repeatedly changing distribution of dopants by diffusing p-type dopants and n-type dopants inside the pn junction portion with heat generated when a predetermined forward bias voltage is applied to the first p-type electrode and the first n-type electrode so that the side of p-type semiconductor portion has a positive voltage and the side of n-type semiconductor portion has a negative voltage to cause a current to flow in the pn junction portion, and decreasing the current flowing in the pn junction portion and reducing a temperature thereof to fix distribution of p-type dopants and n-type dopants inside the pn junction portion by causing a population inversion between a conduction band and a valence band to occur in the pn junction portion to induce and emit electrons in the conduction band forming the population inversion.

2. The method of manufacturing a light emitting device according to claim 1, further comprising: a first electrode removing process of removing the first n-type electrode after the DPP annealing process; a second low resistance portion formation process of adding n-type dopants so that an n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more; and a second electrode formation process of re-forming a second n-type electrode on the other surface.

3. The method of manufacturing a light emitting device according to claim 2, wherein, in the second low resistance portion formation process, the n-type semiconductor portion is polished as thin as possible within a range in which formation of the pn junction portion is possible and the n-type dopants are ion-implanted into the other surface so that the n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a perspective view of a device before processing according to the present embodiment.

(2) FIG. 2A to FIG. 2D are a view illustrating a manufacturing procedure of a light emitting device according to a first embodiment.

(3) FIG. 3A to FIG. 3D are a view illustrating a manufacturing procedure of a light emitting device according to a second embodiment.

(4) FIG. 4A to FIG. 4E are a view illustrating a manufacturing procedure of a light emitting device according to a third embodiment.

(5) FIG. 5A to FIG. 5E are a view illustrating a manufacturing procedure of a light emitting device according to a fourth embodiment.

(6) FIG. 6 is a graph showing correlations between a depth, a p-type dopant concentration, and an n-type dopant concentration of the silicon semiconductor device described in Non-Patent Document 1.

DESCRIPTION OF THE EMBODIMENTS

(7) In the disclosure, in the first low resistance portion formation process before the DPP annealing process, the second region excluding the first region on one surface is polished, or p-type dopants are ion-implanted into the second region so that a p-type dopant concentration of the p-type semiconductor portion under the second region is 110.sup.19 particles/cm.sup.3 or more. That is, in one surface, a p-type dopant concentration under the second region is increased while a p-type dopant concentration under the first region is maintained at a low concentration. In addition, an n-type dopant concentration diffused into the entire device is set low, and thus the n-type dopant concentration in the n-type semiconductor portion on the other surface side is low. Therefore, at the time of DPP annealing, by applying a voltage between the first p-type electrode formed in the first region on one surface and the first n-type electrode formed on the other surface, the entire device can be efficiently heated. Further, at the time of driving, by applying a voltage between the second p-type electrode formed in the second region and the first n-type electrode formed on the other surface, heat generation on one surface side can be suppressed.

(8) According to the method of manufacturing a light emitting device according to the invention, the invention further includes a first electrode removing process of removing the first n-type electrode after the DPP annealing process, a second low resistance portion formation process of adding n-type dopants so that an n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more, and a second electrode formation process of re-forming a second n-type electrode on the other surface.

(9) In the disclosure, in the second low resistance portion formation process before driving, an n-type dopant concentration of the n-type semiconductor portion is set to 110.sup.19 particles/cm.sup.3 or more by ion-implanting n-type dopants. That is, an n-type dopant concentration under the other surface is increased. Thus, since a concentration under the other surface can be increased in addition to the concentration under the second region of one surface which has already been increased, it is possible to suppress heat generation on both the one surface side and the other surface side, and heat generation of the entire device can be suppressed at the time of driving.

(10) According to the method of manufacturing a light emitting device of the invention, the invention provides that in the second low resistance portion formation process, the n-type semiconductor portion is polished as thin as possible within a range in which formation of the pn junction portion is possible and the n-type dopants are ion-implanted into the other surface so that the n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more.

(11) In the disclosure, in the second low resistance portion formation process, the n-type semiconductor portion is polished as thin as possible within a range in which the pn junction portion can be formed and the n-type dopants are ion-implanted into the other surface so that the n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more. Thereby, a volume of the device can be suppressed to the minimum, and heat generation during driving can be suppressed to the utmost.

(12) In the disclosure, the vicinity of one surface has a low p-type dopant concentration without fixation of p-type dopants. In addition, an n-type dopant concentration diffused into the entire device is set low, and thus the n-type dopant concentration in the n-type semiconductor portion on the other surface side is low. Therefore, by applying a voltage between the third p-type electrode formed on one surface and the third n-type electrode formed on the other surface, the entire device can be efficiently heated. Further, in the third low resistance portion formation process after the DPP annealing process, by polishing one surface or ion-implanting p-type dopants into one surface, the p-type dopant concentration of the p-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more. That is, the p-type dopant concentration under one surface is increased. Thereby, heat generation on one surface side at the time of driving can be suppressed.

(13) According to the method of manufacturing a light emitting device according to the invention, the invention further includes a third electrode removing process of removing the third n-type electrode after the DPP annealing process, a fourth low resistance portion formation process of adding n-type dopants so that an n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more, and a fifth electrode formation process of re-forming the third n-type electrode on the other surface.

(14) In the disclosure, in the fourth low resistance portion formation process before driving, n-type dopants are ion-implanted so that the n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more. That is, the n-type dopant concentration under the other surface is increased. Thus, since a concentration under the other surface can be increased in addition to the concentration under one surface which has already been increased, it is possible to suppress heat generation on both the one surface side and the other surface side, and heat generation of the entire device can be suppressed during driving.

(15) According to the method of manufacturing a light emitting device of the invention, the invention provides that in the fourth low resistance portion formation process, the n-type semiconductor portion is polished as thin as possible within a range in which formation of the pn junction portion is possible and the n-type dopants are ion-implanted into the other surface so that the n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more.

(16) In the disclosure, in the fourth low resistance portion formation process, the n-type semiconductor portion is polished as thin as possible within a range in which the pn junction portion can be formed and n-type dopants are ion-implanted into the other surface so that the n-type dopant concentration of the n-type semiconductor portion is 110.sup.19 particles/cm.sup.3 or more. Thereby, a volume of the device can be suppressed to the minimum, and heat generation during driving can be suppressed to the utmost.

(17) According to the method of manufacturing a light emitting device of the invention, the n-type dopants and the p-type dopants in the light emitting device are reversely configured.

(18) In the disclosure, the n-type dopants and the p-type dopants in the light emitting device are reversely configured. Therefore, the disclosure can be applied even when the n-type dopants and the p-type dopants are reversed.

(19) According to the disclosure, it is possible to efficiently heat the device at the time of DPP annealing and suppress heat generation of the device at the time of driving.

(20) Hereinafter, embodiments of the disclosure will be described with reference to the drawings

(21) As illustrated in FIG. 1, a device 50 before processing is prepared by ion-implanting p-type dopants into an upper surface of a substrate formed of single-crystal silicon in which n-type dopants have been uniformly diffused at a low concentration. The device 50 is formed of an n-type semiconductor portion 1 in which n-type dopants are diffused, a p-type semiconductor portion 2 in which p-type dopants are diffused so that a p-type dopant concentration is higher than an n-type dopant concentration, and a pn junction portion 3 formed at a boundary portion between the n-type semiconductor portion 1 and the p-type semiconductor portion 2.

(22) The n-type semiconductor portion 1 is formed on a lower surface side of the device 50. In the n-type semiconductor portion 1, n-type dopants are evenly diffused in a concentration range of 110.sup.14 particles/cm.sup.3 or more and 110.sup.16 particles/cm.sup.3 or less. The n-type dopants are formed of, for example, at least one of arsenic and antimony.

(23) The p-type semiconductor portion 2 is formed on an upper surface side of the device 50. In the p-type semiconductor portion 2, p-type dopants are diffused so that a peak value of the p-type dopant concentration is in a concentration range of 110.sup.19 particles/cm.sup.3 or more and 110.sup.21 particles/cm.sup.3 or less. Here, the p-type dopants added by ion-implantation have a low fixation rate in the vicinity of a surface of the device 50. Accordingly, in the p-type semiconductor portion 2, a low-concentration portion 2a having a low p-type dopant concentration is formed in the vicinity of an upper surface of the ion-implanted device 50 and a high-concentration portion 2b in which p-type dopants are diffused to have the above-described concentration range at a peak value is formed under the low-concentration portion 2a. The p-type dopant may be, for example, formed of boron.

(24) Next, a method of manufacturing light emitting devices 100, 200, 300, and 400 by processing the above-described device 50 will be described in detail with reference to FIGS. 2 to 5.

First Embodiment

(25) As illustrated in FIG. 2A, a region 50a on a substantially half on the left side of an upper surface of a device 50 is polished and a low-concentration portion 2a of a p-type semiconductor portion 2 is removed, thereby exposing a high-concentration portion 2b.

(26) As illustrated in FIG. 2B, a p-type electrode 4 is formed on the region 50a, and a p-type electrode 5 is formed on a region 50b on a substantially half on the right side of the upper surface of the device 50 not to interfere with the p-type electrode 4. Thereby, independent p-type electrodes 4 and 5 are respectively formed on the high-concentration portion 2b having a high p-type dopant concentration and the low-concentration portion 2a having a low p-type dopant concentration. Further, an n-type electrode 6 is formed on a lower surface of the device 50. Thereby, the n-type electrode 6 is formed on the n-type semiconductor portion 1 having a low n-type dopant concentration.

(27) A voltage is applied between the p-type electrode 5 and the n-type electrode 6 to perform DPP annealing.

(28) As illustrated in FIG. 2C, the n-type electrode 6 is removed, and the n-type semiconductor portion 1 is polished so that a thickness thereof is substantially equal to a thickness of the p-type semiconductor portion 2 under the region 50a.

(29) As illustrated in FIG. 2D, n-type dopants are ion-implanted into the lower surface of the device 50 so that the n-type dopant concentration of the n-type semiconductor portion 1 is in a concentration range of 110.sup.19 particles/cm.sup.3 or more. Thereafter, an n-type electrode 7 is formed on the lower surface of the device 50. Thereby, the n-type electrode 7 is formed on the n-type semiconductor portion 1 having a high n-type dopant concentration. Further, the n-type dopants implanted into the lower surface of the device 50 need not be arsenic or antimony.

(30) The light emitting device 100 is manufactured as described above. Further, at the time of driving the light emitting device 100, a voltage is applied between the p-type electrode 4 and the n-type electrode 7.

Operations and Effects

(31) In the present embodiment, at the time of DPP annealing, a voltage is applied between the p-type electrode 5 formed on the low-concentration portion 2a having a low p-type dopant concentration and the n-type electrode 6 formed on the n-type semiconductor portion 1 having a low n-type dopant concentration. Thereby, the entire device 50 can be efficiently heated from both the upper surface side and the lower surface side. In addition, at the time of driving, a voltage is applied between the p-type electrode 4 formed on the high-concentration portion 2b having a high p-type dopant concentration and the n-type electrode 7 formed on the n-type semiconductor portion 1 in which the n-type dopant concentration is increased. Thereby, heat generation on the upper surface side and the lower surface side can be suppressed, and heat generation of the entire device 50 can be suppressed.

(32) Further, after the DPP annealing, the n-type semiconductor portion 1 is polished to have a thickness that is substantially equal to the thickness of the p-type semiconductor portion 2 under the region 50a. Therefore, since a volume of the device 50 is suppressed to a minimum, heat generation during driving can be suppressed to the utmost.

Second Embodiment

(33) As illustrated in FIG. 3A, p-type dopants are ion-implanted into a region 50a on a substantially half on the left side of an upper surface of a device 50 to form an ion implantation portion 2al in which a p-type dopant concentration on a substantially half on the left side of a low-concentration portion 2a is 110.sup.19 particles/cm.sup.3 or more. Further, the p-type dopants implanted into the region 50a on the substantially half on the left side of the upper surface of the device 50 need not be boron.

(34) As illustrated in FIG. 3B, a p-type electrode 8 is formed on the region 50a, and a p-type electrode 9 is formed on a region 50b on a substantially half on the right side of the upper surface of the device 50 so as not to interfere with the p-type electrode 4. Thereby, the independent p-type electrodes 8 and 9 are respectively formed on the ion implantation portion 2al having a high p-type dopant concentration and the low-concentration portion 2a having a low p-type dopant concentration. Further, an n-type electrode 10 is formed on a lower surface of the device 50. Thereby, the n-type electrode 10 is formed on an n-type semiconductor portion 1 having a low n-type dopant concentration.

(35) A voltage is applied between the p-type electrode 9 and the n-type electrode 10 to perform DPP annealing.

(36) As illustrated in FIG. 3C, the n-type electrode 10 is removed, and the n-type semiconductor portion 1 is polished so that a thickness thereof is substantially equal to a thickness of the p-type semiconductor portion 2.

(37) As illustrated in FIG. 3D, n-type dopants are ion-implanted into the lower surface of the device 50 so that the n-type dopant concentration of the n-type semiconductor portion 1 is in a concentration range of 110.sup.19 particles/cm.sup.3 or more. Thereafter, an n-type electrode 11 is formed on the lower surface of the device 50. Thereby, the n-type electrode 11 is formed on the n-type semiconductor portion 1 having a high n-type dopant concentration. Further, the n-type dopants implanted into the lower surface of the device 50 need not be arsenic or antimony.

(38) The light emitting device 200 is manufactured as described above. Further, at the time of driving the light emitting device 200, a voltage is applied between the p-type electrode 8 and the n-type electrode 11.

Operations and Effects

(39) In the present embodiment, at the time of the DPP annealing, a voltage is applied between the p-type electrode 9 formed on the low-concentration portion 2a having a low p-type dopant concentration and the n-type electrode 10 formed on the n-type semiconductor portion 1 having a low n-type dopant concentration. Thereby, the entire device 50 can be efficiently heated from both the upper surface side and the lower surface side. In addition, at the time of driving, a voltage is applied between the p-type electrode 8 formed on the ion implantation portion 2al having a high p-type dopant concentration and the n-type electrode 11 formed on the n-type semiconductor portion 1 in which the n-type dopant concentration is increased. Thereby, heat generation on the upper surface side and the lower surface side can be suppressed, and heat generation of the entire device 50 can be suppressed.

(40) Further, after the DPP annealing, the n-type semiconductor portion 1 is polished to have a thickness that is substantially equal to the thickness of the p-type semiconductor portion 2 under the region 50a. Therefore, since a volume of the device 50 is suppressed to a minimum, heat generation during driving can be suppressed to the utmost.

Third Embodiment

(41) As illustrated in FIG. 4A, a p-type electrode 12 is formed on an upper surface of a device 50. Thereby, the p-type electrode 12 is formed on a low-concentration portion 2a having a low p-type dopant concentration. Further, an n-type electrode 13 is formed on a lower surface of the device 50. Thereby, the n-type electrode 13 is formed on the n-type semiconductor portion 1 having a low n-type dopant concentration.

(42) A voltage is applied between the p-type electrode 12 and the n-type electrode 13 to perform DPP annealing.

(43) As illustrated in FIG. 4B, the p-type electrode 12 is removed and an upper surface of the device 50 is polished to remove the low-concentration portion 2a of a p-type semiconductor portion 2, thereby exposing a high-concentration portion 2b. Thereafter, as illustrated in FIG. 4C, a p-type electrode 14 is formed on the upper surface of the device 50. Thereby, the p-type electrode 14 is formed on the high-concentration portion 2b having a high p-type dopant concentration.

(44) As illustrated in FIG. 4D, the n-type electrode 13 is removed, and the n-type semiconductor portion 1 is polished so that a thickness thereof is substantially equal to a thickness of the p-type semiconductor portion 2.

(45) As illustrated in FIG. 4E, ion implantation is performed on the lower surface of the device 50 so that the n-type dopant concentration of the n-type semiconductor portion 1 is in a concentration range of 110.sup.19 particles/cm.sup.3 or more. Thereafter, an n-type electrode 15 is formed on the lower surface of the device 50. Thereby, the n-type electrode 15 is formed on the n-type semiconductor portion 1 having a high n-type dopant concentration. Further, the n-type dopants implanted into the lower surface of the device 50 need not be arsenic or antimony.

(46) As described above, the light emitting device 300 is manufactured. Further, at the time of driving the light emitting device 300, a voltage is applied between the p-type electrode 14 and the n-type electrode 15.

Operations and Effects

(47) In the present embodiment, at the time of DPP annealing, a voltage is applied between the p-type electrode 12 formed on the low-concentration portion 2a having a low p-type dopant concentration and the n-type electrode 13 formed on the n-type semiconductor portion 1 having a low n-type dopant concentration. Thereby, the entire device 50 can be efficiently heated from both the upper surface side and the lower surface side. In addition, at the time of driving, a voltage is applied between the p-type electrode 14 formed on the high-concentration portion 2b having a high p-type dopant concentration and the n-type electrode 15 formed on the n-type semiconductor portion 1 in which the n-type dopant concentration is increased. Thereby, heat generation on the upper surface side and the lower surface side can be suppressed, and heat generation of the entire device 50 can be suppressed.

(48) Further, after the DPP annealing, the n-type semiconductor portion 1 is polished to have a thickness that is substantially equal to the thickness of the p-type semiconductor portion 2 under the region 50a. Therefore, since a volume of the device 50 is suppressed to a minimum, heat generation during driving can be suppressed to the utmost.

Fourth Embodiment

(49) As illustrated in FIG. 5A, a p-type electrode 16 is formed on an upper surface of a device 50. Thereby, the p-type electrode 16 is formed on a low-concentration portion 2a having a low p-type dopant concentration. Further, an n-type electrode 17 is formed on a lower surface of the device 50. Thereby, the n-type electrode 17 is formed on the n-type semiconductor portion 1 having a low n-type dopant concentration.

(50) A voltage is applied between the p-type electrode 16 and the n-type electrode 17 to perform DPP annealing.

(51) As illustrated in FIG. 5B, the p-type electrode 16 is removed and p-type dopants are ion-implanted into the upper surface of the device 50 so that the p-type dopant concentration of the low-concentration portion 2a is in a concentration range of 110.sup.19 particles/cm.sup.3 or more. Thereafter, as illustrated in FIG. 5C, a p-type electrode 18 is formed on the upper surface of the device 50. Further, the p-type dopants implanted into the upper surface of the device 50 need not be boron.

(52) As illustrated in FIG. 5D, the n-type electrode 17 is removed, and the n-type semiconductor portion 1 is polished so that a thickness thereof is substantially equal to a thickness of the p-type semiconductor portion 2.

(53) As illustrated in FIG. 5E, ion implantation is performed on the lower surface of the device 50 so that the n-type dopant concentration of the n-type semiconductor portion 1 is in a concentration range of 110.sup.19 particles/cm.sup.3 or more. Thereafter, an n-type electrode 19 is formed on the lower surface of the device 50. Thereby, the n-type electrode 19 is formed on the n-type semiconductor portion 1 having a high n-type dopant concentration. Further, the n-type dopants implanted into the lower surface of the device 50 need not be arsenic or antimony.

(54) As described above, the light emitting device 400 is manufactured. Further, at the time of driving the light emitting device 400, a voltage is applied between the p-type electrode 18 and the n-type electrode 19.

Operations and Effects

(55) In the present embodiment, at the time of DPP annealing, a voltage is applied between the p-type electrode 16 formed on the low-concentration portion 2a having a low p-type dopant concentration and the n-type electrode 17 formed on the n-type semiconductor portion 1 having a low n-type dopant concentration. Thereby, the entire device 50 can be efficiently heated from both an upper surface side and a lower surface side. In addition, at the time of driving, a voltage is applied between the p-type electrode 18 formed on the low-concentration portion 2a in which the p-type dopant concentration is increased and the n-type electrode 19 formed on the n-type semiconductor portion 1 in which the n-type dopant concentration is increased. Thereby, heat generation on the upper surface side and the lower surface side can be suppressed, and heat generation of the entire device 50 can be suppressed.

(56) Further, after the DPP annealing, the n-type semiconductor portion 1 is polished to have a thickness that is substantially equal to the thickness of the p-type semiconductor portion 2 under the region 50a. Therefore, since a volume of the device 50 is suppressed to a minimum, heat generation during driving can be suppressed to the utmost.

(57) The disclosure is not limited to the embodiments and examples described above, and various design modifications are possible within the scope of the described claims.

(58) In the present embodiment, the left half of the upper surface of the device 50 is set as the region 50a, and the right half is set as the region 50b, and the p-type electrodes 4, 5, 8, and 9 are formed, however, the regions 50a and 50b may be set in any way. For example, the regions 50a and 50b may be formed in a comb shape and the p-type electrodes 4, 5, 8, and 9 formed along the regions 50a and 50b may be alternately arranged in a uniaxial direction.

(59) Further, the thickness of the n-type semiconductor portion 1 after polishing may have any value as long as it is within a range in which the pn junction portion 3 can be formed.

(60) Also, after DPP annealing, polishing of the n-type semiconductor portion 1 and increasing of the concentration thereof need not be performed. In this case, heat generation on the p-type semiconductor side at the time of driving can be suppressed.

(61) Further, both the n-type dopants and the p-type dopants may be reversely configured.

(62) It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.