Electrical converter and method for operating an electrical converter

Abstract

A DC-DC converter topology based on electromagnetically coupled class-D LC oscillator is proposed. An electrical converter comprises at least two oscillators (1,2), each of the at least two oscillators being designed to have an oscillating current and an oscillating voltage. Coupling elements (16, 17, 18, 19) arranged to couple the oscillating currents of the at least two oscillators and/or the oscillating voltages of the at least two oscillator. The at least two oscillators are connected in a series connection, adding their oscillating voltages, and/or in a parallel connection, adding their oscillating currents. The topology can be fully integrated, that is, it can be realized as an integrated circuit without external components, in particular without external passive components, such as capacitors and/or inductors.

Claims

1-14. (canceled)

15. An electrical converter, comprising at least two oscillators, each of the at least two oscillators being designed to have an oscillating current and an oscillating voltage; one or more coupling elements arranged to couple at least one of the oscillating currents of the at least two oscillators, and the oscillating voltages of the at least two oscillators; the at least two oscillators being connected in a series connection, adding their oscillating voltages, or in a parallel connection, adding their oscillating currents, or in a combination of series and parallel connections.

16. The electrical converter of claim 15, wherein the at least two oscillators are connected in a series connection, and wherein it either is the case that the converter is controlled to operate with a voltage across one of the at least two oscillators being an input DC voltage to the converter and a voltage across all of the at least two oscillators being a DC output of the converter; or it is the case that the converter is controlled to operate with a voltage across all of the at least two oscillators being an input DC voltage to the converter and a voltage across one of the at least two oscillators being a DC output of the converter.

17. The electrical converter of claim 15, with one of the at least two oscillators, from now on called top oscillator, having an associated top terminal and a bottom terminal, and another one of the at least two oscillators, from now on called bottom oscillator, having an associated top terminal and a bottom terminal, with the top terminal of the bottom oscillator being connected to the bottom terminal of the top oscillator, wherein it either is the case that the converter is controlled to up-convert an input DC voltage, by the top terminal of the bottom oscillator being connected to a terminal for supplying to the converter an input DC voltage relative to the bottom terminal of the bottom oscillator, and the top terminal of the top oscillator being connected to a DC output terminal for an output voltage relative to the bottom terminal of the bottom oscillator; or wherein it is the case that the converter is controlled to down-convert an input DC voltage, by the top terminal of the top oscillator being connected to a terminal for supplying to the converter an input DC voltage relative to the bottom terminal of the bottom oscillator, and the top terminal of the bottom oscillator being connected to a DC output terminal for an output voltage relative to the bottom terminal of the bottom oscillator.

18. The electrical converter of claim 15 wherein the one or more coupling elements comprise inductive coupling elements, coupling oscillating currents of the at least two oscillators, in particular wherein one or more of the inductive coupling elements are transformers.

19. The electrical converter of claim 15, wherein the one or more coupling elements comprise capacitive coupling elements, coupling oscillating voltages of the at least two oscillators, in particular wherein one or more of the capacitive coupling elements are capacitors.

20. The electrical converter of claim 15, wherein the at least two oscillators are self-oscillating oscillators.

21. The electrical converter of claim 15, wherein at least one of the at least two oscillators is not a self-oscillating oscillator.

22. The electrical converter of claim 15, wherein the self-oscillating oscillator or oscillators are LC oscillators.

23. The electrical converter of claim 15, wherein the self-oscillating oscillator or oscillators are one of Class-D LC oscillators, Class-B LC oscillators, Class-C LC oscillators, Class-E LC oscillators, Class-F LC oscillators, Hartley LC oscillators.

24. The electrical converter of claim 15, wherein one or more of the at least two oscillators are configured to be switched on and off, enabling and disabling oscillation of the oscillator, respectively.

25. The electrical converter of claim 24, being controlled to periodically enable and disable oscillation of one or more or all of the at least two oscillators in order to adapt operation of the converter to load changes.

26. The electrical converter of claim 16, wherein one or more of the at least two oscillators are configured to be switched on and off, enabling and disabling oscillation of the oscillator, respectively.

27. The electrical converter of claim 26, being controlled to periodically enable and disable oscillation of one or more or all of the at least two oscillators in order to adapt operation of the converter to load changes.

28. The electrical converter of claim 15, in which at least one, more than one, or all coupling elements are integrally manufactured with switches of the at least two oscillators.

29. The electrical converter of claim 15, configured for an oscillation frequency of the at least one oscillator to be at least 500 MHz, preferably at least 1 GHz.

30. The electrical converter of claim 15, configured for continuous operation transferring power at a maximum rate of least 1 mW, in particular at least 10 mW, in particular at least 1 W.

31. The electrical converter of claim 15, manufactured in a fully integrated fashion and configured to operate at a power density of least 0.1 W/mm.sup.2, in particular at least 0.2 W/mm.sup.2, in particular at least 0.5 W/mm.sup.2, in particular at least 2.5 W/mm.sup.2.

32. The electrical converter of claim 15, wherein the coupling elements are arranged to move charges moved away from parasitic gate capacitances.

33. Method for operating an electrical converter, the electrical converter comprising at least two oscillators, each of the at least two oscillators being designed to have an oscillating current and an oscillating voltage; one or more coupling elements arranged to couple at least one of the oscillating currents of the at least two oscillators, and the oscillating voltages of the at least two oscillators; the at least two oscillators being connected in a series connection, adding their oscillating voltages, or in a parallel connection, adding their oscillating currents, or in a combination of series and parallel connections, the method comprising the steps of periodically enabling and disabling oscillation of one or more or all of the at least two oscillators in order to adapt operation of the converter to load changes.

34. Method for operating an electrical converter, the electrical converter comprising at least two oscillators, each of the at least two oscillators being designed to have an oscillating current and an oscillating voltage; one or more coupling elements arranged to couple at least one of the oscillating currents of the at least two oscillators, and the oscillating voltages of the at least two oscillators; the at least two oscillators being connected in a series connection, adding their oscillating voltages, or in a parallel connection, adding their oscillating currents, or in a combination of series and parallel connections, with one of the at least two oscillators, from now on called top oscillator, having an associated top terminal and a bottom terminal, and another one of the at least two oscillators, from now on called bottom oscillator, having an associated top terminal and a bottom terminal, with the top terminal of the bottom oscillator being connected to the bottom terminal of the top oscillator, the method comprising either the step of operating the converter to up-convert an input DC voltage, by the top terminal of the bottom oscillator being connected to a terminal supplying an input DC voltage relative to the bottom terminal of the bottom oscillator, and the top terminal of the top oscillator being connected to a DC output terminal providing an output voltage relative to the bottom terminal of the bottom oscillator; or the method comprising the step of operating the converter to down-convert an input DC voltage, by the top terminal of the top oscillator being connected to a terminal supplying an input DC voltage relative to the bottom terminal of the bottom oscillator, and the top terminal of the bottom oscillator being connected to a DC output terminal providing an output voltage relative to the bottom terminal of the bottom oscillator.

Description

[0051] The subject matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings, in which:

[0052] FIG. 1 is a schematic of a prior art switched capacitor converter showing the basic structure and parasitic gate and bottom plate capacitances.

[0053] FIG. 2 is a schematic of a prior art resonant-drain recycling switched capacitor circuit showing the basic structure (bottom plate and drain capacitances not shown, for the sake of clarity) and the parasitic gate capacitances.

[0054] FIG. 3 is a schematic of a prior art resonant-gate recycling switched capacitor circuit showing the basic structure and the parasitic bottom plate capacitance with the parasitic gate capacitances not shown, for the sake of clarity.

[0055] FIG. 4 is a schematic of the proposed converter showing the vertical stack of the two electromagnetically coupled class-D LC oscillators including footer transistors.

[0056] FIG. 5 is a schematic of a single class-D LC oscillator.

[0057] FIG. 6 is a schematic of the single class-D LC oscillator with a footer transistor connected on the bottom.

[0058] FIG. 7 depicts exemplary simulation results generated in a SPICE simulation for the converter in FIG. 4 when used as a voltage doubler, focusing on the full load operation.

[0059] FIG. 8 shows the converter configurations when used as a voltage doubler with the footer transistor switched on and switched off.

[0060] FIG. 9 depicts exemplary simulation results generated in a SPICE simulation for the converter in FIG. 4 when used as a voltage doubler, focusing on the duty cycled operation.

[0061] FIG. 10 depicts measurement results of the efficiency at fixed input voltage of the proposed converter when used as a voltage divider for two different transformer, capacitor and transistor sizing, for a high efficiency and a high power density version, respectively.

[0062] FIG. 11 depicts measurement results of the peak efficiency for different input voltages of the proposed converter when used as a voltage divider for two different transformer, capacitor and transistor sizing, for the high efficiency and high power density versions.

[0063] FIG. 12 depicts measurement results of the conversion ratio at fixed input voltage of the proposed converter when used as a voltage divider for two different transformer, capacitor and transistor sizing, for the high efficiency and high power density versions.

[0064] FIG. 13 depicts measurement results of the efficiency at fixed input voltage of the proposed converter when used as a voltage divider in the normal and duty cycled operations, for two different transformer, capacitor and transistor sizing, for the high efficiency and high power density versions.

[0065] FIG. 14 depicts measurement results of the conversion ratio at fixed input voltage of the proposed converter when used as a voltage divider in the normal and duty cycled operations, for two different transformer, capacitor and transistor sizing, for the high efficiency and high power density versions.

[0066] FIG. 15 shows a generalized structure of the converter.

[0067] FIG. 16 shows all the magnetic couplings possible between the four inductors that are part of the two coupled oscillator cells.

[0068] FIG. 17 shows that both horizontal and vertical couplings are possible separately and also implemented both together.

[0069] FIG. 18 shows some configurations in which vertical magnetic and electric coupling are combined.

[0070] FIG. 19 shows some configurations in which horizontal magnetic and electric coupling are combined.

[0071] FIG. 20 shows an M?N array structure with a generic oscillator as a basic cell. In principle, identical or functionally identical parts are provided with the same reference symbols in the figures.

[0072] FIG. 21 shows a single oscillator unit comprising parallel oscillating units.

[0073] FIG. 22 shows a structure of inductors for magnetic coupling between oscillator units.

[0074] FIG. 23 shows one oscillator generating oscillations and driving another one.

[0075] With reference to FIG. 1, a conventional switched capacitor circuit is composed of a left and a right side, each one with four transistors and one flying capacitor. For down-converting operation the input voltage is applied at the VTOP node and the output voltage is generated on the VMID node. For the down-convert operation the input voltage is applied at the VMID node and the output voltage is generated on the VTOP node. The transistors are controlled with phase signals coming from a phase generator. One of the main loss mechanisms of such a topology are switching losses when turning on and off, caused by the parasitic capacitances at the bottom plate of the flying capacitors and at the gate of each transistor

[0076] FIG. 2 shows a resonant-drain recycling circuit topology which partially reuses the energy that the previously mentioned parasitic bottom plate capacitances (for clarity, they are not shown in the figure) would lose. The structure is the same as that of a conventional switched capacitor circuit depicted in FIG. 1, but with an inductor L.sub.RP activated by two switches connected at its left-side and right-side terminals, controlled by a corresponding signal RP. If activated between two switched capacitor states, the inductor transfers the energy stored in one parasitic bottom plate capacitor to the one on the other side, recycling this energy and thereby improving the efficiency. However, the switching losses associated with the gate capacitances are still present.

[0077] FIG. 3 depicts a resonant-gate recycling circuit topology which partially reuses the energy that the previously mentioned parasitic gate capacitances would lose (for clarity, they are not shown in the figure). The structure is the same to that of a conventional switched capacitor circuit depicted in FIG. 1, but with an inductor L.sub.RP activated by four switches connected at each transistor gate terminal, controlled by corresponding signals RP.sub.1 and RP.sub.2. If activated between two switched capacitor states, the inductor transfers the energy stored in one parasitic gate capacitor to the one which will be activated next, recycling this energy contribution improving the efficiency. However, the switching losses associated with the bottom plate capacitances are still present.

[0078] FIG. 4 shows an embodiment of the proposed circuit topology, comprising two vertically stacked class-D LC oscillators, a lower oscillator 1 and an upper oscillator 2 that are electrically and magnetically coupled by means of flying capacitors and transformers respectively.

[0079] The lower oscillator 1 comprises the following elements: a switching unit 12, an oscillator unit 13 and coupling elements 16, 17, 18, 19. The oscillator unit 13 comprises a lower terminal and two upper terminals 14, 15, corresponding to oscillating nodes. The oscillator unit 13 together with the inductors 16 and 17 together with the capacitance between the node 14 and ground as well as the capacitance between the node 15 and ground form the oscillator. The switching unit 12 is arranged to selectively connect or disconnect the lower terminal to a lower oscillator terminal 11. Each of the two upper terminals 14, 15 is connected through an associated inductance 16, 17 to an upper oscillator terminal 20. The upper oscillator 2 with an upper oscillator unit 23 has the same structure as the lower oscillator 1. The lower oscillator terminal of the upper oscillator 2 is connected to the upper oscillator terminal 20 of the lower oscillator 1.

[0080] In the embodiment of FIG. 4, the oscillator unit 13 is a negative gm cell unit.

[0081] The switching unit 12 can comprise a single switching element, also called footer transistor. The inductances of the two oscillators can be transformer windings, thereby coupling the inductances of the lower oscillator 1 with those of the upper oscillator 2, and serving as inductive coupling elements. The oscillating nodes of the upper and lower oscillator can be coupled pairwise by means of capacitors 18, 19, serving as capacitive coupling elements.

[0082] When operating the oscillators 1, 2, the lower oscillator terminal 11 can carry a lower voltage V.sub.BOT, the lower oscillator terminal of the upper oscillator 2 and upper oscillator terminal 20 of the lower oscillator 1 can carry a voltage V.sub.MID, and the upper oscillator terminal of the upper oscillator 2 can carry a voltage V.sub.TOP.

[0083] The following detailed explanation involves the use of specific type of oscillator, but applies to other types as well.

[0084] Cross-coupled pairs of transistors in each of the oscillator units 13, 23 serve as negative gm cells for negative gm-based oscillators to sustain an oscillation when a DC voltage is applied at the common terminal between the two inductors. The footer transistors are controlled by an enable signal that can switch on and off the two oscillators, adapting the delivered power to the one required by the load.

[0085] A first flying capacitor C.sub.fly,AB is connected between the first oscillating node 14 with a voltage VA of the bottom oscillator 1 and the first resonating node with voltage VB of the top oscillator 2. A second flying capacitor C.sub.fly,CD is connected between the second oscillating node 15 with voltage V.sub.C of the bottom oscillator 1 and the second resonating node with voltage V.sub.D of the top oscillator. The flying capacitors C.sub.fly,AB and C.sub.fly,CDintroduce an electric coupling between the bottom and top oscillator, as a consequence the alternating-current (AC) component of the top oscillator voltages V.sub.B and V.sub.D will follow the AC component of the bottom oscillator voltages V.sub.A and V.sub.C.

[0086] The transformer XFMR.sub.AB implements a magnetic coupling between the inductors L1 and L2, and the transformer XFMR.sub.CD between the inductors L3 and L4. The magnetic coupling forces the AC component of the bottom and top oscillator currents to be identical.

[0087] To up-convert an input voltage, the DC source is connected on the top terminal of the bottom oscillator, which will start its operation. The resonating waveforms of the bottom oscillator are coupled to the top oscillator thanks to the electric and magnetic coupling offered by the flying capacitors and transformer respectively, with a DC shift equal to the input voltage. Thus, an output voltage on the top terminal of the top oscillator is generated which will be twice the input DC value.

[0088] To down-convert an input voltage, the DC source is connected on the top terminal of the top oscillator. Both oscillators will start to operate and a DC voltage of half magnitude with respect the input one will be generated on the top terminal of the bottom oscillator.

[0089] When the power required by the load strongly decreases, the converter might operate far from its peak efficiency point. In order to ensure high efficiency operation in light loads, a rectangular waveform is fed to both footer transistor gates defining the on-time of the converter. When the enable signal is at a high value, the converter operates as in full load and power is delivered to the load. When the enable signal is low, the oscillators are both switched off and no power is delivered to the load. Operation with efficiency close to the peak value is ensured it the duty cycle of the rectangular wave is tuned in a way to ensure the correct amount of power to the load.

[0090] By using the gate and drain parasitic capacitances of the transistors in the negative gm cells and the bottom plate parasitic capacitance of the flying capacitor as resonance element, together with one of the inductors of one of the transformers, the charge stored in the LC series resonant circuit is not discharged to ground as in the prior art, but is stored in the oscillator and then delivered to the output.

[0091] The value of inductances in the coupled oscillators can be different from one another, for generating different voltages across each oscillator. The capability of generating different voltages translates into different DC-DC converter voltage conversion ratios, expressed as VCR=VOUT/VIN, which makes the proposed topology more flexible to a wide variety of applications where there are specific demands on the voltage conversion ratio. So, in the context of FIG. 4 this can mean that L1 and L3 have a certain value and L2 and L4 have another value, different from that of L1 and L3.

[0092] FIG. 5 shows the schematic of the single class-D LC oscillator, where the DC input voltage is connected at the V.sub.TOP terminal, the DC ground at the V.sub.BOT terminal and the two oscillating nodes are VC.sub.1 and VC.sub.2.

[0093] Where L.sub.1 and L.sub.2 are the two inductors and C.sub.res1 and C.sub.res2 are composed of the drain and gate parasitic capacitances of the transistors. When a DC voltage is applied on the V.sub.TOP terminal the oscillator starts its operation and two resonating voltages are generated on the nodes VC.sub.1 and VC.sub.2.

[0094] FIG. 6 shows the schematic of the single class-D LC oscillator with the footer transistor connected between the two transistor source terminals and the V.sub.BOT terminal. The footer transistor can stop the current flowing in the oscillator from the DC input connected at the V.sub.TOP terminal, stopping the oscillation as well. Therefore, the voltages VC.sub.1 and VC.sub.2 will not be resonating anymore and no current will be taken from the DC source. The oscillator will be totally shut down, consuming no power.

[0095] FIG. 7 shows the result of the simulations in SPICE of the circuit depicted in FIG. 4 when operating as an up-converter. Thus, a DC input voltage is connected on the VMID terminal and the output voltage is generated on the VTOP terminal. The footer transistor is fed with a constant DC voltage and behave as a constantly-on ideal switch. The converter operates in two main phases ?1 and ?2, further divided in two sub-phases each, ?1A and ?113, ?2A and ?2B. The first graph on the top shows the resonating voltages. If operated as an up-converter connecting the DC source on the VMID terminal an taking the output voltage from the VTOP terminal, the electromagnetic coupling between the two stacked oscillators make the top one work reversely to the bottom one. Thus, the top oscillator voltages VB and VD will follow the bottom oscillator VA and VC, with a DC shift equal to the input voltage VIN. The output voltage VOUT will be generated on the VTOP terminal, and it will be equal to twice the input voltage if no load is applied. If a load is connected on the VTOP terminal the output voltage will be:

VOUT=2*VIN?ROUT*IOUT

[0096] Where Vin is the input voltage applied on the VTOP terminal, ROUT is the output resistance of the converter and IOUT is the output current of the converter leaving the VTOP terminal.

[0097] The second graph in FIG. 7 shows the inductor currents continuously oscillating throughout both phases, and the output current will be the sum of the inductor currents IL2 and IL4. The AC components of the top oscillator currents IL2 and IL4 follows the AC component of the bottom oscillator currents IL1 and IL3. The DC components of those currents goes farther from zero the higher the current required by the load.

[0098] The third graph in FIG. 7 depicts the flying capacitor voltages V.sub.CFLY,AB and V.sub.CFLY,CD, which show a standard charge and discharge capacitor behaviour. During phase ?1, the flying capacitor C.sub.FLY,AB is connected between VMID and VTOP, meaning that it is discharging to the load and its current is linearly decreasing. The same is for C.sub.FLY,CD during phase ?2. During phase ?1, the flying capacitor C.sub.FLY,CD is connected between VMID and VBOT, meaning that it is charging from the DC input voltage source and its current is increasing. The same is for C.sub.FLY,AB during phase ?2.

[0099] FIG. 8 shows the circuit schematic when the footer enable signal is high, with logic value 1, and when it is low, with logic value 0. Each of the two vertically stacked oscillators, an example of whose single cell schematic is depicted in FIG. 5, is simply represented with the standard symbol of an oscillator. The footer transistor is simplified as an on/off ideal switch. When the footer enable signal is high, the converter operates as in full load, thus both oscillators are resonating, and power is delivered to the load.

[0100] During this time, called on-time of the converter, the output voltage increases. When the footer enable signal is low, both oscillators are switched off and no power is delivered to the load. During this time, called off-time of the converter, the output capacitor provides current to the resistive load and the output voltage decreases.

[0101] FIG. 9 shows the simulation of the converter depicted in FIG. 4 when the footer transistor is fed with a rectangular wave, named as EN and shows at the bottom of FIG. 9. The resonating voltages are oscillating during the on-time, providing power to the load and the output voltage VOUT is increasing. No power is delivered to the output during the off-time and the output voltage VOUT is decreasing. During this time, the output capacitor is providing power to the output resistive load, limiting the output voltage decrease.

[0102] A magnified drawing of the resonating voltages VA, VB, VC and VD is displayed on the top of FIG. 9. The one on the top-left shows the startup of the oscillators, in which the converter is transitioning from the OFF to the ON phase. The one in the middle shows the operation during the on-time, similar to that in full load where all the resonating voltages are oscillating. The one on the top-right shows the turn-off of the oscillators, where the resonating voltage amplitudes is decreasing approaching zero.

[0103] FIG. 10 shows the efficiency measurements result of the proposed converter when operated in down-conversion with a 2.8V input voltage and zero output capacitance. Two versions of the proposed converter have been measured, presenting different transformers, flying capacitors and transistors sizing, originating the High Efficiency and the High Power Density versions. The high efficiency version achieves a peak efficiency equal to 67% at a power density of 0.21 W/mm{circumflex over ()}2 resonating at 1.25 GHz. The high power density version achieves a peak efficiency equal to 58.1% at a power density of 0.88 W/mm{circumflex over ()}2 resonating at 2.5 GHz. The measurement result shows the tradeoff between higher efficiency of the high efficiency version implemented with larger transformers and flying capacitances, and higher power density of the high power density version implemented with smaller transformers and flying capacitors.

[0104] FIG. 11 shows the efficiency measurements result of the proposed converter when operated in down-conversion with input voltage ranging from 1V and 3.6V for the high efficiency version and 1V and 3V for the high power density version, and zero output capacitance. The measurement results show the wide range of input voltages that the proposed converter could operate with.

[0105] FIG. 12 shows the voltage conversion ratio measurements result of the proposed converter when operated in down-conversion with a 2.8V input voltage and zero output capacitance. The voltage conversion ratio (VCR) is defined as:

VCR=VOUT/VIN

[0106] The measurement results show the output voltage characteristics of the proposed converter over a varying load resistance when operating in full load without the use of the footer to regulate the output voltage.

[0107] FIG. 13 shows the efficiency measurements result of the proposed converter when operated in down-conversion with a 2.8V input voltage, comparing the full load operation with the duty cycled operation. The dark curve shows the full load operation, where the footer transistor is controlled with a constant DC voltage and acts as an always-on switch with low on-resistance. The grey curve shows the operation when the footer transistor is controlled with a square wave which duty cycles the converter. The measurement results show that the duty cycling scheme successfully improves the converter efficiency which remains close to the peak from 70 uW up to 0.5 W of output power.

[0108] FIG. 14 shows the voltage conversion ratio measurements result of the proposed converter when operated in down-conversion with a 2.8V input voltage, comparing the full load operation with the duty cycled operation. The dark curve shows the full load operation, where the footer transistor is controlled with a constant DC voltage and acts as a always-on switch with low on-resistance. The grey curve shows the operation when the footer transistor is controlled with a square wave which duty cycles the converter. The measurement results shows that the duty cycling scheme successfully regulates the output voltage to the desired value providing optimal efficiency.

[0109] FIG. 15 shows a generalized basic structure of a series or vertical arrangement of two oscillators, where at least two oscillators are electrically and/or magnetically coupled by means of capacitors and/or inductors respectively. Elements presented in the context of the more detailed structure of FIG. 4 are designated with the same reference numbers.

[0110] The at least two oscillators generally are of the same type. They can be of one or more of the following types: Class-D LC oscillator (as in the preceding figures), Class-B LC oscillator, Class-C LC oscillator, Class-E LC oscillator, Class-F LC oscillator, Hartley LC oscillator, Cross-Coupled oscillator, Ring oscillator, Delay-line oscillator, Wien Bridge oscillator, RC Phase Shift oscillator, Hartley oscillator, Voltage Controlled oscillator, Colpitts oscillator, Clapp oscillator, Crystal oscillator, Armstrong oscillator, Meissner oscillator, Tuned Collector oscillator, Pierce oscillator, Robinson oscillator, Royer oscillator, Tuned Collector oscillator, Pierce oscillator, Robinson oscillator, Royer oscillator.

[0111] Some of the oscillators listed above have only one oscillating terminal, and the flying capacitors are organized accordingly: for instance, if only one node is available, according to one embodiment, only one flying capacitor is be used. According to other embodiments, the oscillator output is converted from being single-ended to double-ended, replacing one output terminal by two output terminals, and the coupling elements are connected to these two output terminals.

[0112] FIG. 16 shows all the magnetic coupling possible between the four inductors that are part of the two coupled oscillator cells. All the magnetic coupling coefficients below can be positive or negative. It also shows the two ways in which horizontal coupling could be arranged vertically. For more than two oscillator cells, the coupling can be extended accordingly.

[0113] FIG. 17 shows that both horizontal and vertical couplings are possible separately and also implemented both together.

[0114] FIG. 18 shows some configurations in which vertical magnetic and electric coupling are combined. This does not show all the possible combinations but some important ones. All the coupling coefficients shown in FIG. 16 can be added and combined to for all the possible ways in which the coupling magnetic and electric coupling could involve all the capacitors and inductors in the structure.

[0115] FIG. 19 shows some configurations in which horizontal magnetic and electric coupling are combined. This does not show all the possible combinations but some important ones. All the coupling coefficients shown in FIG. 16 can be added and combined to for all the possible ways in which the coupling magnetic and electric coupling could involve all the capacitors and inductors in the structure. Each of the configurations shown in FIG. 19 can correspond to the internal structure of the oscillators shown in FIG. 15. For example, if one of the configurations implements the bottom oscillator 1 of FIG. 15, the VMID terminal could be the input or output and the VBOT terminal would be the reference. If it implements the top oscillator 2 of FIG. 15, the VMID terminal could be the input or output and the VBOT terminal would be output or input, respectively.

[0116] FIG. 20 shows an M?N array structure with a generic oscillator as basic cell. Each oscillator can be coupled with any of the other oscillators in the array by means of capacitors and/or inductors. The coupling could be vertical and/or horizontal, where any of the single cell oscillating node could be electrically coupled any of the oscillating nodes of the other cell using capacitors, and/or one of the inductors of the single cell could be magnetically coupled with any of the inductors in the other cell.

[0117] The value of a single inductance in any of the coupled oscillators can be different from each other, for generating different voltages across each oscillator. The capability of generating different voltages translates into different DC-DC converter voltage conversion ratios, expressed as VCR=VOUT/VIN, which will make the proposed topology more flexible to a wide variety of applications where there are specific demands on the voltage conversion ratio required.

[0118] FIG. 21 shows, referring to the array presented in FIG. 20, how each single oscillator unit can comprise one or more parallel oscillating units. FIG. 21 shows the example for a minimum size array of 2 rows and 1 column, where the bottom unit comprises M parallel oscillators and the top unit by N parallel oscillators, where M and N can be any integer number. The capability of designing a single unit as combination of multiple parallel units results in different voltages generated across each oscillator, providing more flexibility to design the proposed converter featuring several voltage conversion ratios to fit a wide variety of applications.

[0119] FIG. 22 shows, referring to the array presented in FIG. 20, and for the case of a 4?1 array with 4 rows and 1 column, a structure of inductors. This structure can be beneficial to maximize the magnetic coupling between the single oscillator units of the array, namely k12, k13, k14, k23, k24, k34 in the example, to maximize the converter efficiency. Therefore, if one of the inductors belonging to a single oscillator unit (L1-L4 in the 4 depicted oscillators) needs to be coupled with any of the inductors in the other units (L1-L4), in the example of building them with an 8-shaped structure, they can be arranged as depicted in FIG. 22. Therein, each inductor comprises two loops arranged in an 8-shape in a planar configuration. One loop of each inductor is arranged to be magnetically coupled with one loop of a corresponding adjacent inductor. Each inductor is coupled, by its two loops, to two respective adjacent inductors. The inductors are in a sequence, with a loop of a first inductor of the sequence being coupled to a loop of a last inductor of the sequence, thereby forming a circular arrangement. The arrangement provides a high coupling between all the inductors.

[0120] The inductance value of an inductor can be between 10 pH and 100 nH, in particular between 100 pH and 50 nH, in particular between 500 pH and 20 nH.

[0121] The loops can be coupled by adjacent placing, involving either interleaving, stacking or both, of the involved inductors. Interleaving means that conductors of the loop lie mostly in the same plane, crossing one another at, for example, two locations. Stacking means that the conductors of the loop are at least approximately congruent and lie in parallel planes. In each case (interleaving or stacking) and also for other arrangements of coupled inductors in a fully integrated converter, manufactured as an integrated circuit, the conductors can be realized as conducting layers within the integrated circuit. In each case (interleaving or stacking), and also for other arrangements of coupled inductors, the conductors can be realized as conducting layers on a printed circuit board (PCB).

[0122] FIG. 23 shows an embodiment in which only one oscillator is to be cross-connected and is responsible to generate and maintain the oscillations. Thereby, the other electrically, magnetically or electromagnetically coupled oscillators can avoid the cross-connection and are simply coupled through the gate of the transistors with an appropriate coupling capacitance. This will offer more design flexibility of the voltages provided to the other electrically, magnetically or electromagnetically coupled oscillators transistor gates through the sizing of the additional coupling capacitors CC1 and CC2. This can reduce or minimize the transistor resistive losses and respect their device maximum ratings. The structure of FIG. 23 shows such a structure, based on the example of the class-D oscillator but which could also be any other type as explained above in relation to FIG. 15.

[0123] Application fields for the converter presented herein are, for example: Power management and energy harvesting circuits (for DC/DC, AC/DC, DC/AC and AC/AC-converter), Low-dropout regulators, Voltage Regulators, Power Amplifiers, LED drivers, Flash drivers, Charge-pump circuits, Mm-Wave Wireless communication circuits, Radars, Image sensors, Time-of-flight sensors, Circuits for machine learning and artificial intelligence, Analog-to-digital converters, Transceivers, Optical communication circuits, Memories, Frequency synthesizers, Phase locked loop, Delay locked loop, Voltage controlled oscillators, CRYO-CMOS for quantum technologies, Circuits for internet of things, Biomedical circuits, Processors, Clock circuits, Circuits for security, Circuits for RF and emerging THz techniques.