OPTOELECTRONIC SEMICONDUCTOR CHIP, MANUFACTURING METHOD AND SEMICONDUCTOR COMPONENT

Abstract

In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence with a bottom side, a bottom coating located on the bottom side and an electrode layer located on an underside of the bottom coating facing away from the semiconductor layer sequence, wherein the bottom coating has a thickness gradient and at least one ridge line at which the bottom coating is thickest, wherein the electrode layer extends over the at least one ridge line such that a contact side of the electrode layer facing away from the semiconductor layer sequence follows the bottom coating true to shape, and wherein an electrical and mechanical contact plane of the contact side parallel to the bottom side is defined by the at least one ridge line.

Claims

1.-16. (canceled)

17. An optoelectronic semiconductor chip comprising: a semiconductor layer sequence with a bottom side; a bottom coating located on the bottom side; and an electrode layer located on an underside of the bottom coating facing away from the semiconductor layer sequence, wherein the bottom coating has a thickness gradient and at least one ridge line at which the bottom coating is thickest, wherein the electrode layer extends over the at least one ridge line such that a contact side of the electrode layer facing away from the semiconductor layer sequence follows the bottom coating true to shape, and wherein an electrical and mechanical contact plane of the contact side parallel to the bottom side is defined by the at least one ridge line.

18. The optoelectronic semiconductor chip according to claim 17, wherein the bottom coating comprises exactly one ridge line, and wherein the ridge line is a closed line.

19. The optoelectronic semiconductor chip according to claim 18, wherein the electrode layer comprises a constant thickness at least within the ridge line.

20. The optoelectronic semiconductor chip according to claim 17, wherein the ridge line or at least one of the ridge lines is a circle, as seen in plan view of the bottom side.

21. The optoelectronic semiconductor chip according to claim 17, wherein the bottom coating comprises a base body directly located on the bottom side and a step layer on a valley side of the base body facing away from the semiconductor layer sequence, wherein the valley side is free of the step layer in a central region, and wherein the step layer runs around the central region.

22. The optoelectronic semiconductor chip according to claim 21, wherein the ridge line or at least one of the ridge lines limits the central region, and wherein a corresponding at least one ridge line protrudes the central region in a direction away from the semiconductor layer sequence.

23. The optoelectronic semiconductor chip according to claim 21, wherein the base body is of an electrically conductive material and the step layer is of a dielectric material.

24. The optoelectronic semiconductor chip according to claim 21, wherein the step layer comprises a uniform, constant layer thickness in regions where it is present, and wherein the layer thickness of the step layer is between 20 nm and 0.5 ?m, inclusively.

25. The optoelectronic semiconductor chip according to claim 21, wherein the base body is convexly curved throughout such that the base body comprises a collective lens shape when viewed in cross-section.

26. The optoelectronic semiconductor chip according to claim 17, wherein the bottom coating, when viewed in cross section, is curved only in an edge region and is otherwise oriented parallel to the bottom side.

27. The optoelectronic semiconductor chip according to claim 17, wherein the electrode layer completely covers the bottom coating.

28. The optoelectronic semiconductor chip according to claim 17, wherein the bottom coating comprises a maximum thickness between 50 nm and 0.5 ?m, inclusively, and wherein the semiconductor chip is a ?LED such that an edge length of the bottom side, when seen in plan view, is between 1 ?m and 30 ?m, inclusively.

29. The optoelectronic semiconductor chip according to claim 17, wherein the bottom coating comprises a decreasing thickness starting from the at least one ridge line towards edges of the bottom side.

30. A method for manufacturing the optoelectronic semiconductor chip according to claim 17, the method comprising: providing the semiconductor layer sequence; applying the bottom coating to the bottom side; forming the at least one ridge line; and providing the electrode layer by overmolding the bottom coating true to shape with a material of the electrode layer.

31. A semiconductor component comprising: a plurality of optoelectronic semiconductor chips according to claim 17; a carrier; and connectors, wherein the optoelectronic semiconductor chips are fixed to a carrier mounting side of the carrier by the connectors, wherein the bottom sides are oriented parallel to the carrier mounting side, and wherein the electrode layers are pressed in a region of the ridge lines by the connectors until the carrier mounting side such that the bottom sides are oriented parallel to one another by the ridge lines.

32. The semiconductor component according to claim 31, wherein the semiconductor component is a red-green-blue display.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings show:

[0050] FIGS. 1 to 4 schematic sectional views of process steps of an embodiment of a manufacturing process for optoelectronic semiconductor chips described herein;

[0051] FIGS. 5 to 8 schematic sectional views of process steps of an embodiment of a manufacturing process for optoelectronic semiconductor chips described herein;

[0052] FIG. 9 a schematic sectional view of a region around a ridge line of an embodiment of an optoelectronic semiconductor chip described herein;

[0053] FIGS. 10 to 13 schematic top views of embodiments of semiconductor optoelectronic chips described herein;

[0054] FIGS. 14 to 17 schematic sectional views of embodiments of semiconductor optoelectronic chips described herein; and

[0055] FIG. 18 a schematic sectional view of an embodiment of a semiconductor component with optoelectronic semiconductor chips described herein.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0056] FIGS. 1 to 4 show an embodiment of a manufacturing method for optoelectronic semiconductor chips 1. According to FIG. 1, a semiconductor layer sequence 2 is provided. The semiconductor layer sequence 2 is based, for example, on the material system AlInGaN. The semiconductor layer sequence 2 is preferably already separated from a wafer, but can alternatively still be a part of a wafer, so that a separation can take place only in a subsequent, not shown process step, for example only after the step of FIG. 4.

[0057] It is also illustrated in FIG. 1 that a base body 31 of a bottom coating 3 is applied to a bottom side 20 of the semiconductor layer sequence 2. The bottom side 20 is opposite an emission side 25 of the semiconductor layer sequence 2. The bottom side 22 is flat, for example. The base body 31 does not extend to edges 22 of the bottom side 22. Further, the base body 31 is lens-shaped, for example spherical segment-shaped. A maximum thickness of the base body 31 is, for example, between 0.1 ?m and 0.3 ?m inclusive. A valley side 34 of the base body 31 facing away from the semiconductor layer sequence 2 can thus be continuously curved.

[0058] The shape of the base body 31 can be adjusted, for example, with a mask layer 5 which overhangs towards the base body 31 and which has a greater thickness than the base body 31. The curved shape of the valley side 34 results, in particular, from shading effects on the mask layer 5 when a material of the base body 31 is applied. The base body 31 is, for example, made of Ag, Al or Au which is vapor-deposited.

[0059] According to FIG. 2, a base layer 32 for a step layer 32 is applied to the base body 31. The starting layer 32 is preferably applied true to shape to the valley side 34 of the base body 31 so that the starting layer 32 has the same cross-sectional shape as the base body 31, merely enlarged and/or displaced. The same masking layer 5 can be used to produce the starting layer 32 as for the base body 31.

[0060] The starting layer 32 is preferably thin, for example with a thickness of at least 20 nm and/or of at most 100 nm. For example, the starting layer 32 is made of a dielectric material such as silicon dioxide and/or aluminum oxide.

[0061] In FIGS. 1 and 2, the starting layer 32 and the base body 31 are each formed by only a single material. Starting layers 32 and base bodies 31 composed of several sublayers and/or materials are also possible, as in all other embodiment examples.

[0062] According to FIG. 3, the starting layer 32 is patterned to form a step layer 32, for example with the aid of a further mask layer, not shown. This exposes the valley side 34 in a central region C. In a circumferential edge region E, the step layer 32 remains and completely covers the base body 31 there. A bottom coating 3 is thus composed of the step layer 32 and the base body 31.

[0063] Removal of the step layer 32 from the central region C results in a thickest portion of the bottom coating 3 along an edge of the exposed central region C. This thickest portion forms a ridge line 33. The step layer 32 ends toward the central region 33 at or near the ridge line 33.

[0064] According to FIG. 4, an electrode layer 4 is applied to the bottom coating 2. The electrode layer 4 is preferably a metallic layer, for example of Ag, Al and/or Au. A thickness of the electrode layer 4 is, for example, at least 30 nm or at least 50 nm and/or at most 0.25 ?m or at most 120 nm.

[0065] The electrode layer 4 overmolds the bottom coating 2 true to shape, so that a contact side 40 of the electrode layer 4 facing away from the semiconductor layer sequence 2 has the same shape or basic shape as the bottom side 30 of the bottom coating 3. In this case, the electrode layer 4 is preferably a continuous, uninterrupted layer that overmolds the ridge line 33 without tearing.

[0066] At least within the ridge line 33, the electrode layer 4 has a constant layer thickness, for example, whereby the electrode layer 4 can extend with constant thickness over the ridge line 33. It is possible that the electrode layer 4 becomes thinner towards outer edges of the bottom coating 3 and thus tapers off.

[0067] The resulting optoelectronic semiconductor chip 1 is in particular a PLED. That is, the semiconductor chip 1 is arranged to generate light and the bottom side 20 has an edge length or an average edge length between 1 ?m and 30 ?m inclusive. A thickness of the semiconductor layer sequence 2 perpendicular to the bottom side 20 is, for example, between 0.5 ?m and 5 ?m inclusive, in particular between 1.0 ?m and 2.5 ?m inclusive.

[0068] FIGS. 5 to 8 illustrate a further embodiment of the manufacturing process. The steps of FIGS. 5 to 8 are carried out as explained in connection with FIGS. 1 to 4.

[0069] Unlike FIGS. 1 to 4, however, the base body 31 is significantly wider in the direction parallel to the bottom side 20. Thus, the valley side 34 in the central region C is flat and is oriented parallel to the bottom side 20; this applies, for example, to at least 70% or to at least 85% of an area of the central region C. In the edge region E, on the other hand, the valley side 34 is curved, as is the bottom side 30.

[0070] As in FIG. 4, according to FIG. 8 the entire valley side 34 in the central region C is preferably closer to the bottom side 20 than the ridge line 33.

[0071] In all other respects, the comments on FIGS. 1 to 4 apply in the same way to FIGS. 5 to 8, and vice versa.

[0072] FIG. 9 shows a detailed view of the area around the ridge line 33, such as illustrated in FIG. 4 or 8. In the region of the crest line 33, the contact side 40 preferably has a bend or a rounding with a relatively small radius. Thus, the contact side 40 at the ridge line 33 may be wedge-shaped, as seen in cross-section. In the direction away from the central region C, the contact side 40 preferably has an angle A to a contact plane P. The contact plane P is defined by the ridge line 33 and runs through points of the contact side 40 furthest away from the semiconductor layer sequence 2.

[0073] The contact plane P is oriented parallel to the bottom side 20, for example with a tolerance of at most 1.5? or of at most 0.5? or of at most 0.2?. The angle A is preferably more than 0?, for example at least 0.3? or at least 1.2? and/or at most 6? or at most 4?. This preferably also applies to all other embodiments.

[0074] Optionally, the step layer 32 has a front side 35 which runs at an angle to the valley side 35, for example with an angle B of at least 45? and/or of at most 80?, in particular between 50? and 70? inclusive. That is, the front side 35 is then not oriented perpendicular to the valley side 34. This facilitates over-shaping of the ridge line 33 and the front side 35 by the electrode layer 4, since excessive slopes of the underside 30 can be avoided.

[0075] In all other respects, the comments on FIGS. 1 to 8 apply in the same way to FIG. 9, and vice versa.

[0076] In FIGS. 10 to 13, various top views of the bottom sides 20 of semiconductor chips 1 are shown. These semiconductor chips 1 are manufactured in particular by the processes of FIGS. 1 to 4 or 5 to 8.

[0077] According to FIG. 10, the exact one ridge line 33 is formed by a closed line, in particular a closed circular line. Thus the central region C is a circular area. A diameter of the central region C is, for example, at least 30% and/or at most 70% of a shortest edge length L of the bottom side 20. Thus a stable support surface for the semiconductor chip 1 can be achieved by the ridge line 33.

[0078] The bottom coating 3 can also be circular in shape. A difference in the diameters of the central region C and the edge region E is, for example, at least 5% or at least 10% and/or at most 20% or at most 10% of the shortest edge length L.

[0079] Furthermore, it is illustrated in FIG. 10 that the entire bottom side 20 may be covered by the electrode layer 4. That is, the electrode layer 4 may extend to the edge 22 of the bottom side 20. Alternatively, the electrode layer 4 ends at a distance from the edge 22.

[0080] In all other respects, the comments on FIGS. 1 to 9 apply in the same way to FIG. 10, and vice versa.

[0081] In the example shown in FIG. 11, the ridge line 33 is designed as a closed are triangle, with individual circular arcs meeting at contact points U and being convex in shape. This design of the ridge line makes it possible to have exactly three contact points U, so that the contact plane P can be clearly defined. The bottom coating 3 is again circular and/or spherical segment-shaped, for example.

[0082] Deviating from FIG. 11, not only triangles or are triangles, but also polygons or are polygons can be used. For example, in a hexagon or floor hexagon, six of the contact points U may be present, not drawn.

[0083] In all other respects, the comments on FIG. 10 apply in the same way to FIG. 11.

[0084] FIG. 12 illustrates that there are two ridge lines 33, which are separated from each other by an intermediate region D and which are circled by the common edge region E. The ridge lines 33 may be concentric. The ridge lines 33 can be arranged concentrically. In the intermediate region D, the contact side 40 is closer to the bottom side 20 than in the ridge lines 33.

[0085] Deviating from the illustration in FIG. 12, it is also possible that differently shaped ridge lines are combined with each other, for example a circular ridge line with a hexagonal or are hexagonal ridge line.

[0086] In all other respects, the comments on FIGS. 10 and 11 apply in the same way to FIG. 12.

[0087] In the embodiment example of FIG. 13, there are also several ridge lines 33. In this case, the ridge lines 33 are straight sections that run parallel to one another, for example. Each of the ridge lines 33 can be assigned its own bottom coating 3. The bottom coatings 3 are configured, for example, in a semicircular shape. In this configuration, the bottom coatings 3 may increase towards the edges 22 associated with the respective ridge lines 33, i.e. have a thickness increasing towards the respective edge 22.

[0088] In all other respects, the comments on FIGS. 10 to 12 apply in the same way to FIG. 13.

[0089] The top views of FIGS. 10 to 13 can be used for all the sectional views shown.

[0090] In the embodiment shown in FIG. 14, the bottom coating 3 is in one piece and circular in shape. The central region C is free of the bottom coating 3, i.e. in the central region C the electrode layer 4 extends directly to the bottom side 20.

[0091] In all other respects, the comments on FIGS. 1 to 13 apply in the same way to FIG. 14, and vice versa.

[0092] According to FIG. 15, the bottom coating 3 is triangular in shape when viewed in cross-section. This means that, at least in the edge region E, the underside 30 can be in the form of straight sections.

[0093] Optionally, the electrode layer 4 is flattened in the region of the ridge line 33. Such a flattened region of the contact side 40 may also be present in all other embodiments. For example, the flattened region, as seen in cross-section through a center of the bottom side 20, has a width of at least 1% or of at most 5% of the minimum edge length L.

[0094] In all other respects, the comments on FIG. 14 apply in the same way to FIG. 15.

[0095] Based on FIGS. 14 and 15, it is possible that the bottom coating 3 also has a multilayer structure, but that the base body already defines the ridge line by structuring, which then extends through the following, optional layers of the bottom coating 3 to the contact side 40.

[0096] In FIG. 16, it is shown that the step layer 32 of the bottom coating 3 may extend beyond the edge 22 to the side surfaces of the semiconductor layer sequence 2. In this case, the step layer 32 can serve as a passivation of the semiconductor layer sequence 2.

[0097] In contrast, the step layer 32 in FIG. 17 already ends at a distance from the edge 22. The step layer 32 and the electrode layer 4 can end equidistant from the edge 22, so that the bottom coating 3 and the electrode layer 4 can be congruent with each other.

[0098] In all other respects, the comments on FIGS. 1 to 15 apply in the same way to FIGS. 16 and 17, and vice versa.

[0099] In FIG. 18, an embodiment of a semiconductor component 8 is shown. The semiconductor component 8 comprises a plurality of the semiconductor chips 1 as described in connection with FIGS. 1 to 17.

[0100] The semiconductor chips 1 are mounted on a common carrier 81, the carrier 81 having a planar carrier mounting side 80 for this purpose. Conductor tracks and electrical connection areas can be located on the carrier mounting side 80, not shown.

[0101] The semiconductor chips 1 are attached to the carrier mounting side 80 by means of a mechanical connecting means 82. The connecting means 82 is, for example, an electrically non-conductive adhesive such as a photoresist. The semiconductor chips 1 are mounted, for example, by pressing them onto the carrier 81 through the connecting means 82. This is facilitated by the relatively sharp edges of the contact sides 40 in the region of the ridge lines 33. In addition, defined contact surfaces are ensured by the ridge lines 33.

[0102] By shrinking the connecting means 82 during a curing process, it is additionally possible for the semiconductor chips 1 to be attracted to the carrier 81. The ridge lines 33 ensure that an alignment of the semiconductor chips 1 with defined emission directions is maintained even in the case of such shrinkage or shrinkage.

[0103] For example, red-green-blue pixels, also known as RGB pixels, are formed by the semiconductor chips 1. That is, red, green and blue emitting semiconductor chips 1 can be combined with each other. The corresponding emission color comes about, for example, directly by the respective semiconductor layer sequence 2 or by means of a phosphor, not shown.

[0104] Optionally, a filler material 83 is located between adjacent semiconductor chips 2. The filler material 83 is, for example, white to ensure high radiation efficiency or black to achieve high contrast. Further cover layers can be applied to all semiconductor chips 1 and to the optional filler material 83, not drawn, for example to protect the semiconductor chips 1 mechanically, electrically and/or chemically.

[0105] The semiconductor chips 1 are, for example, chips to be contacted on both sides. That is, the emission sides 25 can be electrically connected by means of electrical connection means 85, such as bonding wires. Alternatively, the semiconductor chips 1 may be designed as flip chips. The same applies to all other embodiments.

[0106] The components shown in the figures preferably follow one another in the sequence indicated, in particular directly one after the other, unless otherwise described. Components not touching each other in the figures are preferably spaced apart. Insofar as lines are drawn parallel to one another, the associated surfaces are preferably likewise aligned parallel to one another. Furthermore, the relative positions of the drawn components to each other are correctly reproduced in the figures, unless otherwise specified.

[0107] The invention described herein is not limited by the description based on the embodiments. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or embodiments.