RF AMPLIFIER OF ACCURATE BIAS AND HEALTHY HEADROOM AND METHOD THEREOF
20240171142 ยท 2024-05-23
Inventors
Cpc classification
International classification
Abstract
A method operates to bias an RF receiver by incorporating a first NMOSFET as a common-source amplifier; incorporating a second NMOSFET as a cascode device stacked upon the first NMOSFET, injecting a reference current into a drain of a third NMOSFET; using a first operational amplifier to generate a first bias voltage to control a gate of the first NMOSFET, a gate of the third NMOSFET, and a gate of a fourth NMOSFET in accordance with a voltage difference between the drain of the third NMOSFET and a drain of the fourth NMOSFET; incorporating a fifth NMOSFET stacked upon the fourth NMOSFET; and using a second operational amplifier to generate a second bias voltage to control a gate of the second NMOSFET and a gate of the fifth NMOSFET in accordance with a voltage difference between a reference voltage and the drain of the fourth NMOSFET.
Claims
1. A RF amplifier comprising: a cascode amplifier comprising a stack up of a first NMOSFET (n-channel metal oxide semiconductor field effect transistor) biased by a first bias voltage and a second NMOSFET biased by a second bias voltage; a load network comprising a load inductor configured to couple a power supply node to a drain of the second NMOSFET; and a bias generation network configured to generate the first bias voltage and the second bias voltage in accordance with a reference current and a reference voltage, the bias generation network comprising a third NMOSFET, a fourth NMOSFET, a fifth NMOSFET, a first operational amplifier, and a second operational amplifier, wherein: the reference current injects into a drain of the third NMOSFET; the first operational amplifier outputs the first bias voltage to control both a gate of the third NMOSFET and a gate of the fourth NMOSFET in accordance with a voltage difference between the drain of the third NMOSFET and either a drain of the fourth NMOSFET or the reference voltage; the fifth NMOSFET is stacked upon the fourth NMOSFET in the same way as that the second NMOSFET is stacked upon the first NMOSFET; the second operational amplifier outputs the second bias voltage to control a gate of the fifth NMOSFET in accordance with a voltage difference between the reference voltage and the drain of the fourth NMOSFET; and a drain of the fifth NMOSFET connects to the power supply node.
2. The RF amplifier of claim 1, wherein the bias generation network further comprises a compensation capacitor coupled to the gate of the third NMOSFET to stabilize the first operational amplifier.
3. The RF amplifier of claim 1, wherein a width-to-length ratio of the fourth NMOSFET is scaled from a width-to-length ratio of the third NMOSFET by a first scaling factor.
4. The RF amplifier of claim 3, wherein a width-to-length ratio of the first NMOSFET is scaled from the width-to-length ratio of the fourth NMOSFET by a second scaling factor, and a width-to-length ratio of the second NMOSFET is scaled from the width-to-length ratio of the fifth NMOSFET by the second scaling factor.
5. The RF amplifier of claim 1 further comprising an AC (alternate current) coupling network comprising a capacitor configured to couple a first node to a second node and a resistor configured to couple the first bias voltage to the second node, to which a gate of the first NMOSFET is connected.
6. The RF amplifier of claim 1 further comprising a load capacitor connected to the load inductor in parallel.
7. A method comprising: incorporating a first NMOSFET (n-channel metal oxide semiconductor field effect transistor) as a common-source amplifier; incorporating a second NMOSFET as a cascode device stacked upon the first NMOSFET, wherein a source of the second NMOSFET connects to a drain of the first NMOSFET and a drain of the second NMOSFET connects to a power supply node via a load inductor; injecting a reference current into a drain of a third NMOSFET; using a first operational amplifier to generate a first bias voltage to control a gate of the first NMOSFET, a gate of the third NMOSFET, and a gate of a fourth NMOSFET in accordance with a voltage difference between the drain of the third NMOSFET and either a drain of the fourth NMOSFET or a reference voltage; incorporating a fifth NMOSFET stacked upon the fourth NMOSFET, wherein a source of the fifth NMOSFET connects to the drain of the fourth NMOSFET and a drain of the fifth NMOSFET connects to the power supply node; and using a second operational amplifier to generate a second bias voltage to control both a gate of the second NMOSFET and a gate of the fifth NMOSFET in accordance with a voltage difference between the reference voltage and the drain of the fourth NMOSFET.
8. The method of claim 7 further comprising incorporating a compensation capacitor coupled to the gate of the third NMOSFET to stabilize the first operational amplifier.
9. The method of claim 7, wherein a width-to-length ratio of the fourth NMOSFET is scaled from a width-to-length ratio of the third NMOSFET by a first scaling factor.
10. The method of claim 9, wherein a width-to-length ratio of the first NMOSFET is scaled from the width-to-length ratio of the fourth NMOSFET by a second scaling factor, and a width-to-length ratio of the second NMOSFET is scaled from the width-to-length ratio of the fifth NMOSFET by the second scaling factor.
11. The method of claim 7 further comprising using an AC (alternate current) coupling capacitor configured to couple a first node to a second node and a resistor configured to couple the first bias voltage to the second node, to which a gate of the first NMOSFET is connected.
12. The method of claim 7 further comprising incorporating a load capacitor connected to the load inductor in parallel.
13. A method comprising: incorporating a cascode amplifier comprising a second NMOSFET stacked upon a first NMOSFET; incorporating a fifth NMOSFET stacked upon a fourth NMOSFET in the same way as the second NMOSFET is stacked upon the first NMOSFET; injecting a reference current into a drain of a third NMOSFET; configuring the third NMOSFET and the fourth NMOSFET to be a current mirror by using a first bias voltage to control both a gate of the third NMOSFET and a gate of the fourth NMOSFET; establishing the first bias voltage in accordance with a voltage difference between the drain of the third NMOSFET and either a drain of the fourth NMOSFET or a reference voltage using a first operational amplifier; establishing a second bias voltage to control a gate of the fifth NMOSFET in accordance with a voltage difference between the reference voltage and the drain of the fourth NMOSFET; using the first bias voltage to control a gate of the first NMOSFET; using the second bias voltage to control of a gate of the second NMOSFET; connecting a drain of the fifth NMOSFET to a power supply node; and connecting a drain of the second NMOSFET to the power supply node via a load inductor.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DETAILED DESCRIPTION OF THIS DISCLOSURE
[0013] The present disclosure is directed to RF amplifiers. While the specification describes several example embodiments considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.
[0014] Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as voltage, current, circuit node, signal, power supply, ground, bias voltage, DC (direct current), AC (alternate current), NMOSFET (n-channel metal oxide semiconductor field effect transistor), PMOSFET (p-channel metal oxide semiconductor field effect transistor), current mirror, current source, operational amplifier, common-source amplifier, cascode, and impedance. Terms like these are used in a context of microelectronics, and the associated concepts are apparent to those of ordinary skills in the art and thus will not be explained in detail in this disclosure.
[0015] A circuit is a collection of a transistor, a capacitor, a resistor, and/or other electronic devices inter-connected in a certain manner to embody a certain function.
[0016] A network is a circuit or a collection of circuits configured to embody a certain function.
[0017] In this present disclosure, a circuit node is simply referred to as a node for short, as the meaning is clear from a context of microelectronics.
[0018] Those of ordinary skill in the art can recognize a resistor symbol, a capacitor symbol, an inductor symbol, and a MOSFET (metal-oxide semiconductor field effect transistor) symbol, for both PMOSFET and NMOSFET, in a schematic diagram. A MOSFET has a source terminal, a gate terminal, and a drain terminal, all of which those of ordinary skill in the art can easily identify. Pertaining to a MOSFET, in this present disclosure, a source terminal, a gate terminal, and a drain terminal are simply referred to as source, gate, and drain, for short, without causing confusion in a context of microelectronics.
[0019] Those of ordinary skills in the art can read schematics of a circuit comprising resistors, capacitors, NMOSFET, and PMOSFET, and do not need a verbose description about how one transistor, resistor, or capacitor connects with another in the schematics.
[0020] This present disclosure is disclosed in terms of an engineering sense. For instance, regarding two variables X and Y, when it is said that X is equal to Y, it means that X is approximately equal to Y, i.e., a difference between X and Y is smaller than a specified engineering tolerance. When it is said that X is zero, it means that X is approximately zero, i.e., X is smaller than a specified engineering tolerance. When it is said that X is substantially smaller than Y, it means that X is negligible with respect to Y, i.e., a ratio between X and Y is smaller than an engineering tolerance and therefore X is negligible when compared to Y.
[0021] Throughout this disclosure, V.sub.DD denotes a power supply node, and V.sub.SS denotes a ground node. Note that a ground node is a node at which a voltage level is substantially zero, and a power supply node is a node at which a voltage level is substantially stationary and higher than zero.
[0022] In this present disclosure, a signal is a voltage or a current of a variable level that can vary with time. A (voltage or current) level of a signal at a moment represents a state of the signal at that moment.
[0023] A schematic diagram of a RF amplifier 100 in accordance with an embodiment of the present disclosure in shown in
[0024] It should be noted that current flow direction and signal propagation direction are different things. In terms of current flow, I.sub.out flows from the fourth node 104 into the cascode amplifier 110. In terms of signal propagation, however, it's the cascode amplifier 110 that initiates and dictates I.sub.out, while the fourth node 104 and the voltage thereof V.sub.104 respond passively. That is why it is said that the cascode amplifier 110 outputs I.sub.out to the fourth node 104, albeit I.sub.out flows from the fourth node 104 into the cascode amplifier 110.
[0025] Load network 150, which includes a load inductor L 150, provides DC coupling between the power supply node V.sub.DD and a voltage V 104 at the fourth node 104; DC wise, V 104 is effectively shorted to V.sub.DD. A source of M1 connects to a fifth node 105. In an optional embodiment, RF amplifier 100 further comprises a source degeneration network 140 comprising a source inductor L 140 configured to provide DC coupling between the ground node V.sub.SS and the fifth node 105; in this case, DC wise, a voltage V 105 at the fifth node 105 is shorted to V.sub.SS. In an alternative embodiment, the source inductor L 140 is replaced by a short circuit so that V 105 is outright shorted to V.sub.SS.
[0026] The bias generation network comprises a third NMOSFET M3, a fourth NMOSFET M4, a fifth NMOSFET M5, a first operational amplifier OP1, and a second operational amplifier OP2. A reference current I.sub.ref injects into a drain of M3. M3 and M4 form a current mirror, wherein a gate of M3 is connects to a gate of M4 at a sixth node 106, and a drain current I.sub.m of M4 is equal to the reference current I.sub.ref times a scaling factor that depends on width-to-length ratios of M3 and M4. An objective of the bias generation network is to ensure that M3 and M4 can form a very accurate current mirror despite channel length modulation; this is achieved by using a negative feedback loop. In a negative feedback loop comprising an operational amplifier of a sufficiently large gain, a voltage at a positive input terminal (+) and a voltage at a negative input terminal (?) will be adjusted and made equal. In a first embodiment wherein a first dashed line DL1 is a solid connection while a second dashed line DL2 is broken, OP1 outputs the first bias voltage V.sub.b1 to the sixth node 106 to control both the gate of M3 and the gate of M4 in accordance with a voltage difference between a voltage V.sub.107 at a seventh node 107 and a voltage V.sub.108 at an eighth node 108, wherein the drain of M3 and the drain of M4 connect to the seventh node 107 and the eighth node 108, respectively. M4 and M5 mimic M1 and M2 in a cascode topology: like M1, M4 is an input device; and like M2, M5 is a cascode device that is stacked upon M4, wherein a source of M5 connects to the drain of M4 and a drain of M5 connects to V.sub.DD. OP2 generates a second bias voltage V.sub.b2 to control both a gate of M5 and a gate of M2 in accordance with a voltage difference between a reference voltage V.sub.ref and V.sub.108. OP2 and M5 forms a first negative feedback loop to force V.sub.108 (which is the voltage at the ? terminal of OP2) to be equal to V.sub.ref (which is the voltage at the + terminal of OP2), provided a gain of OP2 is sufficiently large. OP1 and M3 forms a second negative feedback loop to force V.sub.107 (which is the voltage at the + terminal of OP1) to be equal to V.sub.108 (which is the voltage at the ? terminal of OP1), and thus equal to V.sub.ref, provided a gain of OP1 is sufficiently large.
[0027] In a second embodiment, wherein the second dashed line DL2 is a solid connection while the first dashed line DL1 is broken, OP1 outputs the first bias voltage V.sub.b1 to the sixth node 106 to control both the gate of M3 and the gate of M4 in accordance with a voltage difference between V.sub.107 and V.sub.ref. In this case, the second negative feedback loop will force V.sub.107 (which is the voltage at the + terminal of OP1) to be equal to V.sub.ref, while the first negative feedback loop will still force V.sub.108 to be equal to V.sub.ref (which is the voltage at the ? terminal of OP1). As such, V.sub.107 will still be forced to be equal to V.sub.108. In summary, the negative input terminal (?) of OP1 can connect to either V.sub.108 (in the first embodiment) or V.sub.ref (in the second embodiment), but the result is the same: V.sub.107 will be equal to V.sub.108, so that a channel modulation effect of M3 can be the same as a channel modulation effect of M4, resulting in a highly accurate current mirroring from I.sub.ref to I.sub.m.
[0028] Bias generation network 160 further comprises a compensation capacitor C.sub.160 configured to shunt the sixth node 106 to the ground node V.sub.SS to provide a frequency compensation that can improve stability of the second negative feedback loop. In a further embodiment not shown in the figure but clear to those of ordinary skill in the art, bias generation network 160 further comprises a serial resistor that is inserted between the sixth node 106 and the compensation capacitor C.sub.160. Concepts of stability and frequency compensation regarding a negative feedback loop are well understood by those of ordinary skill in the art and thus not described in detail here. Those skilled in the art can choose to use a frequency compensation scheme at their discretion and do not necessarily need to use the same circuit shown in the bias generation network 160.
[0029] Let width-to-length ratios of M1, M2, M3, M4, and M5 be W.sub.1/L.sub.1, W.sub.2/L.sub.2, W.sub.3/L.sub.3, W.sub.4/L.sub.4, and W.sub.5/L.sub.5, respectively. Let a scaling factor from W.sub.3/L.sub.3 to W.sub.4/L.sub.4 be ?.sub.1, and a scaling factor from W.sub.4/L.sub.4 to W.sub.1/L.sub.1 be ?.sub.2, i.e.,
?.sub.1?(W.sub.4/L.sub.4)/(W.sub.3/L.sub.3)(1)
?.sub.2?(W.sub.1/L.sub.1)/(W.sub.4/L.sub.4)(2)
[0030] The scaling factor from W.sub.5/L.sub.5 to W.sub.2/L.sub.2 is the same as the scaling factor from W.sub.4/L.sub.4 to W.sub.1/L.sub.1 ?.sub.2, i.e.,
?.sub.2=(W.sub.2/L.sub.2)/(W.sub.5/L.sub.5)(3)
[0031] M3 and M4 have the same gate voltage (V.sub.bi), the same drain voltage (thanks to the second negative feedback loop), and the same source voltage (V.sub.SS), therefore I.sub.ref is accurately mirrored into I.sub.m with a scaling factor determined by (W.sub.4/L.sub.4)/(W.sub.3/L.sub.3). From equation (1), we obtain
I.sub.m=?.sub.1I.sub.ref(4)
[0032] In a static condition, M1 and M4 have the same gate voltage (V.sub.b1) and the same source voltage (V.sub.SS), M2 and M5 have the same gate voltage (V.sub.b2) and the same drain voltage (V.sub.DD), and the scaling factor (of the width-to-length ratio) from M4 to M1 is the same as the scaling factor (of the width-to-length ratio) from M5 to M2. This demands a voltage V.sub.103 at the third node 103 must be equal to the voltage V.sub.108 at the eighth node 108; i.e., a DC voltage of V.sub.103 must be equal to V.sub.ref. As such, the output current I.sub.out is scaled from the mirrored current I.sub.m by the factor ?.sub.2, i.e.,
I.sub.out=?.sub.2I.sub.m(5)
From, equations (4) and (5), we have
I.sub.out=?.sub.1?.sub.2I.sub.ref(6)
[0033] The output current of cascode amplifier 110, therefore, can be highly accurate, thanks to using the bias generation network 160 comprising two negative feedback loops along with a proper scaling of width-to-length ratios of devices. The accuracy relies on merits of negative feedback loops and device matching and can be highly insensitive to PVT variation. This fulfills a first objective of the present disclosure.
[0034] A drain-to-source voltage of M1 is V.sub.ref and a drain-to-source voltage of M2 is V.sub.DD-V.sub.ref; both can be accurate and insensitive to process and temperature variation. It is inevitable, however, that a headroom of cascode amplifier 110 is dependent upon and thus limited by V.sub.DD, since a sum of the drain-to-source voltage of M1 and the drain-to-source voltage of M2 must be equal to V.sub.DD. Nevertheless, the headroom can be optimized if V.sub.ref tracks V.sub.DD; in this case, the drain-to-source voltages of M1 and M2 both track V.sub.DD, and an adverse impact of headroom reduction due to a drop of V.sub.DD can be alleviated by distributing the reduction between M1 and M2. This fulfills a second objective of the present disclosure, that a healthy headroom can be maintained despite PVT variation.
[0035] In an embodiment, V.sub.ref is derived from V.sub.DD by using a resistive voltage divider that divides V.sub.DD into V.sub.ref, wherein two resistors are connected in series and inserted between V.sub.DD and V.sub.SS, and V.sub.ref is tapped at a connection point of the two resistors. The cascode device embodied by M2 usually provides a voltage gain (so that a swing of V.sub.104 is greater than a swing of V.sub.103), it is advantageous to allocate more headroom to M2 than M1. Therefore, in an embodiment, V.sub.ref is lower than half V.sub.DD.
[0036] In a further embodiment, the RF amplifier 100 further comprises an impedance matching network 120 comprising a serial inductor L.sub.120 and configured to provide impedance matching between the first node 101 and a ninth node 109; in this case, an input of the RF amplifier 100 is a voltage V.sub.109 at the ninth node 109, instead of a voltage V.sub.101 at the first node 101. Concept of impedance matching is well understood by those of ordinary skill in the art and thus not explained in detail.
[0037] Source degeneration network 140, which comprises the source inductor L.sub.140, is also used to provide impedance matching. Using a source inductor to provide impedance matching is well known in the prior art and thus not described in detail here. In an embodiment, the source inductor L.sub.140 comprises a metal trace. In an, the source inductor L.sub.140 comprises a bonding wire of a package.
[0038] In an optional embodiment, the load network 150 further comprises a load capacitor C.sub.150 that is connected to the load inductor L.sub.150 in parallel to form a resonant network to boost a load impedance Z.sub.150 at a frequency of interest. Concepts of resonant network and impedance are well understood by those of ordinary skill in the art and thus not described in detail here. In an embodiment, the load capacitor C.sub.150 comprises a parasitic capacitor.
[0039] Operational amplifiers are well known in the prior art. Those skilled in the art can freely choose a suitable circuit implementation known in the prior art to embody OP1 and OP2 at their discretion.
[0040] As illustrated by a flow diagram shown in
[0041] As illustrated by a flow diagram shown in
[0042] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure.
[0043] Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.