DUAL-PATH CHARGE PUMP

Abstract

Examples of improved charge pumps are disclosed. In one example, a system comprises a first charge path comprising a first stage to boost an input voltage and a second stage to boost a voltage received from the first stage of the first charge path; and a second charge path comprising a first stage to boost an input voltage and a second stage to boost a voltage received from the first stage of the second charge path; wherein an output of the second stage of the first charge path is coupled to the first stage of the second charge path and an output of the second stage of the second charge path is coupled to the first stage of the first charge path.

Claims

1. A system comprising: a first charge path comprising a first stage to boost an input voltage and a second stage to boost a voltage received from the first stage of the first charge path; and a second charge path comprising a first stage to boost an input voltage and a second stage to boost a voltage received from the first stage of the second charge path; wherein an output of the second stage of the first charge path is coupled to the first stage of the second charge path and an output of the second stage of the second charge path is coupled to the first stage of the first charge path.

2. The system of claim 1, wherein the output of the second stage of the second charge path is applied to a gate of a first boost transistor in the first stage of the first charge path.

3. The system of claim 2, wherein the output of the second stage of the first charge path is applied to a gate of a second boost transistor in the first stage of the second charge path.

4. The system of claim 3, wherein the second boost transistor is an NMOS transistor.

5. The system of claim 4, wherein the first boost transistor is an NMOS transistor.

6. The system of claim 3, wherein the first stage of the first charge path and the second stage of the second charge path receive a first clock signal and a second clock signal.

7. The system of claim 6, wherein the first stage of the second charge path and the second stage of the first charge path receive a third clock signal and a fourth clock signal.

8. The system of claim 7, wherein the first clock signal and the second clock signal are complementary clock signals.

9. The system of claim 8, wherein the third clock signal and the fourth clock signal are complementary clock signals.

10. The system of claim 1, wherein the second stage in the first charge path comprises: a first native NMOS transistor comprising a first terminal coupled to a supply voltage, a second terminal, and a gate for receiving a control signal; and a second native NMOS transistor comprising a first terminal coupled to the second terminal of the first native NMOS transistor, a second terminal coupled the output of the second stage of the first charge path, and a gate coupled to the supply voltage.

11. The system of claim 10, wherein the second stage in the second charge path comprises: a third native NMOS transistor comprising a first terminal coupled to a supply voltage, a second terminal, and a gate for receiving a control signal; and a fourth native NMOS transistor comprising a first terminal coupled to the second terminal of the first native NMOS transistor, a second terminal coupled the output of the second stage of the second charge path, and a gate coupled to the supply voltage.

12. A method comprising: boosting a first voltage, by a first stage in a first charge path, to generate a second voltage; boosting the second voltage, by a second stage in the first charge path, to generate a third voltage; boosting a fourth voltage, by a first stage in a second charge path, to generate a fifth voltage; boosting the fifth voltage, by a second stage in the second charge path, to generate a sixth voltage; applying the third voltage to the first stage of the second charge path; and applying the sixth voltage to the first stage of the first charge path.

13. The method of claim 12, wherein applying the sixth voltage to the first stage of the first charge path comprises applying the sixth voltage to a gate of a first boost transistor in the first stage of the first charge path.

14. The method of claim 13, wherein applying the third voltage to the first stage of the second charge path comprises applying the third voltage to a gate of a second boost transistor in the first stage of the second charge path.

15. The method of claim 14, wherein the second boost transistor is an NMOS transistor.

16. The method of claim 15, wherein the first boost transistor is an NMOS transistor.

17. The method of claim 16, comprising: applying a first clock signal to the first stage of the first charge path and the second stage of the second charge path; and applying a second clock signal to the first stage of the first charge path and the second stage of the second charge path.

18. The method of claim 17, comprising: applying a third clock signal to the first stage of the second charge path and the second stage of the first charge path; and applying a fourth clock signal to the first stage of the second charge path and the second stage of the first charge path.

19. The method of claim 18, wherein the first clock signal and the second clock signal are complementary clock signals.

20. The method of claim 19, wherein the third clock signal and the fourth clock signal are complementary clock signals.

21. A system comprising: a first charge path comprising (i+1) boost stages, where i>1; and a second charge path comprising (i+1) boost stages; wherein the first charge path and the second charge path receive an input voltage and generate an output voltage greater than the input voltage; and wherein an output of boost stage (N+1) of the first charge path is coupled to boost stage N of the second charge path and an output of boost stage (N+1) of the second charge path is coupled to boost stage N of the first charge path, where 1?N?i.

22. The system of claim 21, comprising: a first clock signal and a second clock signal provided to the first charge path, wherein the first clock signal and the second clock signal are complementary clock signals; and a third clock signal and a fourth clock signal provided to the second charge path, wherein the third clock signal and the fourth clock signal are complementary clock signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 depicts a prior art split gate flash memory cell.

[0028] FIG. 2 depicts another prior art split gate flash memory cell.

[0029] FIG. 3 depicts another prior art split gate flash memory cell.

[0030] FIG. 4 depicts another prior art split gate flash memory cell.

[0031] FIG. 5 depicts a prior art memory system.

[0032] FIG. 6 depicts a prior art charge pump.

[0033] FIG. 7 depicts a clocking scheme for the prior art charge pump of FIG. 6.

[0034] FIG. 8 depicts a simplified diagram of the prior art charge pump of FIG. 6.

[0035] FIG. 9 depicts a charge pump.

[0036] FIG. 10 depicts a clocking scheme for the charge pump of FIG. 9.

[0037] FIG. 11 depicts a simplified diagram of the charge pump of FIG. 6.

DETAILED DESCRIPTION OF THE INVENTION

[0038] FIG. 9 depicts charge pump 900. Charge pump 900 comprises i+1 stages, which are stages 901-0 (stage 0), 901-1 (stage 1), . . . , 901-(i?1) (pre-out stage), and 901-i (output stage). Charge pump 900 also comprises a dual path, specifically, path 901 and 951. Each stage within a path can be referred to as a boost stage. Each boost stage boosts its received input voltage and outputs the boosted voltage to the next stage as the input voltage for the next stage, or in the case of stage 901-i, as the output Vout of charge pump 900. Paths 901 and 951 operate out of phase with one another, such that the output, Vout, is always at the maximum boosted voltage. FIG. 10 depicts examples of clock timing diagrams for CK1, CK2, CK3, and CK4 used in charge pump 900. Clocks signals CK1, CK2, CK3, and CK4 are generated from a common clock signal, denoted CLK. Clock signals CK1 and CK2 are complements of each other, and clock signals CK3 and CK4 are complements of each other. A respective first edge of clock signals CK1 and CK2 are delayed from a respective first edge of common clock signal CLK by an amount Tdelay1, and a respective second edge of clock signals CK1 and CK2 are aligned with a respective second edge of common clock signal CLK. A respective first edge of clock signals CK3 and CK4 are aligned with a respective first edge of common clock signal CLK and a respective second edge of clock signals CK3 and CK4 are delayed from a respective second edge of common clock signal CLK by an amount Tdelay2. Charge pump 900 improves against the body effect compared to prior art charge pump 600, as discussed in greater detail below with reference to FIG. 11.

[0039] FIG. 11 depicts three example stages, stages N, N+1 and N+2 (where N ranges from 0 to (i?1) corresponding to stages 901-0, . . . , 901-i in FIG. 9) for paths 901 and 951 in charge pump 900. Respective boost stages in respective paths in charge pump 900 perform the boost operation in the same manner, which will explained with reference to boost stage corresponding to stage N in path 901. Node D is the input voltage received by stage N+1 in path 901. CK2 and CK3 are clock signals as shown in FIG. 10 and are coupled to capacitors 1105 and 1106, respectively. When CK2 goes high, the voltage on the top plate of capacitor 1105, which is node D, is boosted by the amount of the voltage by which CK2 increased. There is a delay period, Tdelay2, between a rising edge of CK2 and a rising edge of CK3 as shown in FIG. 10, and this delay will utilize a higher potential on node D to pre-charge node A through MB_T2 by the amount of OUT2 minus V.sub.TH of MB_T2. Thereafter, CK3 goes high, and the voltage on the top plate of capacitor 1106, which is node A, is boosted by the amount of the voltage by which CK3 increased. Consequently, the potential at node A now is equal to an amount of the voltage boosted from CK3 plus an amount of voltage from the pre-charge time, and the charge from node D to node E now can pass more effectively due to the boosted voltage on node A.

[0040] Referring back to FIG. 8, transistor 806 can be enabled to place VOUT at an initial voltage of VDD, or it can remain enabled throughout operation of charge pump 600 to provide a floor for the value of VOUT (VOUT will always be equal to or exceed VDD).

[0041] Stage N+2 in path 901, or charge pump 900, comprises native NMOS transistor 1103 (a first native NMOS transistor) and native NMOS transistor 1104 (a second native NMOS transistor), which have lower threshold voltages that NMOS transistor 806 used in prior art charge pump 600. The use of native NMOS transistors 1103 and 1104 instead of NMOS transistors allows for a high initial voltage to be placed on OUT1 and similar nodes in other stages, which allows charge pump 900 to hit its target faster. In addition, the signal VGI provides a gating signal to native NMOS transistor 1103 and may turn off native NMOS transistor 1103 right after charge pump 900 is activated, to reduce the chance of significant leakage due to the low threshold voltage of native NMOS transistor 1103. Native NMOS transistor 1104 is provided to reduce stress on native NMOS transistor 1103, as the voltage difference between the source and gate of native NMOS transistor 1103 will be relatively large (HV?0V) when charge pump 900 is activated, where HV is the high voltage generated by the charge pump.

[0042] Native NMOS transistors 1153 (a third native NMOS transistor) and 1154 (a fourth native NMOS transistor) play the same role in stage N+1 of path 951 as does native NMOS transistors 1103 and 1104 in stage N+1 of path 901. The other pump stages of charge pump 900 contain native NMOS transistors that play the same role, as shown in FIGS. 9 and 11.

[0043] To overcome the body effect on boost transistors 1101 (MB_T2) (which is a first boost transistor) and 1151 (MB_B2) (which is a second boost transistor), charge pump 900 applies higher voltages to the gates of those transistors than in prior art charge pump 600. Specifically, charge pump 900 uses the output voltage from path 951 of stage N+2 (node OUT2) as the gate voltage for transistor 1101 (MB_T2) in stage N+1 of path 901 and the output voltage from path 901 of stage N+2 (node OUT1) as the gate voltage for transistor 1151 (MB_B2) in stage N+1 of path 951. Due to the boost provided by the subsequent stage, the gate voltages for transistors 1101 (MB_T2) and 1151 (MB_B2) are larger than would be the case in prior art charge pump 600, and node A and node B, respectively, can be pre-charged to a higher level than would be the case in prior art charge pump 600, which means that the gate voltages of transistors 1102 (MS_T2) and 1152 (MS B2) after boosted by CK3 and CK1, respectively, would be higher than would be the case in prior art charge pump 600, so that they are able to deal with the increased V.sub.TH after the body effect. As a result, the boosting is more effective in charge pump 900 than in prior art charge pump 600. Charge pump 900 is able to provide a higher output voltage than charge pump 600, with higher efficiency and lower process-temperature variation.

[0044] The boost stages of charge pump 900 can operate to perform a method comprising boosting a first voltage (the voltage at node D), by a first stage (stage N+1) in a first charge path (path 901), to generate a second voltage (the voltage at node E); boosting the second voltage, by a second stage (stage N+2) in the first charge path (path 901), to generate a third voltage (the voltage OUT1); boosting a fourth voltage (the voltage at node C), by a first stage (stage N+1) in a second charge path (path 951), to generate a fifth voltage (the voltage at node F); boosting the fifth voltage, by a second stage (stage N+2) in the second charge path (path 951), to generate a sixth voltage (the voltage OUT2); applying the third voltage to the first stage of the second charge path; and applying the sixth voltage to the first stage of the first charge path; wherein applying the sixth voltage to the first stage of the first charge path comprises applying the sixth voltage to a gate of a first boost transistor (1101) in the first stage of the first charge path and applying the third voltage to the first stage of the second charge path comprises applying the third voltage to a gate of a second boost transistor (1151) in the first stage of the second charge path. The method can further comprise applying a first clock signal (CK3) to the first stage of the first charge path and the second stage of the second charge path; applying a second clock signal (CK4) to the first stage of the first charge path and the second stage of the second charge path; applying a third clock signal (CK1) to the first stage of the second charge path and the second stage of the first charge path; and applying a fourth clock signal (CK2) to the first stage of the second charge path and the second stage of the first charge path.

[0045] It should be noted that, as used herein, the terms over and on both inclusively include directly on (no intermediate materials, elements or space disposed therebetween) and indirectly on (intermediate materials, elements or space disposed therebetween). Likewise, the term adjacent includes directly adjacent (no intermediate materials, elements or space disposed therebetween) and indirectly adjacent (intermediate materials, elements or space disposed there between), mounted to includes directly mounted to (no intermediate materials, elements or space disposed there between) and indirectly mounted to (intermediate materials, elements or spaced disposed there between), and electrically coupled includes directly electrically coupled to (no intermediate materials or elements there between that electrically connect the elements together) and indirectly electrically coupled to (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element over a substrate can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.