LATCH TYPE SENSE AMPLIFIER FOR NON-VOLATILE MEMORY

Abstract

A latch type sense amplifier includes three transistors, a latching device and two capacitors. The two drain/source terminals of the first transistor are connected with a first node and a second node. The gate terminal of the first transistor receives a reference voltage. The two drain/source terminals of the second transistor are connected with the first node and a third node. The gate terminal of the second transistor is connected with a data line. The two drain/source terminals of the third transistor are connected with a first supply voltage and the first node. The gate terminal of the third transistor receives an enable signal. The latching device is connected with the second node and the third node. The first capacitor is connected between gate terminals of the third transistor and the first transistor. The second capacitor is connected between gate terminals of the third transistor and the second transistor.

Claims

1. A latch type sense amplifier for a non-volatile memory, a selected memory cell of the non-volatile memory being connected with a data line, the latch type sense amplifier comprising: a first transistor, wherein a first drain/source terminal of the first transistor is connected with a first node, a second drain/source terminal of the first transistor is connected with a second node, a gate terminal of the first transistor receives a reference voltage, and the gate terminal of the first transistor is a first input terminal of the latch type sense amplifier; a second transistor, wherein a first drain/source terminal of the second transistor is connected with the first node, a second drain/source terminal of the second transistor is connected with a third node, a gate terminal of the second transistor is connected with the data line, and the gate terminal of the second transistor is a second input terminal of the latch type sense amplifier a third transistor, wherein a first drain/source terminal of the third transistor receives a first supply voltage, a second drain/source terminal of the third transistor is connected with the first node, and a gate terminal of the third transistor receives an enable signal; a latching device connected with the second node and the third node; a first capacitor, wherein a first terminal of the first capacitor is connected with the gate terminal of the third transistor, and a second terminal of the first capacitor is connected with the gate terminal of the first transistor; and a second capacitor, wherein a first terminal of the second capacitor is connected with the gate terminal of the third transistor, and a second terminal of the second capacitor is connected with the gate terminal of the second transistor.

2. The latch type sense amplifier as claimed in claim 1, wherein a read cycle contains a charging phase and a sensing phase, wherein when the charging phase is switched to the sensing phase, the enable signal is activated, wherein when the enable signal is activated, a first couple voltage and a second couple voltage are respectively coupled to the first input terminal and the second input terminal of the sense amplifier according to a change of a voltage at the first node, and a third couple voltage and a fourth couple voltage are respectively coupled to the first input terminal and the second input terminal of the sense amplifier according to a change of the enable signal, wherein the first couple voltage and the third couple voltage are offset by each other, and the second couple voltage and the fourth couple voltage are offset by each other.

3. The latch type sense amplifier as claimed in claim 1, wherein the latching device: a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the second node, a second drain/source terminal of the fourth transistor receives a second supply voltage, and a gate terminal of the fourth transistor is connected with the third node; and a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with the third node, a second drain/source terminal of the fifth transistor receives the second supply voltage, and a gate terminal of the fifth transistor is connected with the second node, wherein the second node or the third node is an output terminal of the latch type sense amplifier, wherein in a sensing phase of a read cycle, the latch type sense amplifier generates an output signal to indicate a storing state of the selected memory cell.

4. The latch type sense amplifier as claimed in claim 3, wherein the first transistor, the second transistor and the third transistor are p-type transistors, and the fourth transistor and the fifth transistor are n-type transistors, wherein a magnitude of the first supply voltage is higher than a magnitude of the second supply voltage.

5. The latch type sense amplifier as claimed in claim 3, wherein the first transistor, the second transistor and the third transistor are n-type transistors, and the fourth transistor and the fifth transistor are p-type transistors, wherein a magnitude of the first supply voltage is lower than a magnitude of the second supply voltage.

6. The latch type sense amplifier as claimed in claim 1, wherein the latching device: a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the second node, a second drain/source terminal of the fourth transistor is connected with a fourth node, and a gate terminal of the fourth transistor is connected with a fifth node; a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with the third node, a second drain/source terminal of the fifth transistor is connected with the fifth node, and a gate terminal of the fifth transistor is connected with the fourth node; a sixth transistor, wherein a first drain/source terminal of the sixth transistor is connected with the fourth node, a second drain/source terminal of the sixth transistor receives a second supply voltage, and a gate terminal of the sixth transistor is connected with the fifth node; a seventh transistor, wherein a first drain/source terminal of the seventh transistor is connected with the fifth node, a second drain/source terminal of the seventh transistor receives the second supply voltage, and a gate terminal of the seventh transistor is connected with the fourth node; wherein the fourth node or the fifth node is an output terminal of the latch type sense amplifier, wherein in a sensing phase, the latch type sense amplifier generates an output signal to indicate a storing state of the selected memory cell.

7. The latch type sense amplifier as claimed in claim 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are p-type transistors, and the sixth transistor and the seventh transistor are n-type transistors, wherein a magnitude of the first supply voltage is higher than a magnitude of the second supply voltage.

8. The latch type sense amplifier as claimed in claim 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are n-type transistors, and the sixth transistor and the seventh transistor are p-type transistors, wherein a magnitude of the first supply voltage is lower than a magnitude of the second supply voltage.

9. The latch type sense amplifier as claimed in claim 1, wherein the latch type sense amplifier further comprises an auxiliary circuit, and the auxiliary circuit is connected with the data line, wherein in a reset phase of a read cycle, a voltage at the data line is maintained in an initial voltage under control of the auxiliary circuit.

10. The latch type sense amplifier as claimed in claim 9, wherein the auxiliary circuit comprises a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the data line, a second drain/source terminal of the fourth transistor receives a ground voltage, and a gate terminal of the fourth transistor receives a reset signal, wherein in the reset phase, the reset signal is activated, the fourth transistor is turned on, and the data line is discharged to the ground voltage, wherein the ground voltage is equal to the initial voltage.

11. The latch type sense amplifier as claimed in claim 1, wherein the latch type sense amplifier further comprises an auxiliary circuit, and the auxiliary circuit is connected with the data line, wherein in a pre-charge phase of a read cycle, a voltage at the data line is maintained in the first supply voltage under control of the auxiliary circuit, wherein after the pre-charge phase and in a reset phase of the read cycle, the voltage at the data line is maintained in an initial voltage under control of the auxiliary circuit.

12. The latch type sense amplifier as claimed in claim 11, wherein the auxiliary circuit comprises a fourth transistor and a fifth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the data line, a second drain/source terminal of the fourth transistor receives a ground voltage, a gate terminal of the fourth transistor receives a reset signal, a first drain/source of the fifth transistor is connected with the data line, a second drain/source terminal of the fifth transistor receives the first supply voltage, and a gate terminal of the fifth transistor receives a pre-charge signal, wherein in the pre-charge phase, the pre-charge signal is activated, and the fifth transistor is turned on, so that the data line is pre-charged to the first supply voltage, wherein in the reset phase, the reset signal is activated, and the fourth transistor is turned on, so that the data line is discharged to the ground voltage, wherein the ground voltage is equal to the initial voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

[0009] FIG. 1 is a schematic circuit diagram illustrating the architecture of a non-volatile memory;

[0010] FIG. 2A is a schematic circuit diagram illustrating an exemplary sensing circuit used in the non-volatile memory of the present invention;

[0011] FIG. 2B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 2A;

[0012] FIG. 3A is a schematic circuit diagram illustrating another exemplary sensing circuit used in the non-volatile memory of the present invention;

[0013] FIG. 3B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 3A;

[0014] FIG. 4A is a schematic circuit diagram illustrating a further exemplary sensing circuit used in the non-volatile memory of the present invention;

[0015] FIG. 4B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 4A;

[0016] FIG. 5A is a schematic circuit diagram illustrating a sense amplifier according to a first embodiment of the present invention;

[0017] FIG. 5B is a schematic circuit diagram illustrating a sense amplifier according to a second embodiment of the present invention;

[0018] FIG. 6A is a schematic circuit diagram illustrating a sensing circuit with sense amplifiers of the first embodiment;

[0019] FIG. 6B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 6A;

[0020] FIG. 7A is a schematic circuit diagram illustrating a sense amplifier according to a third embodiment of the present invention;

[0021] FIG. 7B is a schematic circuit diagram illustrating a sense amplifier according to a fourth embodiment of the present invention;

[0022] FIG. 8A is a schematic circuit diagram illustrating a sensing circuit with sense amplifiers of the third embodiment;

[0023] FIG. 8B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 8A;

[0024] FIGS. 9A and 9B schematically illustrate two other possible examples of the anti-couple devices used in the sense amplifier of the present invention;

[0025] FIG. 10A is a schematic circuit diagram illustrating a sense amplifier according to a fifth embodiment of the present invention; and

[0026] FIG. 10B is a schematic circuit diagram illustrating a sense amplifier according to a sixth embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0027] FIG. 1 is a schematic circuit diagram illustrating the architecture of a non-volatile memory. As shown in FIG. 1, the non-volatile memory comprises a memory cell array 110, a bit line selector 120 and a sensing circuit 130. The memory cell array 110 comprises m?n memory cells C.sub.11?C.sub.mn, wherein m and n are positive integers.

[0028] Please refer to FIG. 1 again. In the memory cell array 110, the n memory cells C.sub.11?C.sub.1n in the first row are connected with a word line WL.sub.1. Moreover, the n memory cells C.sub.11-C.sub.1n in the first row are respectively connected with corresponding n bit lines B.sub.L1-B.sub.Ln. The n memory cells C.sub.21?C.sub.2n in the second row are connected with a word line WL.sub.2. Moreover, the n memory cells C.sub.21?C.sub.2n in the second row are respectively connected with the corresponding n bit lines B.sub.L1-B.sub.Ln. The rest may be deduced by analogy. Similarly, the n memory cells C.sub.m1?C.sub.mn in the m-th row are connected with a word line WL.sub.m. Moreover, the n memory cells C.sub.m1?C.sub.mn in the m-th row are respectively connected with the corresponding n bit lines B.sub.L1-B.sub.Ln.

[0029] The bit line selector 120 is connected with the n bit lines B.sub.L1?B.sub.Ln and p data lines DL.sub.1?DL.sub.p, wherein p is a positive integer smaller than or equal to n. When the read action of the non-volatile memory is performed, the bit line selector 120 selects p bit lines from the n bit lines B.sub.L1?B.sub.Ln. In addition, the selected p bit lines are connected with the corresponding p data lines DL.sub.1?DL.sub.p through the bit line selector 120.

[0030] The sensing circuit 130 is connected with the p data lines DL.sub.1?DL.sub.p. When the read action is performed, the sensing circuit 130 receives the cell currents from the p data lines DL.sub.1?DL.sub.p and generates a p-bit output data Dout to indicate the storing states of corresponding p selected memory cells. In other words, the sensing circuit 130 can judge the storing states of the p memory cells in the selected row.

[0031] For example, n is 32, and p is 8. When the read action is performed, the word line WL 1 is activated. In other words, the first row is the selected row. In a first sensing cycle of the read action, the bit lines BL.sub.1?BL.sub.8 are respectively connected with the data lines DL.sub.1?DL.sub.8 through the bit line selector 120. Consequently, the eight memory cells C.sub.11?C.sub.18 in the selected row are the selected memory cells. The cell currents generated by the selected memory cells C.sub.11?C.sub.18 flow to the sensing circuit 130. According to the cell currents from the data lines DL.sub.1?DL.sub.8, the sensing circuit 130 generates a one-byte output data Dout to indicate the storing states of the selected memory cells C.sub.11?C.sub.18.

[0032] Similarly, in the second, third and fourth sensing cycles of the read action, the bit lines BL.sub.9?BL.sub.16, BL.sub.17?BL.sub.24 and BL.sub.25?BL.sub.32 are respectively and sequentially connected with the data lines DL.sub.1?DL.sub.8 through the bit line selector 120. In addition, the sensing circuit 130 generates the corresponding output data Dout sequentially. According to the four output data Dout generated in the four sensing cycles, the sensing circuit 130 acquires the storing states of all memory cells C1.sub.11?C.sub.1n in the first row (i.e., the first selected row). The operating principles of the sensing circuit 130 will be described as follows.

[0033] FIG. 2A is a schematic circuit diagram illustrating an exemplary sensing circuit used in the non-volatile memory of the present invention. FIG. 2B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 2A. The sensing circuit 130 comprises p sense amplifiers 201?20p. The circuitry structures of the p sense amplifiers 201?20p are identical. The first input terminal of the sense amplifier 201 receives a reference voltage V.sub.REF. The second input terminal of the sense amplifier 201 is connected with the data line DL.sub.1. The enable terminal of the sense amplifier 201 receives an enable signal EN. The output terminal of the sense amplifier 201 generates an output signal D.sub.O1. The first input terminal of the sense amplifier 202 receives the reference voltage V.sub.REF. The second input terminal of the sense amplifier 202 is connected with the data line DL.sub.2. The enable terminal of the sense amplifier 202 receives the enable signal EN. The output terminal of the sense amplifier 202 generates an output signal D.sub.O2. The rest may be deduced by analogy. Similarly, the first input terminal of the sense amplifier 20p receives the reference voltage V.sub.REF. The second input terminal of the sense amplifier 20p is connected with the data line DL.sub.p. The enable terminal of the sense amplifier 20p receives the enable signal EN. The output terminal of the sense amplifier 20p generates an output signal Don. Moreover, the p output signals D.sub.O1?D.sub.Op are collaboratively formed as the output data Dout.

[0034] In a read cycle, p selected memory cells in the selected row of the memory cell array 110 are respectively connected with the data lines DL.sub.1?DL.sub.p through the bit line selector 120. The p selected memory cells respectively generate p cell currents I.sub.CELL1?I.sub.CELLp to charge the corresponding data lines DL.sub.1?DL.sub.p. Consequently, the data lines DL.sub.1?DL.sub.p respectively generate the corresponding charged voltages V.sub.DL1?V.sub.DLp. In other words, the changes of the charged voltages V.sub.DL1?V.sub.DLp can be respectively determined according to the magnitudes of the cell currents I.sub.CELL1?I.sub.CELLp. Moreover, the storing states of the p selected memory cells are respectively determined by the p sense amplifiers 201?20p of the sensing circuit 130 according to the charged voltages V.sub.DL1?V.sub.DLp.

[0035] In another read cycle, other p selected memory cells in the selected row of the memory cell array 110 are respectively connected with the data lines DL.sub.1?DL.sub.p through the bit line selector 120. The p selected memory cells respectively generate p cell currents I.sub.CELL1?I.sub.CELLp to charge the corresponding data lines DL.sub.1?DL.sub.p. Consequently, the data lines DL.sub.1-DL.sub.p respectively generate the corresponding charged voltages V.sub.DL1?V.sub.DLp. Moreover, the storing states of the p selected memory cells are respectively determined by the p sense amplifiers 201?20p of the sensing circuit 130 according to the charged voltages V.sub.DL1?V.sub.DLp.

[0036] Please refer to FIG. 2B. In the time interval between the time point t.sub.A and the time point t.sub.D, a read cycle signal R.sub.CYCLE is in the high-level state to represent a read cycle. Generally, different bit lines BL.sub.1?BL.sub.n are selected to be connected with the corresponding data lines DL.sub.1?DL.sub.p through the bit line selector 120 according to the read cycle signal R.sub.CYCLE. As shown in FIG. 2B, the read cycle contains a charging phase and a sensing phase.

[0037] The time interval between the time point t.sub.A and the time point t.sub.B is the charging phase. In the charging phase, the p selected memory cells respectively generate the p cell currents I.sub.CELL1?I.sub.CELLp to charge the corresponding data lines DL.sub.1?DL.sub.p. Consequently, the data lines DL.sub.1?DL.sub.p respectively generate the corresponding charged voltages V.sub.DL1?V.sub.DLp. For example, the cell current I.sub.CELL1 is lower than the cell current I.sub.CELL2. Consequently, as shown in FIG. 2B, the charged voltages V.sub.DL1 on the data line DL.sub.1 rises at a slower rate, and the charged voltages V.sub.DL2 on the data line DL.sub.1 rises at a faster rate.

[0038] The time interval between the time point t.sub.B and the time point t.sub.C is the sensing phase. In the sensing phase, the enable signal EN is switched from the high-level state to the low-level state, indicating that the enable signal EN is activated. Meanwhile, the sense amplifiers 201 and 202 are activated. Moreover, the storing states of the selected memory cells are respectively determined according to the relationship between the reference voltage V.sub.REF and the charged voltages V.sub.DL1 and V.sub.DL2. As shown in FIG. 2B, the charged voltage V.sub.DL1 is lower than the reference voltage V.sub.REF. Consequently, the output signal D.sub.O1 outputted from the sense amplifier 201 has a first voltage level (e.g., a low voltage level). Moreover, as shown in FIG. 2B, the charged voltage V.sub.DL2 is higher than the reference voltage V.sub.REF. Consequently, the output signal D.sub.O2 outputted from the sense amplifier 202 has a second voltage level (e.g., a high voltage level).

[0039] At the time point t.sub.D, the read cycle is ended. Since the output signal D.sub.O1 outputted from the sense amplifier 201 has the first voltage level (e.g., the low voltage level), it is confirmed that the selected memory cell connected with the data line DL.sub.1 is in the first storing state. Since the output signal D.sub.O2 outputted from the sense amplifier 202 has the second voltage level (e.g., the high voltage level), it is confirmed that the selected memory cell connected with the data line DL.sub.2 is in the second storing state.

[0040] In another read cycle, other p selected memory cells in the selected row of the memory cell array 110 are respectively connected with the data lines DL.sub.1?DL.sub.p through the bit line selector 120. The storing states of the p selected memory cells are respectively determined by these p sense amplifiers 201?20p of the sensing circuit 130 according to the charged voltages V.sub.DL1?V.sub.DLp. The operating principles are similar to those mentioned above, and not redundantly described herein.

[0041] In some embodiments, the sensing circuit 130 further comprises p auxiliary circuits. The p auxiliary circuits are respectively connected with the p data lines DL.sub.1?DL.sub.p. Due to the arrangement of the p auxiliary circuits, the initial voltages on all of the data lines DL.sub.1?DL.sub.p are identical. For succinctness, only two auxiliary circuits connected with two corresponding sense amplifiers will be described.

[0042] FIG. 3A is a schematic circuit diagram illustrating another exemplary sensing circuit used in the non-volatile memory of the present invention. FIG. 3B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 3A. In FIG. 3B, the time interval between the time point t.sub.1 and the time point t.sub.D is a read cycle. In the read cycle, a read cycle signal R.sub.CYCLE is in the high-level state. Moreover, the read cycle contains a reset phase, a charging phase and a sensing phase.

[0043] In comparison with the sensing circuit 130 shown in FIG. 2A, the sensing circuit 230 of this embodiment further comprises p auxiliary circuits. For succinctness, only two auxiliary circuits 221 and 222 are shown in FIG. 3A. In the sensing circuit 230 shown in FIG. 3A, the data lines DL.sub.1 and DL.sub.2 are respectively connected with the corresponding auxiliary circuits 221 and 222. Each of the auxiliary circuits 221 and 222 comprises a pull-down device. For example, the pull-down device in the auxiliary circuit 221 is an n-type transistor M.sub.PD1, and the pull-down device in the auxiliary circuit 222 is an n-type transistor M.sub.PD2. For example, a first drain/source terminal of the n-type transistor M.sub.PD1 is connected with the data line DL.sub.1, a second drain/source terminal of the n-type transistor M.sub.PD1 is connected with the ground terminal, and the gate terminal of the n-type transistor M.sub.PD1 receives a reset signal R.sub.ST.

[0044] The time interval between the time point t.sub.1 and the time point to is the reset phase. In the reset phase, the reset signal R.sub.ST is switched from the low-level state to the high-level state, representing that the reset signal R.sub.ST is activated. Meanwhile, the n-type transistor M.sub.PD1 and the n-type transistor M.sub.PD2 are turned on. Consequently, the data lines DL.sub.1 and DL.sub.2 are discharged to the ground voltage. In other words, the ground voltage is the initial voltage.

[0045] After the reset phase, the time interval between the time point to and the time point t.sub.B is the charging phase. In the beginning of the charging phase, the charged voltages V.sub.DL1?V.sub.DL2 on the data lines DL.sub.1?DL.sub.2 start to rise from the initial voltage. The time interval between the time point t.sub.B and the time point t.sub.C is the sensing phase. In the charging phase and the sensing phase, the operations of the sense amplifiers 201 and 202 in the sensing circuit 230 are identical to those of FIGS. 2A and 2B, and not redundantly described herein.

[0046] FIG. 4A is a schematic circuit diagram illustrating a further exemplary sensing circuit used in the non-volatile memory of the present invention. FIG. 4B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 4A. In FIG. 4B, the time interval between the time point t.sub.1 and the time point t.sub.D is a read cycle. In the read cycle, a read cycle signal R.sub.CYCLE is in the high-level state. Moreover, the read cycle contains a pre-charge state, a reset phase, a charging phase and a sensing phase.

[0047] In comparison with the sensing circuit 130 shown in FIG. 2A, the sensing circuit 260 of this embodiment further comprises p auxiliary circuits. For succinctness, only two auxiliary circuits 251 and 252 are shown in FIG. 4A. In the sensing circuit 260 shown in FIG. 4A, the data lines DL.sub.1 and DL.sub.2 are respectively connected with the corresponding auxiliary circuits 251 and 252. Each of the auxiliary circuits 251 and 252 comprises a pull-down device and a pull-up device.

[0048] For example, the pull-down device in the auxiliary circuit 251 is an n-type transistor M.sub.PD1, and the pull-down device in the auxiliary circuit 252 is an n-type transistor M.sub.PD2. Moreover, the pull-up device in the auxiliary circuit 251 is a p-type transistor M.sub.PU1, and the pull-up device in the auxiliary circuit 252 is a p-type transistor M.sub.PU2. Take the auxiliary circuit 251 for example. A first drain/source terminal of the n-type transistor M.sub.PD1 is connected with the data line DL.sub.1, a second drain/source terminal of the n-type transistor M.sub.PD1 is connected with the ground terminal, and the gate terminal of the n-type transistor M.sub.PD1 receives a reset signal R.sub.ST. Moreover, a first drain/source terminal of the p-type transistor M.sub.PU1 is connected with the data line DL.sub.1, a second drain/source terminal of the p-type transistor M.sub.PU1 receives a supply voltage V.sub.DD, and the gate terminal of the p-type transistor M.sub.PU1 receives a pre-charge signal P.sub.RE.

[0049] The time interval between the time point t.sub.1 and the time point t.sub.2 is the pre-charge phase. In the pre-charge phase, the pre-charge signal P.sub.RE is switched from the high-level state to the low-level state, representing that the pre-charge signal P.sub.RE is activated. Meanwhile, the p-type transistor M.sub.PU1 and the p-type transistor M.sub.PU2 are turned on. Consequently, the data lines DL.sub.1 and DL.sub.2 are pre-charged to the supply voltage V.sub.DD.

[0050] The time interval between the time point t.sub.2 and the time point to is the reset phase. In the reset phase, the reset signal R.sub.ST is switched from the low-level state to the high-level state, representing that the reset signal R.sub.ST is activated. Meanwhile, the n-type transistor M.sub.PD1 and the n-type transistor M.sub.PD2 are turned on. Consequently, the data lines DL.sub.1 and DL.sub.2 are discharged to the ground voltage. In other words, the ground voltage is the initial voltage.

[0051] After the reset phase, the time interval between the time point to and the time point t.sub.B is the charging phase. In the beginning of the charging phase, the charged voltages V.sub.DL1?V.sub.DL2 on the data lines DL.sub.1?DL.sub.2 start to rise from the initial voltage. The time interval between the time point t.sub.B and the time point t.sub.C is the sensing phase. In the charging phase and the sensing phase, the operations of the sense amplifiers 201 and 202 in the sensing circuit 260 are identical to those of FIGS. 2A and 2B, and not redundantly described herein.

[0052] FIG. 5A is a schematic circuit diagram illustrating a sense amplifier according to a first embodiment of the present invention. The sense amplifier 500 is a latch type sense amplifier. As shown in FIG. 5A, the sense amplifier 500 comprises three transistors M.sub.P1, M.sub.P2, M.sub.P3 and a latching device 510. The latching device 510 comprises two transistors M.sub.N1 and M.sub.N2. The transistors M.sub.P1, M.sub.P2 and M.sub.P3 are p-type transistors. The transistors M.sub.N1 and M.sub.N2 are n-type transistors.

[0053] The first drain/source terminal of the transistor M.sub.P3 receives the supply voltage V.sub.DD. The gate terminal of the transistor M.sub.P3 receives an enable signal EN. The second drain/source terminal of the transistor M.sub.P3 is connected with a node n. The first drain/source terminal of the transistor M.sub.P1 is connected with the node n. The gate terminal of the transistor M.sub.P1 receives the reference voltage V.sub.REF. The second drain/source terminal of the transistor M.sub.P1 is connected with a node a. The first drain/source terminal of the transistor M.sub.P2 is connected with the node n. The gate terminal of the transistor M.sub.P2 is connected with the data line DL. The second drain/source terminal of the transistor M.sub.P2 is connected with a node b. The latching device 510 is connected with the node a and node b. The gate terminal of the transistor M.sub.P3 is an enable terminal of the sense amplifier 500. The gate terminal of the transistor M.sub.P1 is a first input terminal of the sense amplifier 500. The gate terminal of the transistor M.sub.P2 is a second input terminal of the sense amplifier 500.

[0054] The connecting relationship between the components of the latching device 510 will be described as follows. The first drain/source terminal of the transistor M.sub.N1 is connected with the node a. The gate terminal of the transistor M.sub.N1 is connected with the node b. The second drain/source terminal of the transistor M.sub.N1 receives a supply voltage V.sub.SS The first drain/source terminal of the transistor M.sub.N2 is connected with the node b. The gate terminal of the transistor M.sub.N2 is connected with the node a. The second drain/source terminal of the transistor M.sub.N2 receives the supply voltage V.sub.SS. Moreover, the node a is an output terminal of the sense amplifier 500. An output signal D.sub.O is outputted from the node a. The magnitude of the supply voltage V.sub.DD is higher than the magnitude of the supply voltage V.sub.SS. For example, the supply voltage V.sub.DD is 3.3.V, and the supply voltage V.sub.SS is a ground voltage (0V).

[0055] Generally, when the enable signal EN is in the high-level state, the transistor M.sub.P3 is turned off. Meanwhile, the sense amplifier 500 is disabled. Moreover, when the enable signal EN is in the low-level state, the transistor M.sub.P3 is turned on. Meanwhile, the sense amplifier 500 is enabled. Under this circumstance, the sense amplifier 500 generates the output signal D.sub.O according to the relationship between the charged voltage V.sub.DL on the data line DL and the reference voltage V.sub.REF.

[0056] For example, if the charged voltage V.sub.DL on the data line DL is lower than the reference voltage V.sub.REF, the transistor M.sub.P2 is turned on, the transistor M.sub.P1 is turned off, the transistor M.sub.N1 is turned on, and the transistor M.sub.N2 is turned off. Consequently, the output signal D.sub.O is the supply voltage V.sub.SS, indicating that the output signal D.sub.O has a first voltage level (e.g., a low voltage level). Whereas, if the charged voltage V.sub.DL on the data line DL is higher than the reference voltage V.sub.REF, the transistor M.sub.P2 is turned off, the transistor M.sub.P1 is turned on, the transistor M.sub.N1 is turned off, and the transistor M.sub.N2 is turned on. Consequently, the output signal D.sub.O is the supply voltage V.sub.DD, indicating that the output signal D.sub.O has a second voltage level (e.g., a high voltage level).

[0057] As mentioned above, the sense amplifier 500 of the first embodiment can be applied to the sensing circuit 130. That is, p sense amplifiers 500 are respectively connected with the p data lines DL.sub.1?DL.sub.p. In the sensing phase of the read cycle, the p output signals D.sub.O1?D.sub.Op are respectively generated according to the relationships between the reference voltage V.sub.REF and the charged voltages V.sub.DL1?V.sub.DLp on the data lines DL.sub.1?DL.sub.p. The p output signals D.sub.O1?D.sub.Op can be used to indicate the storing states of the p selected memory cells in the selected row.

[0058] FIG. 5B is a schematic circuit diagram illustrating a sense amplifier according to a second embodiment of the present invention. The sense amplifier 550 is a latch type sense amplifier. In comparison with the sense amplifier 500 of the first embodiment, the structure of the latching device 560 in the sense amplifier 500 of this embodiment is distinguished. For succinctness, only the relationship between the latching device 560 and associated components will be described as follows.

[0059] The latching device 560 comprises four transistors M.sub.P4, M.sub.P5, M.sub.N1 and M.sub.N2. The transistors M.sub.P4 and M.sub.P5 are p-type transistors, and the transistors M.sub.N1 and M.sub.N2 are n-type transistors. The connecting relationship between the components of the latching device 560 will be described as follows. The first drain/source terminal of the transistor M.sub.P4 is connected with the node a. The gate terminal of the transistor M.sub.P4 is connected with a node d. The second drain/source terminal of the transistor M.sub.P4 is connected with a node c. The first drain/source terminal of the transistor M.sub.P5 is connected with the node b. The gate terminal of the transistor M.sub.P5 is connected with a node c. The second drain/source terminal of the transistor M.sub.P5 is connected with the node d. The first drain/source terminal of the transistor M.sub.N1 is connected with the node c. The gate terminal of the transistor terminal M.sub.N1 is connected with the node d. The second drain/source terminal of the transistor M.sub.N1 receives the supply source V.sub.SS. The first drain/source terminal of the transistor M.sub.N2 is connected with the node d. The gate terminal of the transistor M.sub.N2 is connected with the node c. The second drain/source terminal of the transistor M.sub.N2 receives the supply voltage V.sub.SS. The node c is an output terminal of the sense amplifier 550. In addition, the output signal D.sub.O is outputted from the node c. Moreover, the magnitude of the supply voltage V.sub.DD is higher than the magnitude of the supply voltage V.sub.SS. For example, the supply voltage V.sub.DD is 3.3.V, and the supply voltage V.sub.SS is 0V.

[0060] Similarly, when the enable signal EN is in the high-level state, the transistor M.sub.P3 is turned off. Meanwhile, the sense amplifier 550 is disabled. Moreover, when the enable signal EN is in the low-level state, the transistor M.sub.P3 is turned on. Meanwhile, the sense amplifier 550 is enabled. Under this circumstance, the sense amplifier 550 generates the output signal D.sub.O according to the relationship between the charged voltage V.sub.DL on the data line DL and the reference voltage V.sub.REF.

[0061] For example, if the charged voltage V.sub.DL on the data line DL is lower than the reference voltage V.sub.REF, the transistor M.sub.P2 is turned on, the transistor M.sub.P5 is turned on, the transistor M.sub.P1 is turned off, the transistor M.sub.P4 is turned off, the transistor M.sub.N1 is turned on, and the transistor M.sub.N2 is turned off. Consequently, the output signal D.sub.O is the supply voltage V.sub.SS, indicating that the output signal D.sub.O has a first voltage level (e.g., a low voltage level). Whereas, if the charged voltage V.sub.DL on the data line DL is higher than the reference voltage V.sub.REF, the transistor M.sub.P2 is turned off, the transistor M.sub.P5 is turned off, the transistor M.sub.P1 is turned on, the transistor M.sub.P4 is turned on, the transistor M.sub.N1 is turned off, and the transistor M.sub.N2 is turned on. Consequently, the output signal D.sub.O is the supply voltage V.sub.DD, indicating that the output signal D.sub.O has a second voltage level (e.g., a high voltage level).

[0062] As mentioned above, the sense amplifier 550 of the second embodiment can be applied to the sensing circuit 130. That is, p sense amplifiers 550 are respectively connected with the p data lines DL.sub.1?DL.sub.p. In the sensing phase of the read cycle, the p output signals D.sub.O1?D.sub.Op are respectively generated according to the relationships between the reference voltage V.sub.REF and the charged voltages V.sub.DL1?V.sub.DLp on the data lines DL.sub.1?DL.sub.p. The p output signals D.sub.O1-D.sub.Op can be used to indicate the storing states of the p selected memory cells in the selected row.

[0063] In the two sense amplifiers 500 and 550, the first voltage level of the output signal D.sub.O is the low voltage level, and the second voltage level of the output signal D.sub.O is the high voltage level. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in a variant example, the node b of the sense amplifier 500 is the output terminal. Under this circumstance, the first level state of the output signal D.sub.O is the high voltage level, and the second level state of the output signal D.sub.O is the low voltage level. That is, the node b can be served as the output terminal of the sense amplifier 500. Similarly, in a variant example, the node d of the sense amplifier 550 is the output terminal. Under this circumstance, the first level state of the output signal D.sub.O is the high voltage level, and the second level state of the output signal D.sub.O is the low voltage level. That is, the node d can be served as the output terminal of the sense amplifier 550.

[0064] Alternatively, the node a and the node b are used as two output terminals of the sense amplifier 500. Moreover, the node a and the node b generate complementary output signals. Similarly, the node c and the node d are used as two output terminals of the sense amplifier 550. Moreover, the node c and the node d generate complementary output signals.

[0065] FIG. 6A is a schematic circuit diagram illustrating a sensing circuit with sense amplifiers of the first embodiment. FIG. 6B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 6A. As shown in FIG. 6A, the sensing circuit comprises p sense amplifiers 601?60p. The circuitry structure of each of the p sense amplifiers 601?60p is identical to the circuitry structure of the sense amplifier of the first embodiment.

[0066] The first input terminals of the p sense amplifiers 601?60p receive a reference voltage V.sub.REF. The second input terminals of the p sense amplifiers 601?60p are respectively connected with the corresponding p data lines DL.sub.1?DL.sub.p. The enable terminals of the p sense amplifiers 601?60p receives an enable signal EN. The output terminals of the sense amplifiers 601?60p respectively generate output signals D.sub.O1?D.sub.Op.

[0067] As shown in FIG. 6A, the first input terminals of the p sense amplifiers 601?60p receive the reference voltage V.sub.REF. Consequently, the reference voltage V.sub.REF is a global signal. Moreover, since the second input terminals of the p sense amplifiers 601?60p are respectively connected with the corresponding p data lines DL.sub.1?DL.sub.p, the signals on the data lines DL.sub.1?DL.sub.p are local signals.

[0068] Please refer to FIG. 6B. At the time point t.sub.A, the enable signal EN is switched from the high-level state to the low-level state, indicating that the charging phase is changed to the sensing phase. Meanwhile, the transistors M.sub.P3 in the sense amplifiers 601?60p are turned on. Consequently, the voltage at the node n quickly rises to the supply voltage V.sub.DD. Since the voltage at the node n rises quickly, a capacitive coupling effect is generated. Due to the capacitive coupling effect, the rising voltage at the node n is coupled to the data lines DL.sub.1?DL.sub.p and the reference voltage V.sub.REF. Consequently, the data lines DL.sub.1?DL.sub.p and the reference voltage V.sub.REF are suffered from signal disturbance. The signal disturbance may result in misjudgment of the sense amplifiers 601?60p. The reason will be described as follows.

[0069] Please refer to FIG. 6B again. At the time point t.sub.A, the charging phase is changed to the sensing phase. Since the reference voltage V.sub.REF is the global signal, the capacitive coupling effect becomes stronger. Under this circumstance, a larger couple voltage of positive polarity is generated. At the time point t.sub.B, the couple voltage (?V) of positive polarity is approximately 60 mV. In other words, the reference voltage V.sub.REF rises from 100 mV to about 160 mV.

[0070] Moreover, the changes of the voltages on the data lines DL.sub.1?DL.sub.p may be classified into two situations. In the first situation, the selected memory cell is in the first storing state, and the generated cell current is very low (i.e., nearly zero). In the second situation, selected memory cell is in the second storing state, and the generated cell current is relatively higher.

[0071] Please refer to the curve (I) as shown in FIG. 6B. If the cell current received by the data line is very low (i.e., nearly zero), the charged voltage on the data line rises at a slower rate. At the time point t.sub.A when the changing phase is switched to the sensing phase, the charged voltage is nearly zero. Moreover, since the signal on the data line DL is a local signal, the capacitive coupling effect is weaker. Under this circumstance, a smaller couple voltage of positive polarity is generated. At the time point t.sub.B, the couple voltage (?V) of positive polarity is approximately 20 mV. In other words, the charged voltage on the data line rises from 0 mV to about 20 mV. In the sensing phase, the reference voltage V.sub.REF is about 160 mV, and the charged voltage on the data line DL is about 20 mV. In other words, the reference voltage V.sub.REF is higher than the charged voltage on the data line DL. Consequently, the output signal from the sense amplifier has the first voltage level, indicating that the selected memory cell is in the first storing state.

[0072] Please refer to the curve (II) as shown in FIG. 6B. If the cell current received by the data line is relatively higher, the charged voltage on the data line rises continuously. At the time point to when the changing phase is switched to the sensing phase, the charged voltage is about 130 mV. At the time point t.sub.B, the couple voltage (?V) of positive polarity is approximately 20 mV. In other words, the charged voltage on the data line DL rises from 130 mV to about 150 mV. In the sensing phase, the reference voltage V.sub.REF is about 160 mV, and the charged voltage on the data line is about 150 mV. In other words, the reference voltage V.sub.REF is higher than the charged voltage on the data line DL. Consequently, the output signal from the sense amplifier has the first voltage level, indicating that the selected memory cell is in the first storing state. Actually, the selected memory cell should be in the second storing state. However, the sense amplifier misjudges that the selected memory cell is in the first storing state.

[0073] As mentioned above, at the moment when the operating phase of the sense amplifier is switched from the charging phase to the sensing phase, the voltage at the node n rises quickly, and thus the capacitive coupling effect is generated. Moreover, since the voltage at the node n rises, two couple voltages are generated and respectively coupled to the two input terminals of the sense amplifier. For example, the first couple voltage is coupled to the reference voltage V.sub.REF, and the second couple voltage is coupled to the data line DL. Since the reference voltage V.sub.REF and the charged voltage on the data line increase, the misjudgment of the sense amplifier occurs. Similarly, the sensing circuit with the sense amplifiers 550 of the second embodiment also the above problems. When the charging phase is switched to the sensing phase, the signal disturbance occurs. The signal disturbance may result in misjudgment of the sense amplifier.

[0074] In order to overcome the above drawbacks, the circuitry structure of the sense amplifier needs to be modified. For example, in another embodiment, the sense amplifier is additionally equipped with two anti-couple devices for compensating the signal disturbance at the two input terminals of the sense amplifier. For example, the anti-couple devices are capacitors.

[0075] FIG. 7A is a schematic circuit diagram illustrating a sense amplifier according to a third embodiment of the present invention. The sense amplifier 700 is a latch type sense amplifier. The sense amplifier 700 comprises three transistors M.sub.P1, M.sub.P2, M.sub.P3, a latching device 510 and two capacitors C.sub.a1, C.sub.a2.

[0076] In comparison with the sense amplifier 500 of the first embodiment, the sense amplifier 700 of this embodiment further comprises the two capacitors C.sub.a1 and C.sub.a2. The first terminal of the capacitor C.sub.a1 is connected with the gate terminal of the transistor M.sub.P3. The second terminal of the capacitor C.sub.a1 is connected with the gate terminal of the transistor M.sub.P1. The first terminal of the capacitor C.sub.a2 is connected with the gate terminal of the transistor M.sub.P3. The second terminal of the capacitor C.sub.a2 is connected with the gate terminal of the transistor M.sub.P2.

[0077] FIG. 7B is a schematic circuit diagram illustrating a sense amplifier according to a fourth embodiment of the present invention. The sense amplifier 750 is a latch type sense amplifier. The sense amplifier 750 comprises three transistors M.sub.P1, M.sub.P2, M.sub.P3, a latching device 560 and two capacitors C.sub.a1, C.sub.a2.

[0078] In comparison with the sense amplifier 550 of the second embodiment, the sense amplifier 750 further comprises the two capacitors C.sub.a1 and C.sub.a2. The first terminal of the capacitor C.sub.a1 is connected with the gate terminal of the transistor M.sub.P3. The second terminal of the capacitor C.sub.a1 is connected with the gate terminal of the transistor M.sub.P1. The first terminal of the capacitor C.sub.a2 is connected with the gate terminal of the transistor M.sub.P3. The second terminal of the capacitor C.sub.a2 is connected with the gate terminal of the transistor M.sub.P2.

[0079] The operations of the sense amplifier 700 of the third embodiment are similar to the operations of the sense amplifier 500 of the first embodiment. The operations of the sense amplifier 750 of the fourth embodiment are similar to the operations of the sense amplifier 550 of the second embodiment. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in a variant example, the node b of the sense amplifier 700 is the output terminal. In another variant example, the node a and the node b are used as two output terminals of the sense amplifier 700 for generating complementary output signals. Similarly, in a variant example, the node b of the sense amplifier 750 is the output terminal. In another variant example, the node c and the node d are used as two output terminals of the sense amplifier 750 for generating complementary output signals.

[0080] In the third and fourth embodiments, the anti-couple devices receive the enable signal EN. Moreover, the enable signal EN is activated when the enable signal EN is switched from the high-level state to the low-level state. Consequently, the two input terminals of the sense amplifier generate a couple voltage of negative polarity to compensate the couple voltage of positive polarity. In other words, the signal disturbance at the two input terminals of the sense amplifiers 700 and 750 will be reduced. Consequently, the probability of causing misjudgment of the sense amplifiers 700 and 750 will be reduced.

[0081] Take the sense amplifier 700 of the third embodiment for example. When the enable single EN of the sense amplifier 700 is activated, the transistor M.sub.P3 is turned on. Consequently, the voltage at the node n changes quickly (i.e., rises quickly), and the capacitive coupling effect is generated. Since the voltage at the node n rises, two couple voltages of positive polarity are generated. The two couple voltages of positive polarity are respectively coupled to the two input terminals of the sense amplifier. When the enable signal EN is switched from the high-level state to the low-level state, the enable signal EN is activated. Consequently, two couple voltages of negative polarity are generated and respectively coupled to the two input terminals of the sense amplifier through the two capacitors C.sub.a1 and C.sub.a2. The couple voltages of the positive polarity and the corresponding couple voltages of negative polarity are offset by each other. Consequently, the signal disturbance at the two input terminals of the sense amplifiers 700 will be reduced.

[0082] For example, since the voltage at the node n rises, first and second couple voltages of positive polarity are generated. The first couple voltage of positive polarity is coupled to the first input terminal of the sense amplifier 700. The second couple voltage of positive polarity is coupled to the second input terminal of the sense amplifier 700. Similarly, when the enable signal EN is switched from the high-level state to the low-level state, the enable signal EN is activated. Consequently, third and fourth couple voltages of negative polarity are generated. The third couple voltage is coupled to the first input terminal of the sense amplifier 700. The fourth couple voltage is coupled to the second input terminal of the sense amplifier 700. Since the first couple voltage and the third couple voltage are offset by each other, the signal disturbance at the first input terminal of the sense amplifiers 700 is reduced. Moreover, since the second couple voltage and the fourth couple voltage are offset by each other, the signal disturbance at the second input terminal of the sense amplifier 700 is reduced.

[0083] FIG. 8A is a schematic circuit diagram illustrating a sensing circuit with sense amplifiers of the third embodiment. FIG. 8B is a schematic timing waveform diagram illustrating associated signals of the sensing circuit as shown in FIG. 8A. As shown in FIG. 8A, the sensing circuit comprises p sense amplifiers 801?80p. The circuitry structure of each of the p sense amplifiers 801?80p is identical to the circuitry structure of the sense amplifier of the third embodiment.

[0084] The first input terminals of the p sense amplifiers 801?80p receive a reference voltage V.sub.REF. The second input terminals of the p sense amplifiers 801?80p are respectively connected with the corresponding p data lines DL1-DL p. The enable terminals of the p sense amplifiers 801?80p receive an enable signal EN. The output terminals of the sense amplifiers 801?80p respectively generate output signals D.sub.O1?D.sub.Op.

[0085] Please refer to FIG. 8B. At the time point t.sub.A, the charging phase is changed to the sensing phase. Each of the p sense amplifiers 801?80p comprises the capacitors C.sub.a1 and C.sub.a2. Due to the arrangement of the capacitors C.sub.a1 and C.sub.a2, the signal disturbance at the two input terminals of each of the sense amplifiers 801?80p will be reduced. Consequently, at the time point t.sub.A, the offset couple voltage (?V) is approximately equal to 0 mV. In other words, the reference voltage V.sub.REF nearly doesn't drop and maintains at nearly 100 mV.

[0086] Moreover, the changes of the voltages on the data lines DL.sub.1?DL.sub.p may be classified into two situations. In the first situation, the selected memory cell is in the first storing state, and the generated cell current is very low (i.e., nearly zero). In the second situation, selected memory cell is in the second storing state, and the generated cell current is relatively higher.

[0087] Please refer to the curve (I) as shown in FIG. 8B. If the cell current received by the data line is very low (i.e., nearly zero), the charged voltage on the data line rises at a slower rate. At the time point t.sub.A when the changing phase is switched to the sensing phase, the charged voltage is nearly zero. At the time point t.sub.B, the offset couple voltage (?V) is approximately 2 mV. In other words, the charged voltage on the data line rises from 0 mV to about 2 mV. In the sensing phase, the reference voltage V.sub.REF is about 100 mV, and the charged voltage on the data line is about 2 mV. In other words, the reference voltage V.sub.REF is higher than the charged voltage on the data line. Consequently, the output signal from the sense amplifier has the first voltage level, indicating that the selected memory cell is in the first storing state.

[0088] Please refer to the curve (II) as shown in FIG. 8B. If the cell current received by the data line is relatively higher, the charged voltage on the data line rises continuously. At the time point t.sub.A when the changing phase is switched to the sensing phase, the charged voltage is about 130 mV. At the time point t.sub.B, the offset couple voltage (?V) is approximately 2 mV. In other words, the charged voltage on the data line rises from 130 mV to about 132 mV. In the sensing phase, the reference voltage V.sub.REF is about 100 mV, and the charged voltage on the data line is about 132 mV. In other words, the reference voltage V.sub.REF is lower than the charged voltage on the data line. Consequently, the output signal from the sense amplifier has the second voltage level, indicating that the selected memory cell is in the second storing state. Obviously, the sense amplifier judges correctly that the selected memory cell is in the second storing state.

[0089] Likewise, the sensing circuit with the sense amplifiers 750 of the fourth embodiment can largely reduce the probability of causing misjudgment. Moreover, in the sensing circuit of FIG. 8A, p capacitors C.sub.a1 are connected between the enable terminals and the first input terminals of the p sense amplifiers 801?80p in parallel. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, the number of capacitors connected between the enable terminals and the first input terminals of the p sense amplifiers 801?80p in parallel is not restricted. In a variant example, a single capacitor is connected between the enable terminals and the first input terminals of the p sense amplifiers 801?80p. In this case, the capacitance of the single capacitor is equal to the total of the capacitances of the p capacitors C.sub.a1.

[0090] In the above embodiments, the anti-couple devices are the capacitors C.sub.a1 and C.sub.a2. For example, the capacitors C.sub.a1 and C.sub.a2 are plate capacitors. Alternatively, the capacitors C.sub.a1 and C.sub.a2 are defined by n-type transistors or the p-type transistors. FIGS. 9A and 9B schematically illustrate two other possible examples of the anti-couple devices used in the sense amplifier of the present invention.

[0091] As shown in FIG. 9A, the anti-couple device comprises an n-type transistor M.sub.NC. The n-type transistor M.sub.NC is connected to be formed as a MOS capacitor. The gate terminal of the n-type transistor M.sub.NC is the first terminal of the MOS capacitor. The two drain/source terminals of the n-type transistor M.sub.NC are connected with each other and served as the second terminal of the MOS capacitor. In a variant example, the gate terminal of the n-type transistor M.sub.NC is the second terminal of the MOS capacitor, and the two drain/source terminals of the n-type transistor M.sub.NC are connected with each other and served as the first terminal of the MOS capacitor.

[0092] As shown in FIG. 9B, the anti-couple device comprises a p-type transistor M.sub.PC. The p-type transistor M.sub.PC is connected to be formed as a MOS capacitor.

[0093] The gate terminal of the p-type transistor M.sub.PC is the first terminal of the MOS capacitor. The two drain/source terminals of the p-type transistor M.sub.PC are connected with each other and served as the second terminal of the MOS capacitor. In a variant example, the gate terminal of the p-type transistor M.sub.PC is the second terminal of the MOS capacitor, and the two drain/source terminals are connected with each other and served as the first terminal of the MOS capacitor.

[0094] By adjusting the size of the p-type transistor M.sub.PC or the n-type transistor M.sub.NC, the capacitance of the MOS capacitor is correspondingly adjusted. Consequently, the voltage coupling ratio is adjusted. In this way, the signal disturbance at the two input terminals of the sense amplifier will be reduced.

[0095] In the above embodiments, the enable signal EN is activated when the enable signal EN is switched from the high-level state to the low-level state. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, the enable signal EN is activated when the enable signal EN is switched from the low-level state to the high-level state. According to characteristics of the enable signal EN, some other embodiments of the sense amplifier can be designed.

[0096] FIG. 10A is a schematic circuit diagram illustrating a sense amplifier according to a fifth embodiment of the present invention. The sense amplifier 900 is a latch type sense amplifier.

[0097] The sense amplifier 900 comprises three transistors M.sub.N1, M.sub.N2, M.sub.N3, two capacitors C.sub.b1, C.sub.b2 and a latching device 910. The latching device 910 comprises two transistors M.sub.P1 and M.sub.P2. The transistors M.sub.N1, M.sub.N2, M.sub.N3 are n-type transistors, and the transistors M.sub.P1, M.sub.P2 are p-type transistors.

[0098] The first drain/source terminal of the first transistor M.sub.N3 receives a supply voltage V.sub.SS. The gate terminal of the transistor M.sub.N3 receives an enable signal EN. The second drain/source terminal of the transistor M.sub.N3 is connected with a node m. The first drain/source terminal of the transistor M.sub.N1 is connected with the node m. The gate terminal of the transistor M.sub.N1 receives the reference voltage V.sub.REF. The second drain/source terminal of the transistor M.sub.N1 is connected with a node a. The first drain/source terminal of the transistor M.sub.N2 is connected with the node m. The gate terminal of the transistor M.sub.N2 is connected with a data line DL. The second drain/source terminal of the transistor M.sub.N2 is connected with a node b. The latching device 910 is connected with the node a and the node b. The gate terminal of the transistor M.sub.N3 is an enable terminal of the sense amplifier 900. The gate terminal of the transistor M.sub.N1 is the first input terminal of the sense amplifier 900. The gate terminal of the transistor M.sub.N2 is the second input terminal of the sense amplifier 900.

[0099] The first terminal of the capacitor C.sub.b1 is connected with the gate terminal of the transistor M.sub.N3. The second terminal of the capacitor C.sub.b1 is connected with the gate terminal of the transistor M.sub.N1. The first terminal of the capacitor C.sub.b2 is connected with the gate terminal of the transistor M.sub.N3. The second terminal of the capacitor C.sub.b2 is connected with the gate terminal of the transistor M.sub.N2.

[0100] In the latching device 910, the first drain/source terminal of the transistor M.sub.P1 is connected with the node a. The gate terminal of the transistor M.sub.P1 is connected with the node b. The second drain/source terminal of the transistor M.sub.P1 receives a supply voltage V.sub.DD. The first drain/source terminal of the transistor M.sub.P2 is connected with the node b. The gate terminal of the transistor M.sub.P2 is connected with the node a. The second drain/source terminal of the transistor M.sub.P2 receives the supply voltage V.sub.DD. The node a is the output terminal of the sense amplifier 900 to generate the output signal D.sub.O. The supply voltage V.sub.DD is higher than the supply voltage V.sub.SS. For example, the supply voltage V.sub.DD is 3.3V, and the supply voltage V.sub.SS is a ground voltage (0V).

[0101] Generally, when the enable signal EN is in the low-level state, the transistor M.sub.N3 is turned off. Meanwhile, the sense amplifier 900 is disabled. Moreover, when the enable signal EN is in the high-level state, the transistor M.sub.N3 is turned on. Meanwhile, the sense amplifier 900 is enabled. Under this circumstance, the sense amplifier 900 generates the output signal D.sub.O according to the relationship between the charged voltage V.sub.DL on the data line DL and the reference voltage V.sub.REF.

[0102] For example, if the charged voltage V.sub.DL on the data line DL is lower than the reference voltage V.sub.REF, the transistor M.sub.N2 is turned off, the transistor M.sub.N1 is turned on, the transistor M.sub.P1 is turned off, and the transistor M.sub.P2 is turned on. Consequently, the output signal D.sub.O is the supply voltage V.sub.SS, indicating that the output signal D.sub.O has a first voltage level (e.g., a low voltage level). Whereas, if the charged voltage V.sub.DL on the data line DL is higher than the reference voltage V.sub.REF, the transistor M.sub.N2 is turned on, the transistor M.sub.N1 is turned off, the transistor M.sub.P1 is turned on, and the transistor M.sub.P2 is turned off. Consequently, the output signal D.sub.O is the supply voltage V.sub.DD, indicating that the output signal D.sub.O has a second voltage level (e.g., a high voltage level).

[0103] As mentioned above, the sense amplifier 900 of the fifth embodiment can be applied to the sensing circuit. That is, p sense amplifiers 900 are respectively connected with the p data lines DL.sub.1?DL.sub.p. In the sensing phase of the read cycle, the p output signals D.sub.O1?D.sub.Op are respectively generated according to the relationships between the reference voltage V.sub.REF and the charged voltages V.sub.DL1?V.sub.DLp on the data lines DL.sub.1?DL.sub.p. The p output signals D.sub.O1?D.sub.Op can be used to indicate the storing states of the p selected memory cells in the selected row.

[0104] FIG. 10B is a schematic circuit diagram illustrating a sense amplifier according to a sixth embodiment of the present invention. The sense amplifier 950 is a latch type sense amplifier. In comparison with the sense amplifier 900 of the fifth embodiment, the structure of the latching device 960 in the sense amplifier 950 of this embodiment is distinguished. For succinctness, only the relationship between the latching device 960 and associated components will be described as follows.

[0105] The latching device 960 comprises four transistors M.sub.N4, M.sub.N5, M.sub.P1 and M.sub.P2. The transistors M.sub.N4 and M.sub.N5 are n-type transistors, and the transistors M.sub.P1 and M.sub.P2 are p-type transistors. In the latching device 960, the first drain/source terminal of the transistor M.sub.N4 is connected with the node a. The gate terminal of the transistor M.sub.N4 is connected with a node d. The second drain/source terminal of the transistor M.sub.N4 is connected with a node c. The first drain/source terminal of the transistor M.sub.N5 is connected with the node b. The gate terminal of the transistor M.sub.N5 is connected with the node c. The second drain/source terminal of the transistor M.sub.N5 is connected with the node d. The first drain/source terminal of the transistor M.sub.P1 is connected with the node c. The gate terminal of the transistor M.sub.P1 is connected with the node d. The second drain/source terminal of the transistor M.sub.P1 receives the supply voltage V.sub.DD. The first drain/source terminal of the transistor M.sub.P2 is connected with the node d. The gate terminal of the transistor M.sub.P2 is connected with the node c. The second drain/source terminal of the transistor M.sub.P2 receives the supply voltage V.sub.DD. The node c is an output terminal of the sense amplifier 950 to generate the output signal D.sub.O. Moreover, the magnitude of the supply voltage V.sub.DD is higher than the magnitude of the supply voltage V.sub.SS. For example, the supply voltage V.sub.DD is 3.3.V, and the supply voltage V.sub.SS is 0V.

[0106] Similarly, when the enable signal EN is in the low-level state, the transistor M.sub.N3 is turned off. Meanwhile, the sense amplifier 950 is disabled. Moreover, when the enable signal EN is in the high-level state, the transistor M.sub.N3 is turned on. Meanwhile, the sense amplifier 950 is enabled. Under this circumstance, the sense amplifier 950 generates the output signal D.sub.O according to the relationship between the charged voltage V.sub.DL on the data line DL and the reference voltage V.sub.REF.

[0107] For example, if the charged voltage V.sub.DL on the data line DL is lower than the reference voltage V.sub.REF, the transistor M.sub.N2 is turned off, the transistor M.sub.N5 is turned off, the transistor M.sub.N1 is turned on, the transistor M.sub.N4 is turned on, the transistor M.sub.P1 is turned off, and the transistor M.sub.P2 is turned on. Consequently, the output signal D.sub.O is the supply voltage V.sub.SS, indicating that the output signal D.sub.O has a first voltage level (e.g., a low voltage level). Whereas, if the charged voltage V.sub.DL on the data line DL is higher than the reference voltage V.sub.REF, the transistor M.sub.N2 is turned on, the transistor M.sub.N5 is turned on, the transistor M.sub.N1 is turned off, the transistor M.sub.N4 is turned off, the transistor M.sub.P1 is turned on, and the transistor M.sub.P2 is turned off. Consequently, the output signal D.sub.O is the supply voltage V.sub.DD, indicating that the output signal D.sub.O has a second voltage level (e.g., a high voltage level).

[0108] As mentioned above, the sense amplifier 950 of the sixth embodiment can be applied to the sensing circuit. That is, p sense amplifiers 950 are respectively connected with the p data lines DL.sub.1?DL.sub.p. In the sensing phase of the read cycle, the p output signals D.sub.O1?D.sub.Op are respectively generated according to the relationships between the reference voltage V.sub.REF and the charged voltages V.sub.DL1?V.sub.DLp on the data lines DL.sub.1?DL.sub.p. The p output signals D.sub.O1?D.sub.Op can be used to indicate the storing states of the p selected memory cells in the selected row.

[0109] Moreover, in the fifth embodiment and the sixth embodiment, each of the sense amplifiers 900 and 950 further comprises two capacitors C.sub.b1 and C.sub.b1. When the enabled single EN is activated, the transistor M.sub.N3 is turned on. Consequently, the voltage at the node m changes quickly (i.e., drops quickly), and the capacitive coupling effect is generated. Since the voltage at the node m drops, two couple voltages of negative polarity are generated. The two couple voltages of negative polarity are respectively coupled to the data line DL and the reference voltage V.sub.REF. Consequently, the voltage on the data line DL and the reference voltage V.sub.REF are decreased. When the enable signal EN is switched from the low-level state to the high-level state, the enable signal EN is activated. Consequently, two couple voltages of positive polarity are generated. In addition, the two couple voltages of positive polarity are respectively coupled to the data line DL and the reference voltage V.sub.REF through the two capacitors C.sub.b1 and C.sub.b1. The couple voltages of the positive polarity and the corresponding couple voltages of negative polarity are offset by each other. Consequently, the signal disturbance at the two input terminals of the sense amplifiers 900 will be reduced.

[0110] Of course, the sense amplifier in each of the above embodiments is further connected with an auxiliary circuit. For example, the auxiliary circuit has the circuitry structure of the auxiliary circuit 221 shown in FIG. 3A or the circuitry structure of the auxiliary circuit 251 shown in FIG. 4A. In the reset phase, the voltage at the data line is maintained in the initial voltage under control of the auxiliary circuit. At the moment when the reset phase is changed to the charging phase, the charged voltage on the data line starts to rise from the initial voltage.

[0111] While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.