NON-VOLATILE MEMORY AND REFERENCE CURRENT GENERATOR THEREOF

Abstract

A non-volatile memory receives a supply voltage. The non-volatile memory includes a reference current generator and a sensing circuit. The reference current generator provides a reference current to the sensing circuit. The reference current generator includes a control voltage generation circuit, a current path selecting circuit and a mirroring circuit. The control voltage generation circuit receives a control signal and generates a control voltage according to the control signal. The current path selecting circuit generates the reference current. A current input terminal of the mirroring circuit receives the reference current. If the control signal is set as a first value, the reference current is changed at a first slope in a range of the supply voltage. If the control signal is set as a second value, the reference current is changed at a second slope in the range of the supply voltage.

Claims

1. A non-volatile memory, comprising: a memory module comprising plural data lines; a sensing circuit coupled to the plural data lines of the memory module, wherein a first sense amplifier of the sensing circuit is coupled to a first data line of the plural data lines; and a reference current generator receiving a supply voltage, wherein the reference current generator provides a reference current to the sensing circuit, and the reference current generator comprises: a control voltage generation circuit receiving a control signal and generating a control voltage according to the control signal; a first current path selecting circuit receiving a selection signal and the control voltage, wherein the first current path selecting circuit generates the reference current according to the control voltage and the selection signal; and a mirroring circuit, wherein a current input terminal of the mirroring circuit receives the reference current, and a current mirroring terminal of the mirroring circuit is connected with the first sense amplifier, wherein in a first read cycle, the first sense amplifier determines a storage state of a selected memory cell according to a cell current in the first data line and the reference current, wherein if the control signal is set as a first value, the reference current is changed at a first slope in a range of the supply voltage, wherein if the control signal is set as a second value, the reference current is changed at a second slope in the range of the supply voltage.

2. The non-volatile memory as claimed in claim 1, wherein the first current path selecting circuit comprises a first current path, and the first current path comprises a first voltage-controlled current source and a first switch, which are serially connected between the current input terminal of the mirroring circuit and a ground terminal, wherein the first switch is selectively in a close state or an open state according to a first selection bit of the selection signal, and the first voltage-controlled current source generates a first voltage-controlled current according to the control voltage, wherein when the first switch is in the close state, the reference current is equal to the first voltage-controlled current.

3. The non-volatile memory as claimed in claim 1, wherein the first current path selecting circuit comprises: a first current path comprising a first voltage-controlled current source and a first switch, which are serially connected between the current input terminal of the mirroring circuit and a ground terminal; and a second current path comprising a second voltage-controlled current source and a second switch, which are serially connected between the current input terminal of the mirroring circuit and the ground terminal, wherein the first switch is selectively in a close state or an open state according to a first selection bit of the selection signal, the second switch is selectively in the close state or the open state according to a second selection bit of the selection signal, the first voltage-controlled current source generates a first voltage-controlled current according to the control voltage, and the second voltage-controlled current source generates a second voltage-controlled current according to the control voltage, wherein at least one of the first switch and the second switch is in the close state.

4. The non-volatile memory as claimed in claim 1, wherein the first current path selecting circuit comprises a first current path, and the first current path comprises: a first transistor, wherein a first drain/source terminal of the first transistor is connected with the current input terminal of the mirroring circuit, and a gate terminal of the first transistor receives the control voltage; and a second transistor, wherein a first drain/source terminal of the second transistor is connected with a second drain/source terminal of the first transistor, a gate terminal of the second transistor receives a first selection bit of the selection signal, and a second drain/source terminal of the second transistor is connected with a ground terminal, wherein when the second transistor is in an on state according to the first selection bit of the selection signal, the first transistor generates a first voltage-controlled current according to the control voltage.

5. The non-volatile memory as claimed in claim 1, wherein the first current path selecting circuit comprises a first current path and a second current path, wherein the first current path comprises: a first transistor, wherein a first drain/source terminal of the first transistor is connected with the current input terminal of the mirroring circuit, and a gate terminal of the first transistor receives the control voltage; and a second transistor, wherein a first drain/source terminal of the second transistor is connected with a second drain/source terminal of the first transistor, a gate terminal of the second transistor receives a first selection bit of the selection signal, and a second drain/source terminal of the second transistor is connected with a ground terminal, wherein the second current path comprises: a third transistor, wherein a first drain/source terminal of the third transistor is connected with the current input terminal of the mirroring circuit, and a gate terminal of the third transistor receives the control voltage; a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the current input terminal of the mirroring circuit, a gate terminal of the fourth transistor receives the control voltage, and a second drain/source terminal of the fourth transistor is connected with a second drain/source terminal of the third transistor; and a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with the second drain/source terminal of the fourth transistor, a gate terminal of the fifth transistor receives a second selection bit of the selection signal, and a second drain/source terminal of the fifth transistor is connected with the ground terminal, wherein the second transistor is selectively in an on state or an off state according to the first selection bit of the selection signal, the fifth transistor is selectively in the on state or the off state according to the second selection bit of the selection signal, the first transistor generates a first voltage-controlled current according to the control voltage, and the third transistor and the fourth transistor generate a second voltage-controlled current according to the control voltage, wherein at least one of the second transistor and the fifth transistor is in the on state.

6. The non-volatile memory as claimed in claim 1, wherein the control voltage generation circuit comprises: a first bias circuit connected between the supply voltage and a ground terminal, wherein the first bias circuit generates a first bias voltage; a second current path selecting circuit connected between the supply voltage and a first node, wherein the second current path selecting circuit receives the control signal and the first bias voltage, and generates a first current according to the supply voltage and the control signal; a second bias circuit connected between the first node and the ground terminal, wherein the second bias circuit generates a second bias voltage and provides the second bias voltage to the first node; a first resistor connected between the first node and a second node, wherein a voltage at the second node is the control voltage; and a first transistor, wherein a first drain/source terminal of the first transistor is connected with the second node, a gate terminal of the first transistor is connected with the second node, and a second drain/source terminal of the first transistor is connected with the ground terminal.

7. The non-volatile memory as claimed in claim 6, wherein the first resistor is implemented by a second transistor, wherein a first drain/source terminal of the second transistor is connected with the first node, a gate terminal of the second transistor is connected with the ground terminal, and a second drain/source terminal of the second transistor is connected with the second node.

8. The non-volatile memory as claimed in claim 7, wherein the control voltage generation circuit further comprises a third current path selecting circuit, which is connected between the supply voltage and the second node, wherein the third current path selecting circuit receives the control signal, and the third current path selecting circuit generates a second current according to the supply voltage and the control signal.

9. The non-volatile memory as claimed in claim 8, wherein the third current path selecting circuit comprises: a first current path comprising a second resistor and a first switch, which are serially connected between the supply voltage and the second node; and a second current path comprising a third resistor and a second switch, which are serially connected between the supply voltage and the second node, wherein the first switch is selectively in a close state or an open state according to a first control bit of the control signal, and the second switch is selectively in the close state or the open state according to a second control bit of the control signal.

10. The non-volatile memory as claimed in claim 8, wherein the third current path selecting circuit comprises: a second transistor, wherein a first drain/source terminal of the second transistor receives the supply voltage, a gate terminal of the second transistor receives a first control bit of the control signal, and a second drain/source terminal of the second transistor is connected with the node; a third transistor, wherein a first drain/source terminal of the third transistor receives the supply voltage, and a gate terminal of the third transistor receives a second control bit of the control signal; and a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with a second drain/source terminal of the third transistor, a gate terminal of the fourth transistor receives the second node, and a second drain/source terminal of the fourth transistor is connected with the second node, wherein the second transistor is in an on state or an off state according to the first control bit of the control signal, and the third transistor is in the on state or the off state according to the second control bit of the control signal.

11. The non-volatile memory as claimed in claim 6, wherein the second current path selecting circuit comprises: a first current path comprising a first voltage-controlled current source and a first switch, which are serially connected between the supply voltage and the first node; and a second current path comprising a second voltage-controlled current source and a second switch, which are serially connected between the supply voltage and the first node, wherein the first switch is selectively in a close state or an open state according to a first control bit of the control signal, the second switch is selectively in the close state or the open state according to a second control bit of the control signal, the first voltage-controlled current source generates a first voltage-controlled current according to the first bias voltage, and the second voltage-controlled current source generates a second voltage-controlled current according to the first bias voltage, wherein at least one of the first switch and the second switch is in the close state.

12. The non-volatile memory as claimed in claim 6, wherein the second current path selecting circuit comprises a first current path and a second current path, wherein the first current path comprises: a second transistor, wherein a first drain/source terminal of the second transistor receives the supply voltage, and a gate terminal of the second transistor receives a first control bit of the control signal; and a third transistor, wherein a first drain/source terminal of the third transistor is connected with a second drain/source terminal of the second transistor, a gate terminal of the third transistor receives the first bias voltage, and a second drain/source terminal of the third transistor is connected with the first node, wherein the second current path comprises: a fourth transistor, wherein a first drain/source terminal of the fourth transistor receives the supply voltage, and a gate terminal of the fourth transistor receives a second control bit of the control signal; a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with a second drain/source terminal of the fourth transistor, a gate terminal of the fifth transistor receives the first bias voltage, and a second drain/source terminal of the fifth transistor is connected with the first node, wherein the second transistor is selectively in an on state or an off state according to the first control bit of the control signal, the fourth transistor is selectively in the on state or the off state according to the second control bit of the control signal, the third transistor generates a first voltage-controlled current according to the first bias voltage, and the fifth transistor generates a second voltage-controlled current according to the first bias voltage, wherein at least one of the second transistor and the fourth transistor is in the on state.

13. The non-volatile memory as claimed in claim 6, wherein the first bias circuit comprises: a second transistor, wherein a first drain/source terminal of the second transistor receives the supply voltage, and a gate terminal of the second transistor is connected with a second drain/source terminal of the second transistor; a third transistor, wherein a first drain/source terminal of the third transistor is connected with the second drain/source terminal of the second transistor, a gate terminal of the third transistor is connected with a third node, and a second drain/source terminal of the third transistor is connected with the third node; and a first current source connected between the third node and the ground terminal, wherein a voltage at the third node is the first bias voltage.

14. The non-volatile memory as claimed in claim 6, wherein the second bias circuit comprises: a second transistor, wherein a first drain/source terminal of the second transistor is connected with the first node, and a gate terminal of the second transistor is connected with the first node; and a third transistor, wherein a first drain/source terminal of the third transistor is connected with a second drain/source terminal of the second transistor, a gate terminal of the third transistor is connected with the second drain/source terminal of the second transistor, and a second drain/source terminal of the third transistor is connected with the ground terminal, wherein a voltage at the first node is the second bias voltage.

15. The non-volatile memory as claimed in claim 1, wherein the first value of the control signal is determined according to characteristics of an on current and an off current of the selected memory cell.

16. The non-volatile memory as claimed in claim 1, wherein the first sense amplifier comprises: a first transistor, wherein a first drain/source terminal of the first transistor receives the supply voltage, a gate terminal of the first transistor receives a pre-charge signal, a second drain/source terminal of the first transistor is connected with a first node, the current mirroring terminal of the mirroring circuit is connected with first node, and the first data line is coupled to the first node; a second transistor, wherein a first drain/source terminal of the second transistor is connected with the first node, a gate terminal of the second transistor is connected with a second node, a second drain/source terminal of the second transistor is connected with a ground terminal, and a voltage at the second node a data signal; a third transistor, wherein a first drain/source terminal of the third transistor receives the supply voltage, a gate terminal of the third transistor is connected with the first node, and a second drain/source terminal of the third transistor is connected with the second node; and a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the second node, a gate terminal of the fourth transistor is connected with the first node, and a second drain/source terminal of the fourth transistor is connected with the ground terminal.

17. The non-volatile memory as claimed in claim 1, wherein the first sense amplifier comprises: a first transistor, wherein a first drain/source terminal of the first transistor receives the supply voltage, a gate terminal of the first transistor receives a pre-charge signal, a second drain/source terminal of the first transistor is connected with a first node, the current mirroring terminal of the mirroring circuit is connected with first node, and the first data line is coupled to the first node; a second transistor, wherein a first drain/source terminal of the second transistor receives the supply voltage, a gate terminal of the second transistor receives a bias voltage, and a second drain/source terminal of the second transistor is connected with a second node; a third transistor, wherein a first drain/source terminal of the third transistor receives the supply voltage, a gate terminal of the third transistor is connected with the second node, a second drain/source terminal of the third transistor is connected with a third node, and a voltage at the third node is a data signal; a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the second node, and a gate terminal of the fourth transistor is connected with the first node; a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with a second drain/source terminal of the fourth transistor, a gate terminal of the fifth transistor is connected with the third node, and a second drain/source terminal of the fifth transistor is connected with a ground terminal; a sixth transistor, wherein a first drain/source terminal of the sixth transistor is connected with the second node, a gate terminal of the sixth transistor receives an inverted pre-charge signal, and a second drain/source terminal of the sixth transistor is connected with the ground terminal; and a seventh transistor, wherein a first drain/source terminal of the seventh transistor is connected with the third node, a gate terminal of the seventh transistor is connected with the second node, and a second drain/source terminal of the seventh transistor is connected with the ground terminal.

18. The non-volatile memory as claimed in claim 1, further comprising a first clamping device, wherein the first sense amplifier is coupled to the first data line through the first clamping device.

19. The non-volatile memory as claimed in claim 18, further comprising a second clamping device, wherein the current input terminal of the mirroring circuit is coupled to the first current path selecting circuit through the second clamping device.

20. The non-volatile memory as claimed in claim 18, wherein the first clamping device comprises a first transistor, wherein a first drain/source terminal of the first transistor is connected with the first sense amplifier, a second drain/source terminal of the first transistor is connected with the first data line, and a gate terminal of the first transistor is connected with a clamping voltage generation circuit to receive a clamping voltage.

21. The non-volatile memory as claimed in claim 20, wherein the clamping voltage generation circuit comprises: a first bias circuit connected between the supply voltage and a ground terminal, wherein the first bias circuit generates a first bias voltage; a second current path selecting circuit connected between the supply voltage and a first node, wherein the second current path selecting circuit receives an option signal and the first bias voltage, and generates a first current; a second bias circuit connected between the supply voltage and the ground terminal, wherein the second bias circuit generates a second bias voltage and provides the second bias voltage to the first node; a first resistor connected between the first node and a second node, wherein a voltage at the second node is the clamping voltage; a second transistor, wherein a first drain/source terminal of the second transistor is connected with the second node, and a gate terminal of the second transistor is connected with the second node; and a third transistor, wherein a first drain/source terminal of the third transistor is connected with a second drain/source terminal of the second transistor, a gate terminal of the third transistor is connected with the second drain/source terminal of the second transistor, and a second drain/source terminal of the third transistor is connected with the ground terminal.

22. The non-volatile memory as claimed in claim 21, wherein the first resistor is implemented by a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the first node, a gate terminal of the fourth transistor is connected with the ground terminal, and a second drain/source terminal of the fourth transistor is connected with the second node.

23. The non-volatile memory as claimed in claim 21, wherein the second current path selecting circuit comprises: a first current path comprising a first voltage-controlled current source and a first switch, which are serially connected between the supply voltage and the first node; and a second current path comprising a second voltage-controlled current source and a second switch, which are serially connected between the supply voltage and the first node, wherein the first switch is selectively in a close state or an open state according to a first option bit of the option signal, the second switch is selectively in the close state or the open state according to a second option bit of the option signal, the first voltage-controlled current source generates a first voltage-controlled current according to the first bias voltage, and the second voltage-controlled current source generates a second voltage-controlled current according to the first bias voltage, wherein at least one of the first switch and the second switch is in the close state.

24. The non-volatile memory as claimed in claim 21, wherein the second current path selecting circuit comprises a first current path and a second current path, wherein the first current path comprises: a fourth transistor, wherein a first drain/source terminal of the fourth transistor receives the supply voltage, and a gate terminal of the fourth transistor receives a first option bit of the option signal; and a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with a second drain/source terminal of the fourth transistor, a gate terminal of the fifth transistor receives the first bias voltage, and a second drain/source terminal of the fifth transistor is connected with the first node, wherein the second current path comprises: a sixth transistor, wherein a first drain/source terminal of the sixth transistor receives the supply voltage, and a gate terminal of the sixth transistor receives a second option bit of the option signal; a seventh transistor, wherein a first drain/source terminal of the seventh transistor is connected with a second drain/source terminal of the sixth transistor, a gate terminal of the seventh transistor receives the first bias voltage, and a second drain/source terminal of the seventh transistor is connected with the first node, wherein the fourth transistor is selectively in an on state or an off state according to the first option bit of the option signal, the sixth transistor is selectively in the on state or the off state according to the second option bit of the option signal, the fifth transistor generates a first voltage-controlled current according to the first bias voltage, and the seventh transistor generates a second voltage-controlled current according to the first bias voltage, wherein at least one of the fourth transistor and the sixth transistor is in the on state.

25. The non-volatile memory as claimed in claim 21, wherein the first bias circuit comprises: a fourth transistor, wherein a first drain/source terminal of the fourth transistor receives the supply voltage, and a gate terminal of the fourth transistor is connected with a second drain/source terminal of the fourth transistor; a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with the second drain/source terminal of the fourth transistor, and a gate terminal of the fifth transistor is connected with a second drain/source terminal of the fifth transistor; a sixth transistor, wherein a first drain/source terminal of the sixth transistor is connected with the second drain/source terminal of the fifth transistor, a gate terminal of the sixth transistor is connected with a third node, and a second drain/source terminal of the sixth transistor is connected with the third node; and a first current source connected between the third node and the ground terminal, wherein a voltage at the third node is the first bias voltage.

26. The non-volatile memory as claimed in claim 21, wherein the second bias circuit comprises: a fourth transistor, wherein a first drain/source terminal of the fourth transistor is connected with the first node, and a gate terminal of the fourth transistor is connected with the first node; a fifth transistor, wherein a first drain/source terminal of the fifth transistor is connected with a second drain/source terminal of the fourth transistor, and a gate terminal of the fifth transistor is connected with the second drain/source terminal of the fourth transistor; and a sixth transistor, wherein a first drain/source terminal of the sixth transistor is connected with a second drain/source terminal of the fifth transistor, a gate terminal of the sixth transistor is connected with the second drain/source terminal of the fifth transistor, and a second drain/source terminal of the sixth transistor is connected with the ground terminal, wherein a voltage at the first node is the second bias voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

[0018] FIG. 1 (prior art) is a schematic circuit diagram illustrating a conventional non-volatile memory;

[0019] FIG. 2A is a schematic circuit diagram illustrating the equivalent circuit of a memory cell with N MOS transistors;

[0020] FIG. 2B is a plot illustrating the relationship between the supply voltage and the cell current about the memory cell of FIG. 2A in various storage states;

[0021] FIGS. 2C and 2D are plots illustrating the relationship between the supply voltage and the cell current about the memory cell, in which the reference current is determined according to the characteristics of the memory cell;

[0022] FIG. 3 is a schematic circuit diagram illustrating a non-volatile memory according to a first embodiment of the present invention;

[0023] FIG. 4A is a schematic circuit diagram illustrating the mirroring circuit and the current path selecting circuit of the reference current generator in the non-volatile memory as shown in FIG. 3;

[0024] FIG. 4B is a schematic circuit diagram illustrating a control voltage generation circuit of the reference current generator in the non-volatile memory as shown in FIG. 3;

[0025] FIG. 5A is a schematic circuit diagram illustrating the detailed circuitry structure of the reference current generator in the non-volatile memory according to the first embodiment of the present invention;

[0026] FIG. 5B is a plot illustrating the relationship between the control voltage and the supply voltage of the reference current generator in the non-volatile memory according to the first embodiment of the present invention;

[0027] FIG. 5C is a plot illustrating the relationship between the reference current and the supply voltage of the reference current generator in the non-volatile memory according to the first embodiment of the present invention;

[0028] FIGS. 6A and 6B are schematic circuit diagrams illustrating two types of sense amplifiers used in the sensing circuit of the non-volatile memory according to the first embodiment of the present invention; and

[0029] FIG. 7 is a schematic circuit diagram illustrating a non-volatile memory according to a second embodiment of the present invention; and

[0030] FIG. 8 is a schematic circuit diagram illustrating a clamping circuit in the non-volatile memory according to the second embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0031] Generally, the process parameters and the process conditions of different foundries are not identical. Even if the memory cells with the same structure are produced, the characteristics of the memory cells are also different. Similarly, different batches of memory cells manufactured by the same foundry may have different characteristics. Consequently, when the memory cell array comprising memory cells is operated according to various supply voltages V.sub.S, the cell currents generated by the memory cells have significant differences. The reasons will be described as follows by referring to the memory cell with NMOS transistors.

[0032] FIG. 2A is a schematic circuit diagram illustrating the equivalent circuit of a memory cell with NMOS transistors. FIG. 2B is a plot illustrating the relationship between the supply voltage and the cell current about the memory cell of FIG. 2A in various storage states. As shown in FIG. 2A, the memory cell 200 comprises a select transistor M.sub.SEL, a floating gate transistor M.sub.F and a capacitor C. The memory cell 200 is a multi-time programmable memory cell, which is also referred as an MTP memory cell). In other words, the memory cell 200 may be subjected to a program action, an erase action or a read action.

[0033] The first drain/source terminal of the select transistor M.sub.SEL is connected with a bit line BL. The gate terminal of the select transistor M.sub.SEL is connected with a word line WL. The first drain/source terminal of the floating gate transistor M.sub.F is connected with the second drain/source terminal of the select transistor M.sub.SEL. The second drain/source terminal of the floating gate transistor M.sub.F is connected with a source line SL. The first terminal of the capacitor C is connected with a floating gate FG of the floating gate transistor M.sub.F. The second terminal of the capacitor C is connected with an erase line EL. For example, the capacitor C is composed of an NMOS transistor. The gate terminal of the NMOS transistor is the first terminal of the capacitor C. The first drain/source terminal and the second drain/source terminal of the NMOS transistor are connected with each other and served as the second terminal of the capacitor C.

[0034] For example, two memory cells with the same structure but different characteristics will be illustrated. Please refer to FIG. 2B. When the supply voltage V.sub.S rises from 1.7V to 5.75V, the on currents I.sub.ON_12 of the two memory cells in the first storage state (i.e., the on state) gradually increase. The rising slopes are similar. It can be regarded that the change amounts of the cell currents I.sub.CELL of the two memory cells in the on state are very close.

[0035] However, the rising slops of the cell currents I.sub.CELL generated by the two memory cells in the second storage state (i.e., the off state) are different when the supply voltage V.sub.S changes. In FIG. 2B, the solid line represents the change of the off current I.sub.OFF_1 of the first memory cell. When the supply voltage V.sub.S rises from 1.7V to 5.75V, the slope of the off current I.sub.OFF_1 is smaller. That is, the change amount of the cell current I.sub.CELL of the first memory cell is smaller. In FIG. 2B, the dashed line represents the change of the off current I.sub.OFF_2 of the second memory cell. When the supply voltage V.sub.S rises from 1.7V to 5.75V, the slope of the off current I.sub.OFF_2 is larger. That is, the change amount of the cell current I.sub.CELL of the second memory cell is larger. It is speculated that the above two memory cells may be manufactured in different foundries or manufactured in different batches.

[0036] Obviously, in case that the reference current I.sub.REF is not varied with the change of the supply voltage V.sub.S, the sensing circuit may misjudge the storage state of the memory cell. As shown in FIG. 2B, the sensing circuit can correctly judge the storage state of the first memory cell when the supply voltage V.sub.S is in the range between Va (e.g., 2.0V) and Vc (e.g., 4.0V). The sensing circuit can correctly judge the storage state of the second memory cell when the supply voltage V.sub.S is in the range between Va (e.g., 2.0V) and Vb (e.g., 3.5V). However, if the supply voltage V.sub.S is lower than Va, the sensing circuit may erroneously judge that the two memory cells are in the off state regardless of the actual storage states of the memory cells. Similarly, if the supply voltage V.sub.S is higher than Vc, the sensing circuit may erroneously judge that the two memory cells are in the on state regardless of the actual storage states of the memory cells.

[0037] From the above illustration, it can be seen that different memory cells will have different variations of on/off current under different supply voltage V.sub.S. For allowing the sensing circuit to correctly judge the storage state of the memory cell, the reference current generator needs to provide an appropriate reference current according to the characteristics of the memory cell. For example, the reference current generator may provide an appropriate reference current according to the characteristics of the on current I.sub.ON and the off current I.sub.OFF of the memory cell.

[0038] FIGS. 2C and 2D are plots illustrating the relationship between the supply voltage and the cell current about the memory cell, in which the reference current is determined according to the characteristics of the memory cell. In FIG. 2C, the cell current I.sub.CELL of the first memory cell in the on state is the on current I.sub.ON_12, and the cell current I.sub.CELL of the first memory cell in the off state is the off current I.sub.OFF_1. The reference current generator provides a first reference current I.sub.REF_1 to the sensing circuit. According to the first reference current I.sub.REF_1, the sense amplifier judges the storage state of the first memory cell. In FIG. 2D, the cell current I.sub.CELL of the second memory cell in the on state is the on current I.sub.ON_12, and the cell current I.sub.CELL of the second memory cell in the off state is the off current I.sub.OFF_2. The reference current generator provides a second reference current I.sub.REF_2 to the sensing circuit. According to the second reference current I.sub.REF_2, the sense amplifier judges the storage state of the second memory cell. As the supply voltage V.sub.S increases, the first reference current I.sub.REF_1 and the second reference current I.sub.REF_2 increase. In addition, the slope of the second reference current I.sub.REF_2 is larger than the slope of the first reference current I.sub.REF_1.

[0039] For allowing the sensing circuit of the non-volatile memory to correctly judge the storage state of the memory cell, the reference current generator of the present invention is specially designed, so that the reference current generator is capable of providing the reference currents with different slopes. In accordance with a feature of the present invention, the reference current generator provides a reference current with a specified slope to the sensing circuit according to the characteristics of the memory cell in the non-volatile memory.

[0040] FIG. 3 is a schematic circuit diagram illustrating a non-volatile memory according to a first embodiment of the present invention. As shown in FIG. 3, the non-volatile memory 300 comprises a memory module 110, a reference current generator 320 and a sensing circuit 390. The structures and the operating principles of the memory module 110 in this embodiment are identical to those of the memory module 110 shown in FIG. 1, and not redundantly described herein.

[0041] The sensing circuit 390 comprises X sense amplifiers 381?38x. The X sense amplifiers 381?38x are respectively connected with the corresponding data lines DL.sub.1?DL.sub.X. The X sense amplifiers 381?38x receive the reference current I.sub.REF. According to the cell currents I.sub.CELL in the data lines DL.sub.1?DL.sub.X, the X sense amplifiers 381?38x generate the corresponding data signals D.sub.O1?D.sub.OX. The structures and the operating principles of the X sense amplifiers 381?38x are identical.

[0042] In this embodiment, the reference current generator 320 comprises a mirroring circuit 330, a current path selecting circuit 340 and a control voltage generation circuit 350.

[0043] The control voltage generation circuit 350 receives a control signal S.sub.CTL and generates a control voltage V.sub.CTL. According to the control signal S.sub.CTL, various change relationships between the supply voltage V.sub.S and the control voltage V.sub.CTL can be determined.

[0044] The current path selecting circuit 340 receives the control voltage V.sub.CTL and a selection signal S.sub.SEL, and the current path selecting circuit 340 generates the reference current I.sub.REF. Generally, the control voltage V.sub.CTL and the reference current I.sub.REF are in a positive correlation. That is, as the control voltage V.sub.CTL increases, the reference current I.sub.REF increases. Similarly, as the control voltage V.sub.CTL decreases, the reference current I.sub.REF decreases. In other words, the cooperation of the control voltage generation circuit 350 and the current path selecting circuit 340 can determine various slope variation relationships between the supply voltage V.sub.S and the reference current I.sub.REF.

[0045] The mirroring circuit 330 receives the reference current I.sub.REF. In addition, the reference current I.sub.REF is transmitted from the mirroring circuit 330 to the sense amplifiers 381?38x of the sensing circuit 390. According to the reference current I.sub.REF, the sense amplifiers 381?38x judges the storage states of the corresponding selected memory cells.

[0046] FIG. 4A is a schematic circuit diagram illustrating the mirroring circuit and the current path selecting circuit of the reference current generator in the non-volatile memory as shown in FIG. 3. As shown in FIG. 4A, the mirroring circuit 330 comprises a current input terminal and X current mirroring terminals. The current input terminal of the mirroring circuit 330 is connected with the current path selecting circuit 340 to receive the reference current I.sub.REF. The X current mirroring terminals of the mirroring circuit 330 are respectively connected with the sense amplifiers 381?38x of the sensing circuit 390.

[0047] The mirroring circuit 330 comprises (X+1) transistors M.sub.A and M.sub.B1?M.sub.BX. The first drain/source terminal of the transistor M.sub.A receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.A is connected with the second drain/source terminal of the transistor M.sub.A. The second drain/source terminal of the transistor M.sub.A is the current input terminal of the mirroring circuit 330. The first drain/source terminal of the transistor M.sub.B1 receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.B1 is connected with the gate terminal of the transistor M.sub.A. The second drain/source terminal of the transistor M.sub.B1 is the current mirroring terminal of the mirroring circuit 330. In addition, the second drain/source terminal of the transistor M.sub.B1 is connected with the sense amplifier 381. Moreover, the transistors M.sub.B1?M.sub.BX have the same connection relationship, and not redundantly described herein. The first drain/source terminal of the transistor M.sub.BX receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.BX is connected with the gate terminal of the transistor M.sub.A. The second drain/source terminal of the transistor M.sub.BX is the current mirroring terminal of the mirroring circuit 330. The second drain/source terminal of the transistor M.sub.BX is connected with the corresponding sense amplifier 38x.

[0048] In an embodiment, the sizes of the transistors M.sub.A and M.sub.B1-M.sub.BX are identical. Consequently, when the current input terminal of the mirroring circuit 330 receives the reference current I.sub.REF, the X current mirroring terminals of the mirroring circuit 330 can respectively output the reference currents I.sub.REF to the sense amplifiers 381?38x of the sensing circuit 390.

[0049] The current path selecting circuit 340 comprises two current paths 341 and 342. According to the control voltage V.sub.CTL the current paths 341 and 342 generate corresponding voltage-controlled currents I.sub.C1 and I.sub.C2, respectively. The selection signal S.sub.SEL is a two-bit signal. The two-bit signal contains two selection bits S.sub.SEL_1 and S.sub.SEL_2 corresponding to the current paths 341 and 342, respectively. In addition, at least one current path is activated according to the selection signal S.sub.SEL. The total current of the activated current paths is the reference current I.sub.REF.

[0050] In the current path selecting circuit 340, the current path 341 comprises a voltage-controlled current source 345 and a switch SW.sub.1, and the current path 342 comprises a voltage-controlled current source 346 and a switch SW.sub.2. The voltage-controlled current source 345 and the switch SW.sub.1 of the current path 341 are serially connected between a node a and a ground terminal GND. According to the control voltage V.sub.CTL, the voltage-controlled current source 345 generates the voltage-controlled current I.sub.C1. The switch SW.sub.1 is controlled according to the selection bit S.sub.SEL_1. The voltage-controlled current source 346 and the switch SW.sub.2 of the current path 342 are serially connected between the node a and the ground terminal GND. According to the control voltage V.sub.CTL, the voltage-controlled current source 346 generates the voltage-controlled current I.sub.C2. The switch SW.sub.2 is controlled according to the selection bit S.sub.SEL_2.

[0051] In an embodiment, the voltage-controlled current I.sub.C1 generated by the current path 341 and the voltage-controlled current I.sub.C2 generated by the current path 342 are in a fixed proportional relationship. For example, in case that the control voltage V.sub.CTL is 1.0V, the voltage-controlled current I.sub.C1 and the voltage-controlled current I.sub.C2 are 2.0 ?A and 4.0 ?A, respectively. Whereas, in case that the control voltage V.sub.CTL is 1.2V, the voltage-controlled current I.sub.C1 and the voltage-controlled current I.sub.C2 are 2.4 ?A and 4.8 ?A, respectively. It is noted that the ratio between the voltage-controlled current I.sub.C1 and the voltage-controlled current I.sub.C2 is not restricted.

[0052] Moreover, according to the selection signal S.sub.SEL, at least one of the two switches SW.sub.1 and SW.sub.2 is controlled to be in a close state. For example, if the selection bit S.sub.SEL_1 is in the logic level state 1, the switch SW.sub.1 is in the close state, and the current path 341 is activated. Whereas, if the selection bit S.sub.SEL_1 is in the logic level state 0, the switch SW.sub.1 is in the open state, and the current path 341 is inactivated. In other words, the switches SW.sub.1 and SW.sub.2 are controlled to be in the close state or the open state according to the binary value of the selection signal S.sub.SEL.

[0053] For example, if the two selection bits <S.sub.SEL_1, S.sub.SEL 2> of the selection signal S.sub.SEL are <1, 1>, the current path 341 and the current path 342 are activated. Consequently, the reference current I.sub.REF is equal to I.sub.C1+I.sub.C2. Moreover, if the two selection bits <S.sub.SEL_1, S.sub.SEL_2> of the selection signal S.sub.SEL are <0, 1>, the current path 341 is inactivated, but the current path 342 is activated. Consequently, the reference current I.sub.REF is equal to I.sub.C2.

[0054] In FIG. 4A, the current path selecting circuit 340 comprises the two current paths 341 and 342. As long as the number of the current paths in the current path selecting circuit 340 is larger than or equal to 1, the number of the current paths in the current path selecting circuit 340 is not restricted. For example, in another embodiment, the current path selecting circuit 340 comprises three current paths, and the selection signal S.sub.SEL is a three-bit signal.

[0055] FIG. 4B is a schematic circuit diagram illustrating a control voltage generation circuit of the reference current generator in the non-volatile memory as shown in FIG. 3. As shown in FIG. 4B, the control voltage generation circuit 350 comprises a transistor M.sub.G1, a resistor R.sub.G, two bias circuits 351, 353 and two current path selecting circuits 355, 357.

[0056] The first terminal of the resistor R.sub.G is connected with a node b. The second terminal of the resistor R.sub.G is connected with a node c. The first drain/source terminal of the transistor M.sub.G1 is connected with the node c. The gate terminal of the transistor M.sub.G1 is connected with the node c. The second drain/source terminal of the transistor M.sub.G1 is connected with the ground terminal GND. Moreover, the voltage at the node c is served as the control voltage V.sub.CTL.

[0057] The bias circuit 351 comprises two diode-connected transistors M.sub.D1 and M.sub.D2 and a current source 352. The diode-connected transistors M.sub.D1 and M.sub.D2 are serially connected between the supply voltage V.sub.S and a node d. That is, the first drain/source terminal of the transistor M.sub.D1 receives the supply voltage V.sub.S, the gate terminal of the transistor M.sub.D1 is connected with the second drain/source terminal of the transistor M.sub.D1, the first drain/source terminal of the transistor M.sub.D2 is connected with the second drain/source terminal of the transistor M.sub.D1, the gate terminal of the transistor M.sub.D2 is connected with the node d, and the second drain/source terminal of the transistor M.sub.D2 is connected with the node d. Moreover, the first terminal of the current source 352 is connected with the node d, and the second terminal of the current source 352 is connected with the ground terminal GND.

[0058] In an embodiment, the sizes of the transistors M.sub.D1 and M.sub.D2 are identical, and the current source 352 provides a bias current Isl. Consequently, the bias voltage V.sub.B1 at the node d is approximately equal to V.sub.S?2V.sub.SG, wherein V.sub.SG=(?{square root over (I.sub.B1/K.sub.p)}?V.sub.THP), V.sub.SG is the voltage difference between the source terminal and the gate terminal of the transistor M.sub.D1, K.sub.p is a device parameter of the transistor M.sub.D1, and V.sub.THP is the threshold voltage of the transistor M.sub.D1, and assume that the transistors M.sub.D1 and M.sub.D2 have the same threshold voltage V.sub.THP in ideal. In addition, the threshold voltage V.sub.THP is negative.

[0059] The bias voltage 353 comprises two diode-connected transistors M.sub.E1 and M.sub.E2. The diode-connected transistors M.sub.E1 and M.sub.E2 are serially connected between the node b and the ground terminal GND. That is, the first drain/source terminal of the transistor M.sub.E1 is connected with the node b, the gate terminal of the transistor M.sub.E1 is connected with the node b, the first drain/source terminal of the transistor M.sub.E2 is connected with the second drain/source terminal of the transistor M.sub.E1, the gate terminal of the transistor M.sub.E2 is connected with the first drain/source of the transistor M.sub.E2, and the second drain/source terminal of the transistor M.sub.E2 is connected with the ground terminal GND. Moreover, the bias voltage V.sub.B2 at the node b is determined according to the bias current I.sub.B2.

[0060] For example, the sizes of the transistor M.sub.E1 and the transistor M.sub.E2 are identical. Consequently, the bias voltage V.sub.B2 at the node b is approximately equal to 2V.sub.GS, wherein V.sub.GS=(?{square root over (I.sub.B2/K.sub.n)}+V.sub.THN), V.sub.SG is the voltage difference between the gate terminal and the drain terminal of the transistor M.sub.E2, K.sub.n is a device parameter of the transistor M.sub.E2, and V.sub.THN is the threshold voltage of the transistor M.sub.E2, and assume that the transistors MEI and M.sub.E2 have the same threshold voltage V.sub.THN in ideal. In addition, the threshold voltage V.sub.THN is positive.

[0061] The current path selecting circuit 355 comprises two current paths 361 and 362. According to the bias voltage V.sub.B1, the current paths 361 and 362 generate the corresponding voltage-controlled currents I.sub.D1 and I.sub.D2 respectively. In addition, the control signal S.sub.CTL is a four-bit signal. The four-bit signal contains four control bits S.sub.CTL_A, S.sub.CTL_B, S.sub.CTL_C and S.sub.CTL_D. The current path 361 is controlled according to the control bit S.sub.CTL_A. The current path 362 is controlled according to the control bit S.sub.CTL_B. In addition, at least one current path of the current path selecting circuit 355 is activated according to the control signal S.sub.CTL.

[0062] In the current path selecting circuit 355, the current path 361 comprises a voltage-controlled current source 368 and a switch SW.sub.A, and the current path 362 comprises a voltage-controlled current source 369 and a switch SW.sub.B. The voltage-controlled current source 368 and the switch SW A of the current path 361 are serially connected between the supply voltage V.sub.S and the node b. According to the bias voltage V.sub.B1, the voltage-controlled current source 368 generates the voltage-controlled current I.sub.D1. The switch SW.sub.A is controlled according to the control bit S.sub.CTL_A. The voltage-controlled current source 369 and the switch SW.sub.B of the current path 362 are serially connected between the supply voltage V.sub.S and the node b. According to the bias voltage V.sub.B1, the voltage-controlled current source 369 generates the voltage-controlled current I.sub.D2. The switch SW.sub.B is controlled according to the control bit S.sub.CTL_B.

[0063] In an embodiment, the magnitudes of the voltage-controlled currents I.sub.D1 and I.sub.D2 generated by the voltage-controlled current sources 368, 369 are different. For example, the magnitude of the voltage-controlled current I.sub.D1 is higher than the magnitude of the voltage-controlled current I.sub.D2. Moreover, according to the control signal S.sub.CTL, at least one of the two switches SW A and SW B is controlled to be in a close state. For example, if the control bit S.sub.CTL_A is in the logic level state 0, the switch SW.sub.A is in the close state, and the current path 361 is activated. Whereas, if the control bit S.sub.CTL_A is in the logic level state 1, the switch SW A is in the open state, and the current path 361 is inactivated. For example, if the two control bits <S.sub.CTL_A, S.sub.CTL_B> of the control signal S.sub.CTL is <1, 0>, the current path 362 is activated, but the current path 361 is inactivated.

[0064] The current path selecting circuit 357 comprises two current paths 363 and 364. The current paths 363 and 364 generate the corresponding currents I.sub.E1 and I.sub.E2 respectively. The current path 363 is controlled according to the control bit S.sub.CTL_C of the control signal S.sub.CTL. The current path 364 is controlled according to the control bit S.sub.CTL_D of the control signal S.sub.CTL.

[0065] In the current path selecting circuit 357, the current path 363 comprises a resistor R.sub.C and a switch SW.sub.C, and the current path 364 comprises a resistor R D and a switch SW.sub.D. The resistor R.sub.C and the switch SW.sub.C of the current path 363 are serially connected between the supply voltage V.sub.S and the node c. The switch SW.sub.C is controlled according to the control bit S.sub.CTL_C of the control signal S.sub.CTL. The resistor RD and the switch SW D of the current path 364 are serially connected between the supply voltage V.sub.S and the node c. The switch SW.sub.D is controlled according to the control bit S.sub.CTL_D of the control signal S.sub.CTL.

[0066] In an embodiment, the resistance of the resistor R.sub.C of the current path 363 and the resistance of the resistor R D of the current path 364 are different. Consequently, the magnitudes of the currents I.sub.E1 and I.sub.E2 are different. For example, the magnitude of the resistance of the resistor RD is lower than the magnitude of the resistance of the resistor RD. That is, the current I.sub.E1 is lower than the current I.sub.E2. Moreover, if the control bit S.sub.CTL c is in the logic level state 0, the switch SW.sub.C is in the close state, and the current path 363 is activated. Whereas, if the control bit S.sub.CTL_C is in the logic level state 1, the switch SW.sub.C is in the open state, and the current path 363 is inactivated. For example, if the two control bits <S.sub.CTL_C, S.sub.CTL_D> of the control signal S.sub.CTL is <1, 0>, the current path 364 is activated, and the current path 363 is inactivated. In other words, the switches SW.sub.A?SW.sub.D of the current path selecting circuits 355 and 357 are controlled to be in the close state or the open state according to the binary value of the control signal S.sub.CTL.

[0067] In FIG. 4B, each of the two current path selecting circuits 355 and 357 comprise the two current paths. In practice, the number of the current paths in each of the current path selecting circuits 355 and 357 is not restricted. The total number of the current paths in the current path selecting circuits 355 and 357 is equal to the number of the control bits in the control signal S.sub.CTL.

[0068] When the output current from the current path selecting circuit 355 flows to the node b, a portion of the output current is served as the bias current I.sub.B2 flowing to the bias circuit 353, and another portion of the output current flows to the ground terminal GND through the resistor R.sub.G and the transistor M.sub.G1. In addition, the output current from the current path selecting circuit 357 flows to the node c and then flows to the ground terminal GND through the transistor M.sub.G1.

[0069] The bias circuit 353 generates the bias voltage V.sub.B2 according to the bias current I.sub.B2. The bias voltage V.sub.B2 is in proportion to the voltage difference V.sub.GS of the transistor M.sub.E2, and the voltage difference V.sub.GS is in proportion to the square root of the bias current I.sub.B2. When different supply voltage V.sub.S are provided to the non-volatile memory 300, the bias current I.sub.B2 will change. Furthermore, the change of the bias current I.sub.B2 will cause slight change of the bias voltage V.sub.B2 generated by the bias circuit 353. That is, when different supply voltage V.sub.S are provided to the non-volatile memory 300, the change of the output current from the current path selecting circuit 355 may result in a tiny change of the control voltage V.sub.CTL. In addition, the output current from the current path selecting circuit 357 flows to the node c. When different supply voltage V.sub.S are provided to the non-volatile memory 300, the change of the output current from the current path selecting circuit 357 will directly result in a large change of the control voltage V.sub.CTL.

[0070] In this embodiment, the control signal S.sub.CTL is utilized to determine the current flowing to the node b and the current flowing to the node c, which result in different amplitude changes of the control voltage V.sub.CTL. Therefore, after the control voltage V.sub.CTL is inputted into the current path selecting circuit 340, the reference current I.sub.REF with different slopes will be generated.

[0071] FIG. 5A is a schematic circuit diagram illustrating the detailed circuitry structure of the reference current generator in the non-volatile memory according to the first embodiment of the present invention. The reference current generator 320 comprises the mirroring circuit 330, the current path selecting circuit 340 and the control voltage generation circuit 350. The circuitry structure of the mirroring circuit 330 is similar to that shown in FIG. 4A, and not redundantly described herein.

[0072] In the current path selecting circuit 340, the transistors M.sub.SW1 and M.sub.SW2 are served as the switches, and transistors M.sub.C1?M.sub.C3 are served as the voltage-controlled current sources. In addition, the selection signal S.sub.SEL comprises two selection bits S.sub.SEL_1 and S.sub.SEL_2.

[0073] The current path 341 of the current path selecting circuit 340 comprises two transistors M.sub.C1 and M.sub.SW1. The first drain/source terminal of the transistor M.sub.C1 is connected with the node a. The gate terminal of the transistor M.sub.C1 receives the control signal V.sub.CTL. The first drain/source terminal of the transistor M.sub.SW1 is connected with the second drain/source terminal of the transistor M.sub.C1. The gate terminal of the transistor M.sub.SW1 receives the selection bit S.sub.SEL_1. The second drain/source of the transistor M.sub.SW1 is connected with the ground terminal GND.

[0074] The current path 342 of the current path selecting circuit 340 comprises two transistors M.sub.C2 and M.sub.C3 and a transistor M.sub.SW2. The first drain/source terminal of the transistor M.sub.C2 is connected with the node a. The gate terminal of the transistor M.sub.C2 receives the control signal V.sub.CTL. The first drain/source terminal of the transistor M.sub.C3 is connected with the node a. The gate terminal of the transistor M.sub.C3 receives the control signal V.sub.CTL. The first drain/source terminal of the transistor M.sub.SW2 is connected with the second drain/source terminal of the transistor Mu and the second drain/source terminal of the transistor M.sub.C3. The gate terminal of the transistor M.sub.SW2 receives the selection bit S.sub.SEL_2. The second drain/source terminal of the transistor M.sub.SW2 is connected with the ground terminal GND.

[0075] In an embodiment, the size of each of the transistors M.sub.C1, Mcg and M.sub.C3 is equal to the size of the floating gate transistor of the memory cell. Consequently, the voltage-controlled current I.sub.C1 in the current path 341 and the voltage-controlled current I.sub.C2 in the current path 342 are in a specified proportional relationship, e.g., 1:2. In some other embodiments, the voltage-controlled current source in the current path 342 comprises a single transistor M.sub.C2. In this case, the sizes of the transistors M.sub.C1 and M.sub.C2 are specially designed such that the voltage-controlled current I.sub.C1 in the current path 341 and the voltage-controlled current I.sub.C2 in the current path 342 are in a specified proportional relationship. For example, the size of the transistor M.sub.C2 is x times the size of the transistor M.sub.C1. Consequently, the voltage-controlled currents I.sub.C1 and I.sub.C2 are in the 1:x relationship, and x can be any positive value.

[0076] The control voltage generation circuit 350 comprises a transistor M.sub.G1, a transistor M.sub.G2, the two bias circuits 351 and 353 and the two current path selecting circuits 355 and 357. The connection relationships of the transistor M.sub.G1, the bias circuit 351 and the bias circuit 353 are identical to those of FIG. 4B, and not redundantly described herein. Moreover, the control signal S.sub.CTL contains the control bits S.sub.CTL_A, S.sub.CTL_B, S.sub.CTL_C and S.sub.CTL_D.

[0077] The first drain/source terminal of the transistor M.sub.G2 is connected with the node b. The gate terminal of the transistor M.sub.G2 is connected with the ground terminal GND. The second drain/source terminal of the transistor M.sub.G2 is connected with the node c. The transistor M.sub.G2 may be equivalently regarded as a resistor.

[0078] In the current path selecting circuit 355, the transistors M.sub.SWA and M.sub.SWB are served as the switches, and the transistors M.sub.H1 and M.sub.H2 are served as the voltage-controlled current sources. The current path 361 comprises the transistor M.sub.H1 and the transistor M.sub.SWA. The first drain/source terminal of the transistor M.sub.SWA receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.SWA receives the control bit S.sub.CTL_A. The first drain/source terminal of the transistor M.sub.H1 is connected with the second drain/source terminal of the transistor M.sub.SWA. The gate terminal of the transistor M.sub.H1 receives the bias voltage V.sub.B1. The second drain/source terminal of the transistor M.sub.H1 is connected with the node b.

[0079] The current path 362 of the current path selecting circuit 355 comprises a transistor M.sub.H2 and a transistor M.sub.SWB. The first drain/source terminal of the transistor M.sub.SWB receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.SWB receives the control bit S.sub.CTL_B. The first drain/source terminal of the transistor M.sub.H2 is connected with the second drain/source terminal of the transistor M.sub.SWB. The gate terminal of the transistor M.sub.H2 receives the bias voltage V.sub.B1. The second drain/source terminal of the transistor M.sub.H2 is connected with the node b.

[0080] In an embodiment, the size of the transistors M.sub.H1 and M.sub.H2 are different. Consequently, the voltage-controlled current I.sub.D1 in the current path 361 and the voltage-controlled current I.sub.D2 in the current path 362 are in a specified proportional relationship. For example, the size of the transistor M.sub.H1 is larger than the size of the transistor M.sub.H2. Consequently, the voltage-controlled current I.sub.D1 is higher than the voltage-controlled current I.sub.D2.

[0081] In the current path selecting circuit 357, the transistors M.sub.SWC and M.sub.SWD are served as the switches, and the transistors M.sub.SWC and M.sub.SWD and the transistor M.sub.H3 are served as the resistors. The current path 363 comprises the transistor M.sub.SWC. The first drain/source terminal of the transistor M.sub.SWC receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.SWC receives the control bit S.sub.CTL_C. The second drain/source terminal of the transistor M.sub.SWC is connected with the node c. When the transistor M.sub.SWC is turned on, the current path 363 is activated. Meanwhile, the internal resistance of the transistor M.sub.SWC may be regarded as the resistor.

[0082] The current path 364 of the current path selecting circuit 357 comprises a transistor M.sub.H3 and a transistor M.sub.SWD. The drain/source terminal of the transistor M.sub.SWD receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.SWD receives the control bit S.sub.CTL_D. The first drain/source terminal of the transistor M.sub.H3 is connected with the second drain/source terminal of the transistor M.sub.SWD. The gate terminal of the transistor M.sub.H3 is connected with the node c. The second drain/source terminal of the transistor M.sub.H3 is connected with the node c. It is designed that the current I.sub.E2 is higher than the current I.sub.E1. In accordance with a circuitry design, I.sub.D1>I.sub.D2, I.sub.E2>I.sub.E1, and (I.sub.D1+I.sub.E1) is approximately equal to (I.sub.D2+I.sub.E2).

[0083] As mentioned above, when the supply voltage V.sub.S rises, the output current from the current path selecting circuit 355 may result in a tiny change of the control voltage V.sub.CTL. In addition, the output current from the current path selecting circuit 357 may directly influence the control voltage V.sub.CTL. The current flowing to the node b and the current flowing to the node c are selected according to the control signal S.sub.CTL. That is, when different supply voltage V.sub.S are provided to the non-volatile memory 300, the extent of the change of the control voltage V.sub.CTL may be different. In addition, the reference current I.sub.REF with different slopes will be generated according to the control signal S.sub.CTL.

[0084] FIG. 5B is a plot illustrating the relationship between the control voltage and the supply voltage of the reference current generator in the non-volatile memory according to the first embodiment of the present invention.

[0085] If the control bits of the control signal S.sub.SEL <S.sub.CTL_A, S.sub.CTL_B, S.sub.CTL_C, S.sub.CTL_D> are <0, 1, 0, 1>, the current path 361 of the current path selecting circuit 355 is activated, and the current path 363 of the current path selecting circuit 357 is activated. As shown in FIG. 5B, the relationships between the control voltage V.sub.CTL and the supply voltage V.sub.S are indicated as circular symbols. For example, if the supply voltage V.sub.S is 1.7V, the control voltage V.sub.CTL is approximatively 0.972V. If the supply voltage V.sub.S is 5.75V, the control voltage V.sub.CTL is approximatively 1.359V.

[0086] Whereas, if the control bits of the control signal S.sub.SEL <S.sub.CTL_A, S.sub.CTL_B, S.sub.CTL_C, S.sub.CTL_D> is <1, 0, 1, 0>, the current path 362 of the current path selecting circuit 355 is activated, and the current path 364 of the current path selecting circuit 357 is activated. As shown in FIG. 5B, the relationships between the control voltage V.sub.CTL and the supply voltage V.sub.S are indicated as triangular symbols. For example, if the supply voltage V.sub.S is 1.7V, the control voltage V.sub.CTL is approximatively 0.878V. If the supply voltage V.sub.S is 5.75V, the control voltage V.sub.CTL is approximatively 1.765V.

[0087] As mentioned above in FIG. 5B, when different current paths in the control voltage generation circuit 350 are activated according to the control signal S.sub.CTL, the control voltage V.sub.CTL has different slopes with respect to the supply voltage V.sub.S. In other words, when different supply voltage V.sub.S are provided to the non-volatile memory 300, the change slope of the control voltage V.sub.CTL can be determined according to the control signal S.sub.CTL.

[0088] FIG. 5C is a plot illustrating the relationship between the reference current and the supply voltage of the reference current generator in the non-volatile memory according to the first embodiment of the present invention. The cooperation of the control voltage generation circuit and the current path selecting circuit result in the generation of the reference current. In this embodiment, the selection bits <S.sub.SEL_1, S.sub.SEL 2> of the selection signal S.sub.SEL are <1, 0>. That is, the current path 341 of the current path selecting circuit 340 is activated.

[0089] If the control bits of the control signal S.sub.SEL <S.sub.CTL_A, S.sub.CTL_B, S.sub.CTL_C, S.sub.CTL_D> are <0, 1, 0, 1>, the current path 361 of the current path selecting circuit 355 is activated, and the current path 363 of the current path selecting circuit 357 is activated. As shown in FIG. 50, the relationships between the reference current I.sub.REF and the supply voltage V.sub.S are indicated as circular symbols. For example, if the supply voltage V.sub.S is 1.7V, the reference current I.sub.REF is approximatively 1.31 ?A. If the supply voltage V.sub.S is 5.75V, the reference current I.sub.REF is approximatively 9.329 ?A.

[0090] Whereas, if the control bits of the control signal S.sub.SEL<S.sub.CTL_A, S.sub.CTL_B, S.sub.CTL_C, S.sub.CTL_D> is <1, 0, 1, 0>, the current path 362 of the current path selecting circuit 355 is activated, and the current path 364 of the current path selecting circuit 357 is activated. As shown in FIG. 5C, the relationships between the reference current I.sub.REF and the supply voltage V.sub.S are indicated as triangular symbols. For example, if the supply voltage V.sub.S is 1.7V, the reference current I.sub.REF is approximatively 0.879 ?A. If the supply voltage V.sub.S is 5.75V, the reference current I.sub.REF is approximatively 17.42 ?A.

[0091] As mentioned above in FIG. 5C, when different current paths in the control voltage generation circuit 350 are activated according to the control signal S.sub.CTL, the reference current I.sub.REF has different slopes with respect to the supply voltage V.sub.S. In other words, when different supply voltage V.sub.S are provided to the non-volatile memory 300, the change slope of the reference current I.sub.REF can be determined according to the control signal S.sub.CTL.

[0092] Moreover, if the two selection bits <S.sub.SEL_1, S.sub.SEL 2> of the selection signal S SEL are <0, 1>, the current path 342 of the current path selecting circuit 340 is activated. Consequently, the reference current I.sub.REF outputted from the current path selecting circuit is further doubled.

[0093] For example, in FIG. 5C, the circular symbols represent that the selection bits <S.sub.SEL_1, S.sub.SEL 2> of the selection signal S.sub.SEL are <1, 0>. If the supply voltage V.sub.S is 1.7V, the reference current I.sub.REF is approximatively 1.31 ?A. If the supply voltage V.sub.S is 5.75V, the reference current I.sub.REF is approximatively 9.329 ?A. Whereas, if the two selection bits <S.sub.SEL_1, S.sub.SEL_2> of the selection signal S.sub.SEL are <0, 1> and the supply voltage V.sub.S is 1.7V, the reference current I.sub.REF is approximatively 2.62 ?A. If the supply voltage V.sub.S is 5.75V, the reference current I.sub.REF is approximatively 18.658 ?A.

[0094] As mentioned above, when the supply voltage V.sub.S rises, the output current from the current path selecting circuit 355 may result in a tiny change of the control voltage V.sub.CTL. In addition, the output current from the current path selecting circuit 357 may directly influence the control voltage V.sub.CTL. The current flowing to the node b and the current flowing to the node c are selected according to the control signal S.sub.CTL. That is, when different supply voltage V.sub.S are provided to the non-volatile memory 300, the extent of the change of the control voltage V.sub.CTL may be different. In addition, the reference current I.sub.REF with different slopes will be generated according to the control signal S.sub.CTL.

[0095] In the above embodiments, the control voltage generation circuit 350 comprises the two current path selecting circuits 355 and 357. It is noted that numerous modifications and alterations may be made while retaining the teachings of the invention. For example, in another embodiment, the control voltage generation circuit 350 is equipped with the current path selecting circuit 355 but not equipped with the current path selecting circuit 357. In addition, the current path selecting circuit 355 of the control voltage generation circuit 350 is activated according to the control signal S.sub.CTL. Consequently, when different supply voltage V.sub.S are provided to the non-volatile memory 300, the change slope of the control voltage V.sub.CTL is lower and the change slope of the reference current I.sub.REF is lower.

[0096] In the first embodiment, the sense amplifiers in the sensing circuit 390 of the non-volatile memory may have diverse types. FIGS. 6A and 6B are schematic circuit diagrams illustrating two types of sense amplifiers used in the sensing circuit of the non-volatile memory according to the first embodiment of the present invention. The structures of the sense amplifiers in the sensing circuit 390 are identical. For succinctness, only one sense amplifier will be described as follows.

[0097] As shown in FIG. 6A, the sense amplifier 381 comprises transistors M.sub.K1?M.sub.K4. The current mirroring terminal of the mirroring circuit 330 is connected with a node w1 of the sense amplifier 381. That is, the second drain/source terminal of the transistor M.sub.B1 is connected with the node w1. The mirroring circuit 330 provides the reference current I.sub.REF to the sense amplifier 381. Moreover, the node w1 is coupled to the data line DL.sub.1 to receive the memory current I.sub.CELL of the selected memory cell.

[0098] The first drain/source terminal of the transistor M.sub.K1 receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.K1 receives a pre-charge signal S.sub.PRE. The second drain/source terminal of the transistor M.sub.K1 is connected with the node w1. The first drain/source terminal of the transistor M.sub.K2 receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.K2 is connected with the node w1. The second drain/source terminal of the transistor M.sub.K2 is connected with the node w2. The first drain/source terminal of the transistor M.sub.K3 is connected with the node w1. The gate terminal of the transistor M.sub.K3 is connected with the node w2. The second drain/source terminal of the transistor M.sub.K3 is connected with the ground terminal GND. The first drain/source terminal of the transistor M.sub.K4 is connected with the node w2. The gate terminal of the transistor M.sub.K4 is connected with the node w1. The second drain/source terminal of the transistor M.sub.K4 is connected with the ground terminal GND. Moreover, the voltage at the node w2 is the data signal D.sub.O1.

[0099] Before a read cycle, the transistor M.sub.K1 is turned on according to the pre-charge signal S.sub.PRE. Consequently, the voltage at the node w1 is maintained at the supply voltage V.sub.S. When the read cycle is started, the transistor M.sub.K1 is turned off according to the pre-charge signal S.sub.PRE. When the read cycle is ended, the transistor M.sub.K1 is turned on again according to the pre-charge signal S.sub.PRE. Consequently, the voltage at the node w1 is maintained at the supply voltage V.sub.S. The rest may be deduced by analogy.

[0100] When the read cycle is started, if the reference current I.sub.REF is higher than the memory cell current I.sub.CELL, the voltage at the node w1 is maintained at the supply voltage V.sub.S. Consequently, the transistor M.sub.K4 is turned on, and the transistor M.sub.K2 is turned off. The voltage at the node w2 is the ground voltage (0V). Consequently, the transistor M.sub.K3 is turned off. Moreover, when the read cycle is ended, the data signal D.sub.O1 is the ground voltage, representing that the data signal D.sub.O1 is in the low logic level state. In other words, the selected memory cell is in the off state.

[0101] When the read cycle is started, if the reference current I.sub.REF is lower than the memory cell current I.sub.CELL, the voltage at the node w1 drops from the supply voltage V.sub.S to the ground voltage (0V). Consequently, the transistor M.sub.K4 is turned off, and the transistor M.sub.K2 is turned on. The voltage at the node w2 is the supply voltage V.sub.S. Consequently, the transistor M.sub.K3 is turned on. Moreover, when the read cycle is ended, the data signal D.sub.O1 is the supply voltage V.sub.S, representing that the data signal D.sub.O1 is in the high logic level state. In other words, the selected memory cell is in the on state.

[0102] As mentioned above, the sense amplifier 381 shown in FIG. 6A can determine the storage state of the selected memory cell according to the relationship between the reference current I.sub.REF and the memory cell current I.sub.CELL. Moreover, in the above sense amplifier 381, it will take a long time for the voltage at the node w1 to drop from the supply voltage V.sub.S to the ground voltage (0V). Consequently, the sensing speed cannot be increased.

[0103] As shown in FIG. 6B, the sense amplifier 38x comprises transistors M.sub.L1?K.sub.L7. The current mirroring terminal of the mirroring circuit 330 is connected with a node w3 of the sense amplifier 38x. That is, the second drain/source terminal of the transistor M.sub.BX is connected with the node w3. The mirroring circuit 330 provides the reference current I.sub.REF to the sense amplifier 38x. Moreover, the node w3 is further coupled to the data line DL.sub.X to receive the memory cell current I.sub.CELL of the selected memory cell.

[0104] The first drain/source terminal of the transistor M.sub.L1 receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.L1 receives the pre-charge signal S.sub.PRE. The second drain/source terminal of the transistor M.sub.L1 is connected with the node w3. The first drain/source terminal of the transistor M.sub.L2 receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.L2 receives a bias voltage VBIAS. The second drain/source terminal of the transistor M.sub.L2 is connected with a node w4. The first drain/source terminal of the transistor M.sub.L3 receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.L3 is connected with the node w4. The second drain/source terminal of the transistor M.sub.L3 is connected with a node w5. The first drain/source terminal of the transistor M.sub.L4 is connected with the node w4. The gate terminal of the transistor M.sub.L4 is connected with the node w3. The first drain/source terminal of the transistor M.sub.L5 is connected with the second drain/source terminal of the transistor M.sub.L4. The gate terminal of the transistor M.sub.L5 is connected with the node w5. The second drain/source terminal of the transistor M.sub.L5 is connected with the ground terminal GND. The first drain/source terminal of the transistor M.sub.L6 is connected with the node w4. The gate terminal of the transistor M.sub.L6 receives an inverted pre-charge signal S.sub.PRE. The second drain/source terminal of the transistor M.sub.L6 is connected with the ground terminal GND. The first drain/source terminal of the transistor M.sub.L7 is connected with the node w5. The gate terminal of the transistor M.sub.L7 is connected with the node w4. The second drain/source terminal of the transistor M.sub.L7 is connected with the ground terminal GND. According to the bias voltage VBIAS, the transistor M.sub.L2 is turned on to provide a current to the node w4. Moreover, the voltage at the node w5 is the data signal D.sub.OX.

[0105] Before the read cycle, the transistor M.sub.L1 is turned on according to the pre-charge signal S.sub.PRE, and the transistor M.sub.L6 is turned on according to the inverted pre-charge signal S.sub.PRE. Consequently, the voltage at the node w3 is maintained at the supply voltage V.sub.S, and the voltage at the node w4 is maintained at the ground voltage (0V). When the read cycle is started, the transistor Mu is turned off according to the pre-charge signal S.sub.PRE, and the transistor M.sub.L6 is turned off according to the inverted pre-charge signal S.sub.PRE. When the read cycle is ended, the transistor Mu is turned on again according to the pre-charge signal S.sub.PRE, and the transistor M.sub.L6 is turned on according to the inverted pre-charge signal S.sub.PRE. Consequently, the voltage at the node w3 is maintained at the supply voltage V.sub.S, and the voltage at the node w4 is maintained at the ground voltage (0V). The rest may be deduced by analogy.

[0106] When the read cycle is started, if the reference current I.sub.REF is higher than the memory cell current I.sub.CELL, the voltage at the node w3 is maintained at the supply voltage V.sub.S. The transistor M.sub.L4 and the transistor M.sub.L5 are turned on. The voltage at the node w4 is maintained at the ground voltage (0V). Consequently, the transistor M.sub.L3 is turned on, and the transistor M.sub.L7 is turned off. The voltage at the node w5 is the supply voltage V.sub.S, and the transistor M.sub.L5 is continuously turned on. When the read cycle is ended, the data signal D.sub.OX is the supply voltage V.sub.S, representing that the data signal D.sub.OX is in the high logic level state. Consequently, the selected memory cell is in the off state.

[0107] When the read cycle is started, if the reference current I.sub.REF is lower than the memory cell current I.sub.CELL, the voltage at the node w3 drops from the supply voltage V.sub.S to the ground voltage (0V). The transistor M.sub.L4 is turned off, and the voltage at the node w4 is charged to the supply voltage V.sub.S. The transistor Mo is turned off, and the transistor M.sub.L7 is turned on. The voltage at the node w5 is the ground voltage (0V). Consequently, the transistor ML 5 is turned off. When the read cycle is ended, the data signal D.sub.OX is the ground voltage, representing that the data signal D.sub.OX is in the low logic level state. Consequently, the selected memory cell is in the on state.

[0108] As mentioned above, the sense amplifier 38x shown in FIG. 6B can determine the storage state of the selected memory cell according to the relationship between the reference current I.sub.REF and the memory cell current I.sub.CELL. In the sense amplifier 38x, if the reference current I.sub.REF is lower than the memory cell current I.sub.CELL, the slight reduction of the voltage at the node w3 may turn off the transistor M.sub.L4. When the node w4 is charged from the ground voltage (0V), if the node w4 rises to the threshold voltage of the transistor M.sub.L7, the transistor M.sub.L7 can be turned on. Consequently, the data signal D.sub.OX is the ground voltage (i.e., in the low logic level state). In other words, in the sense amplifier 38x, it is not necessary to drop the voltage at the node w3 to the ground voltage (0V) and rise the voltage at the node w4 to the supply voltage V.sub.S. Even so, the sense amplifier 38x can correctly generate the data signal D.sub.OX, and the sensing speed of the sense amplifier 38x can be enhanced.

[0109] FIG. 7 is a schematic circuit diagram illustrating a non-volatile memory according to a second embodiment of the present invention. In comparison with the non-volatile memory 300 shown in FIG. 3, the non-volatile memory 700 of the second embodiment further comprises a clamping circuit. The clamping circuit provides a clamping voltage V.sub.CLAMP to control the voltages on the data lines D.sub.L1?DL.sub.X. For succinctness, only the clamping circuit and the sensing circuit 790 are described as follows. The operations of the other circuits are similar to those of the non-volatile memory 300 of the first embodiment, and not redundantly described herein.

[0110] The clamping circuit comprises a clamping voltage generation circuit 750 and (X+1) clamping devices 711?71x and 721. The clamping voltage generation circuit 750 generates the clamping voltage V.sub.CLAMP to the clamping devices 711?71x and 721.

[0111] In this embodiment, the clamping voltage V.sub.CLAMP generated by the clamping voltage generation circuit 750 is changed according to the change of the supply voltage V.sub.S. The clamping voltage generation circuit 750 receives an option signal S.sub.OPT. In addition, the clamping voltage generation circuit 750 generates the clamping voltage Vamp according to the option signal S.sub.OPT. When different supply voltage V.sub.S are provided to the non-volatile memory 700, the value of the clamping voltage V.sub.CLAMP is determined according to the option signal S.sub.OPT.

[0112] The clamping device 721 is constructed in the reference current generator 720. The X clamping devices 711?71x are constructed in the sensing circuit 790. As shown in FIG. 3, the mirroring circuit 330 is directly connected with the reference current generator 340, and the sense amplifiers 381?38x are directly connected with the corresponding data lines DL.sub.1?DL.sub.X In comparison with FIG. 3, the mirroring circuit 330 shown in FIG. 7 is coupled to the reference current generator 340 through the clamping device 721, and the sense amplifiers 781-78x are respectively coupled to the corresponding data lines DL.sub.1?DL.sub.X through the clamping devices 711?71x. For example, the first terminal of the clamping device 711 is connected with the sense amplifier 781. The second terminal of the clamping device 711 is connected with the data line DL.sub.1. The voltage on the data line DL.sub.1 is controlled by the clamping device 711 according to the clamping voltage V.sub.CLAMP. Moreover, the sense amplifiers 781-78x of the sensing circuit 790 may be implemented with the sense amplifiers shown in FIG. 6A or 6B.

[0113] FIG. 8 is a schematic circuit diagram illustrating a clamping circuit in the non-volatile memory according to the second embodiment of the present invention. The (X+1) clamping devices are respectively implemented with (X+1) transistors M.sub.V1?M.sub.VX and M.sub.W. The first drain/source terminal of the transistor M.sub.W is connected with the current input terminal of the mirroring circuit 330. The gate terminal of the transistor M.sub.W receives the clamping voltage V.sub.CLAMP The second drain/source terminal of the transistor M.sub.W is connected with the node a in the current path selecting circuit 340. Furthermore, take the transistor M.sub.V1 for example. The first drain/source terminal of the transistor M.sub.V1 is connected with the sense amplifier 781. The gate terminal of the transistor M.sub.V1 receives the clamping voltage V.sub.CLAMP. The second drain/source terminal of the transistor M.sub.V1 is connected with the data line DL.sub.1. When the gate terminal of the transistor M.sub.V1 receives the clamping voltage V.sub.CLAMP, the voltage on the data line DL.sub.1 is clamped at V.sub.DL1=V.sub.CLAMP?(?{square root over (I.sub.CELL/K)}+V.sub.THN) wherein V.sub.THN is the threshold voltage of the transistor Mai, K is a device parameter of the transistor M.sub.V1, and I.sub.CELL is the cell current of the selected memory cell coupled to the data line DL.sub.1. Similarly, the voltage at node a is approximately equal to V.sub.DL1 when the two transistors M.sub.V1 and M.sub.W are of the same size.

[0114] The clamping voltage generation circuit 750 comprises three transistors M.sub.R1, M.sub.R2, M.sub.R3, two bias circuits 741, 743 and a current path selecting circuit 745.

[0115] The first drain/source terminal of the transistor M.sub.R3 is connected with a node y. The gate terminal of the transistor M.sub.R3 is connected with the ground terminal GND. The second drain/source terminal of the transistor M.sub.R3 is connected with a node z. Similarly, the transistor M.sub.R3 may be equivalently regarded as a resistor.

[0116] The diode-connected transistors M.sub.R2 and M.sub.R3 are serially connected between the node z and the ground terminal GND. That is, the first drain/source terminal of the transistor M.sub.R2 is connected with the node z, the gate terminal of the transistor M.sub.R2 is connected with the node z, the first drain/source terminal of the transistor M.sub.R1 is connected with the second drain/source terminal of the transistor M.sub.R2, the gate terminal of the transistor M.sub.R1 is connected with the second drain/source terminal of the transistor M.sub.R2, and the second drain/source terminal of the transistor M.sub.R1 is connected with the ground terminal GND. Moreover, the voltage at the node z is the clamping voltage V.sub.CLAMP.

[0117] The bias circuit 741 comprises three diode-connected transistors M.sub.O1, M.sub.O2, M.sub.O3 and a current source 742. The diode-connected transistors M.sub.O1, M.sub.O2, M.sub.O3 are serially connected between the supply voltage V.sub.S and a node x. That is, the first drain/source of the transistor M.sub.O1 receives the supply voltage V.sub.S, the gate terminal of the transistor M.sub.O1 is connected with the second drain/source terminal of the transistor M.sub.O1, the first drain/source terminal of the transistor M.sub.O2 is connected with the second drain/source terminal of the transistor M.sub.O1, the gate terminal of the transistor M.sub.O2 is connected with the second drain/source of the transistor M.sub.O2, the first drain/source terminal of the transistor M.sub.O3 is connected with the second drain/source terminal of the transistor M.sub.O2, the gate terminal of the transistor M.sub.O3 is connected with the node x, and the second drain/source terminal of the transistor M.sub.O3 is connected with the node x. The first terminal of the current source 742 is connected with the node x. The second terminal of the current source 742 is connected with the ground terminal GND. For example, the sizes of the transistors M.sub.O1, M.sub.O2 and M.sub.O3 are identical. The current source 742 provides a bias current I.sub.B3. Consequently, the bias voltage V.sub.B3 at the node x is approximatively V.sub.S?3V.sub.SG, i.e., V.sub.SG=(?{square root over (I.sub.B3/K.sub.p)}?V.sub.THP), wherein V.sub.SG is the voltage difference between the source terminal and the gate terminal of the transistor M.sub.O1, K.sub.p is the device parameter of the transistor M.sub.O1, and V.sub.THP is the threshold voltage of the transistor M.sub.O1, and assume that the transistors M.sub.O1 M.sub.O2 and M.sub.O3 have the same threshold voltage V.sub.THP in ideal. In addition, the threshold voltage V.sub.THP is negative.

[0118] The bias circuit 743 comprises three diode-connected transistors M.sub.Q1, M.sub.Q2 and M.sub.Q3. The diode-connected transistors M.sub.Q1, M.sub.Q2, M.sub.Q3 are serially connected between the node y and the ground terminal GND. That is, the first drain/source of the transistor M.sub.Q1 is connected with the node y, the gate terminal of the transistor M.sub.Q1 is connected with the node y, the first drain/source terminal of the transistor M.sub.Q2 is connected with the second drain/source terminal of the transistor M.sub.Q1, the gate terminal of the transistor M.sub.Q2 is connected with the first drain/source of the transistor M.sub.Q2, the first drain/source terminal of the transistor M.sub.Q3 is connected with the second drain/source terminal of the transistor M.sub.Q2, the gate terminal of the transistor M.sub.O3 is connected with the first drain/source of the transistor M.sub.Q3, and the second drain/source terminal of the transistor M.sub.Q3 is connected with the ground terminal GND. Moreover, the bias voltage V.sub.B4 at the node y is determined according to the bias current I.sub.B4. For example, the sizes of the transistors M.sub.Q1, M.sub.Q2 and M.sub.Q3 are identical. Consequently, the bias voltage V.sub.B4 at the node y is approximatively 3V.sub.GS, i.e., V.sub.GS=(?{square root over (I.sub.B4/K.sub.n)}+V.sub.THN) wherein V.sub.GS is the voltage difference between the gate terminal and the source terminal of the transistor M.sub.Q3, K.sub.n is the device parameter of the transistor M.sub.Q3, and V THN is the threshold voltage of the transistor M.sub.Q3, and assume that the transistors M.sub.Q1 M.sub.Q2 and M.sub.Q3 have the same threshold voltage V THN in ideal. In addition, the threshold voltage V THN is positive.

[0119] The current path selecting circuit 745 comprises two current paths 761 and 762. According to the bias voltage V.sub.B3, the current paths 761 and 762 generate corresponding voltage-controlled currents I.sub.T1 and I.sub.T2, respectively. The option signal Sop T is a two-bit signal. The two-bit signal contains option bits S.sub.OPT_A and S.sub.OPT_B. The current path 761 is controlled according to the option bits S.sub.OPT_A. The current path 762 is controlled according to the option bits S.sub.OPT_B. In addition, at least one current path of the current path selecting circuit 745 is activated according to the option signal S.sub.OPT.

[0120] In the current path selecting circuit 745, the transistors M.sub.SWE and M.sub.SWF are served as the switches, and the transistors M.sub.T1 and M.sub.2 are served as the voltage-controlled current sources. The first drain/source of the transistor M.sub.SWE receives the supply voltage V.sub.S. The gate terminal of the transistor M.sub.SWE receives the option bit S.sub.OPT_A. The first drain/source terminal of the transistor M.sub.T1 is connected with the second drain/source terminal of the transistor M.sub.SWE. The gate terminal of the transistor M.sub.T1 receives the bias voltage V.sub.B3. The second drain/source terminal of the transistor M.sub.T1 is connected with the node y.

[0121] The current path 762 of the current path selecting circuit 745 comprises the transistor M.sub.T2 and the transistor M.sub.SWF. The first drain/source terminal of the transistor M.sub.SWF receives the bias voltage V.sub.S. The gate terminal of the transistor M.sub.SWF receives the option bit S.sub.OPT_B. The first drain/source terminal of the transistor M.sub.T2 is connected with the second drain/source terminal of the transistor M.sub.SWF. The gate terminal of the transistor M.sub.T2 receives the bias voltage V.sub.B3. The second drain/source terminal of the transistor M.sub.T2 is connected with the node y.

[0122] In an embodiment, the size of the transistors M.sub.T1 and M.sub.T2 are different. Consequently, the voltage-controlled current I.sub.T1 in the current path 761 and the voltage-controlled current I.sub.T2 in the current path 762 are in a specified proportional relationship. For example, the size of the transistor M.sub.T1 is larger than the size of the transistor M.sub.T2. Consequently, the voltage-controlled current I.sub.T1 is higher than the voltage-controlled current I.sub.T2.

[0123] Moreover, according to the option signal S.sub.OPT, at least one of the two switches M.sub.SWE and M.sub.SWF is controlled to be in a close state. For example, if the option bit S.sub.OPT_A is in the logic level state 0, the transistor M.sub.SWE is turned on (i.e., in the close state), and the current path 761 is activated. Whereas, if the option bit S.sub.OPT_A is in the logic level state 1, the transistor M.sub.SWE is turned off (i.e., in the open state), and the current path 761 is inactivated. For example, if the two option bits of the option bit S.sub.OPT<S.sub.OPT_A, S.sub.OPT_B> is <1, 0>, the current path 762 is activated, but the current path 761 is inactivated. In other words, the switches SWE and SWF are controlled to be in the close state or the open state according to the binary value of the option signal S.sub.OPT.

[0124] In FIG. 8, the current path selecting circuit 745 comprises two current paths. In practice, the number of the current paths in the current path selecting circuit 745 is not restricted. The total number of the current paths in the current path selecting circuit 745 is equal to the number of the option bits in the option signal S.sub.OPT.

[0125] As the supply voltage V.sub.S increases, the output current from the current path selecting circuit 745 results in the increase of the clamping voltage V.sub.CLAMP. According to the option signal S.sub.OPT, the current flowing into the node y is selectively adjusted. Consequently, when different supply voltage V.sub.S are provided to the non-volatile memory 700, the slope of the change of the clamping voltage V.sub.CLAMP is correspondingly adjusted according to the option signal S.sub.OPT.

[0126] As mentioned above, the values of the control signal S.sub.CTL and the selection signal S.sub.SEL may be determined by the engineers according to the characteristics of the memory cells after the non-volatile memory 300 leaves the foundry. When a first value of control signal S.sub.CTL and a second value of selection signal S.sub.SEL are determined, the reference current I.sub.REF is changed at a first specified slope in a range of the supply voltage V.sub.S. Similarly, a third value of the option signal S.sub.OPT is determined by the engineers. Consequently, the clamping voltage V.sub.CLAMP is changed at a second specified slope in a range of the supply voltage V.sub.S. After the non-volatile memory 300 leaves the foundry, the sensing circuit 390 can correctly output the data signals D.sub.O1?D.sub.OX according to the reference current I.sub.REF. For example, the values of the control signal S.sub.CTL and the selection signal S.sub.SEL may be determined according to the characteristics of the on current I.sub.ON and the off current I.sub.OFF of the memory cell.

[0127] In the embodiment of FIG. 3, the memory cell in the memory cell array 112 has the structure of the MTP memory cell shown in FIG. 2A. It is noted that the type of the memory cell is not restricted. For example, in another embodiment, the memory cells in the memory cell array 112 are one-time programmable memory cells, which are also referred as OTP memory cells. In this case, the memory cell array 112 is not equipped with the erase line EL.

[0128] While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.