Open-Collector Variable Gain Amplifier and Method Therefor

Abstract

An amplifier circuit has a variable gain amplifier including an input receiving an input signal and an open-conduction output, and an output stage including an input coupled to the open-conduction output of the variable gain amplifier and an output providing an output signal of the amplifier circuit. The variable gain amplifier has a first transistor and second transistor each having a control input receiving the input signal. A third transistor has a control terminal receiving a control signal and a first conduction terminal coupled to a first conduction terminal of the first transistor and a second conduction terminal being a first terminal of the open-conduction output. A fourth transistor has a control terminal receiving the control signal and a first conduction terminal coupled to a first conduction terminal of the second transistor and a second conduction terminal being a second terminal of the open-conduction output.

Claims

1. An amplifier circuit, comprising: a variable gain amplifier including an input receiving an input signal and an open-conduction output; and an output stage including an input coupled to the open-conduction output of the variable gain amplifier and an output providing an output signal of the amplifier circuit.

2. The amplifier circuit of claim 1, wherein the variable gain amplifier includes: a first transistor including a control terminal coupled for receiving a first component of the input signal; a second transistor including a control terminal coupled for receiving a second component of the input signal; a third transistor including a control terminal coupled for receiving a first component of a control signal and a first conduction terminal coupled to a first conduction terminal of the first transistor and a second conduction terminal being a first terminal of the open-conduction output of the variable gain amplifier; and a fourth transistor including a control terminal coupled for receiving a second component of the control signal and a first conduction terminal coupled to a first conduction terminal of the second transistor and a second conduction terminal being a second terminal of the open-conduction output of the variable gain amplifier.

3. The amplifier circuit of claim 2, wherein the variable gain amplifier further includes: a first resistor coupled between a second conduction terminal of the first transistor and a power supply terminal; a second resistor coupled between a second conduction terminal of the second transistor and the power supply terminal; and a capacitor coupled between the second conduction terminal of the first transistor and the second conduction terminal of the second transistor.

4. The amplifier circuit of claim 1, wherein the output stage includes: a first input transmission line including an input coupled to the first terminal of the open-conduction output of the variable gain amplifier; a second input transmission line including an input coupled to an output of the first input transmission line at a first node; a first gain cell including an input coupled to the first node; and a first output transmission line including an input coupled to an output of the first gain cell and an output providing a first component of the output signal of the amplifier circuit.

5. The amplifier circuit of claim 4, wherein the output stage further includes: a third input transmission line including an input coupled to the second terminal of the open-conduction output of the variable gain amplifier; a fourth input transmission line including an input coupled to an output of the third input transmission line at a second node; a second gain cell including an input coupled to the first node; a termination circuit coupled to an output of the second input transmission line and to an output of the fourth input transmission line; and a second output transmission line including an input coupled to an output of the second gain cell and an output providing a second component of the output signal of the amplifier circuit.

6. The amplifier circuit of claim 5, wherein the termination circuit includes: a first resistor coupled between the output of the second input transmission line and a voltage source; and a second resistor coupled between the output of the fourth input transmission line and the voltage source.

7. A semiconductor device comprising an amplifier circuit, including: a variable gain amplifier including an input receiving an input signal and an open-conduction output; and an output stage including an input coupled to the open-conduction output of the variable gain amplifier and an output providing an output signal of the amplifier circuit.

8. The semiconductor device of claim 7, wherein the variable gain amplifier includes: a first transistor including a control terminal coupled for receiving a first component of the input signal; a second transistor including a control terminal coupled for receiving a second component of the input signal; a third transistor including a control terminal coupled for receiving a first component of a control signal and a first conduction terminal coupled to a first conduction terminal of the first transistor and a second conduction terminal being a first terminal of the open-conduction output of the variable gain amplifier; and a fourth transistor including a control terminal coupled for receiving a second component of the control signal and a first conduction terminal coupled to a first conduction terminal of the second transistor and a second conduction terminal being a second terminal of the open-conduction output of the variable gain amplifier.

9. The semiconductor device of claim 8, wherein the variable gain amplifier further includes: a first resistor coupled between a second conduction terminal of the first transistor and a power supply terminal; a second resistor coupled between a second conduction terminal of the second transistor and the power supply terminal; and a capacitor coupled between the second conduction terminal of the first transistor and the second conduction terminal of the second transistor.

10. The semiconductor device of claim 7, wherein the output stage includes: a first input transmission line including an input coupled to the first terminal of the open-conduction output of the variable gain amplifier; a second input transmission line including an input coupled to an output of the first input transmission line at a first node; a first gain cell including an input coupled to the first node; and a first output transmission line including an input coupled to an output of the first gain cell and an output providing a first component of the output signal of the amplifier circuit.

11. The semiconductor device of claim 10, wherein the output stage further includes: a third input transmission line including an input coupled to the second terminal of the open-conduction output of the variable gain amplifier; a fourth input transmission line including an input coupled to an output of the third input transmission line at a second node; a second gain cell including an input coupled to the first node; a termination circuit coupled to an output of the second input transmission line and to an output of the fourth input transmission line; and a second output transmission line including an input coupled to an output of the second gain cell and an output providing a second component of the output signal of the amplifier circuit.

12. The semiconductor device of claim 11, wherein the termination circuit includes: a first resistor coupled between the output of the second input transmission line and a voltage source; and a second resistor coupled between the output of the fourth input transmission line and the voltage source.

13. The semiconductor device of claim 10, wherein the first input transmission line includes inductive properties.

14. A method of making a semiconductor device comprising an amplifier circuit, including: providing a substrate; forming a variable gain amplifier including an input receiving an input signal and an open-conduction output over the substrate; and forming an output stage including an input coupled to the open-conduction output of the variable gain amplifier and an output providing an output signal of the amplifier circuit over the substrate.

15. The method of claim 14, wherein forming the variable gain amplifier includes: providing a first transistor including a control terminal coupled for receiving a first component of the input signal; providing a second transistor including a control terminal coupled for receiving a second component of the input signal; providing a third transistor including a control terminal coupled for receiving a first component of a control signal and a first conduction terminal coupled to a first conduction terminal of the first transistor and a second conduction terminal being a first terminal of the open-conduction output of the variable gain amplifier; and providing a fourth transistor including a control terminal coupled for receiving a second component of the control signal and a first conduction terminal coupled to a first conduction terminal of the second transistor and a second conduction terminal being a second terminal of the open-conduction output of the variable gain amplifier.

16. The method of claim 14, wherein forming the variable gain amplifier further includes: providing a first resistor coupled between a second conduction terminal of the first transistor and a power supply terminal; providing a second resistor coupled between a second conduction terminal of the second transistor and the power supply terminal; and providing a capacitor coupled between the second conduction terminal of the first transistor and the second conduction terminal of the second transistor.

17. The method of claim 14, wherein forming the output stage includes: providing a first input transmission line including an input coupled to the first terminal of the open-conduction output of the variable gain amplifier; providing a second input transmission line including an input coupled to an output of the first input transmission line at a first node; providing a first gain cell including an input coupled to the first node; and providing a first output transmission line including an input coupled to an output of the first gain cell and an output providing a first component of the output signal of the amplifier circuit.

18. The method of claim 14, wherein forming the output stage further includes: providing a third input transmission line including an input coupled to the second terminal of the open-conduction output of the variable gain amplifier; providing a fourth input transmission line including an input coupled to an output of the third input transmission line at a second node; providing a second gain cell including an input coupled to the first node; providing a termination circuit coupled to an output of the second input transmission line and to an output of the fourth input transmission line; and providing a second output transmission line including an input coupled to an output of the second gain cell and an output providing a second component of the output signal of the amplifier circuit.

19. The method of claim 14, wherein the termination circuit includes: providing a first resistor coupled between the output of the second input transmission line and a voltage source; and providing a second resistor coupled between the output of the fourth input transmission line and the voltage source.

20. The method of claim 17, wherein the first input transmission line includes inductive properties.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIGS. 1a-1c illustrate a semiconductor wafer with a plurality of semiconductor die;

[0006] FIG. 2 illustrates a block diagram for a multi-stage VGA amplifier;

[0007] FIG. 3 illustrates further detail of the variable gain amplifier of FIG. 2;

[0008] FIG. 4 illustrates further detail of the output stage of FIG. 2;

[0009] FIG. 5 illustrates a representation of the input transmission line and output transmission line;

[0010] FIG. 6 illustrates one branch of the input transmission line;

[0011] FIG. 7 illustrates further detail of a gain cell from FIG. 4;

[0012] FIG. 8 illustrates further detail of the termination network from FIG. 4; and

[0013] FIG. 9 illustrates a waveform plot of power gain versus frequency for a conventional VGA and the VGA of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0014] The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term semiconductor die as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

[0015] FIG. 1a shows semiconductor wafer or substrate 100 with a base substrate material 102, such as silicon (Si), silicon carbide (SiC), silicon germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, and all families of III-V and II-VI semiconductor materials for structural support. A plurality of semiconductor die or components 104 is formed on wafer 100 separated by a non-active, inter-die wafer area or saw street 106. Saw street 106 provides cutting areas to singulate semiconductor wafer 100 into individual semiconductor die 104. In one embodiment, semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0016] FIG. 1B shows a cross-sectional view of a portion of semiconductor wafer 100. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more amplifiers, diodes, capacitors, and other circuit elements formed within active surface 110 to implement or be used with analog circuits or digital circuits. In the present embodiment, semiconductor die 104 contains a monolithic multi-stage variable gain amplifier.

[0017] An electrically conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating process, evaporation, or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), titanium (Ti), Platinum (Pt), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer 112 operates as contact pads electrically connected to the circuits on active surface 110.

[0018] In FIG. 1c, semiconductor wafer 100 is singulated through saw street 106 using a scribe, saw blade, or laser cutting tool 118 into individual semiconductor die 104. The individual semiconductor die 104 can be inspected and electrically tested for identification of known good die or known good unit (KGD/KGU) post singulation.

[0019] FIG. 2 illustrates multi-stage amplifier 120 with input terminal 122 and formed on a base substrate material 102. In one example, amplifier 120 can be used in an optical modulator driver for data transmission. Amplifier 120 includes multiple stages for signal conditioning and controlled amplification. Amplifier 120 can be differential or single-ended. Input impedance matching block 124 provides a matching impedance to the input impedance to minimize or eliminate reflections. Input direct current (DC) block 126 uses series capacitors to block or reduce DC components of the input signal V.sub.IN. Emitter follower block 128 provides unity gain, high input impedance, and low output impedance to aid with impedance matching. Amplifier 120 includes voltage gain amplifier feature 130 and output stage or power amplifier 132 to provide output signal V.sub.OUT at terminal 134 as an amplified version of the input signal V.sub.IN having an amplitude controlled by control signals applied to or contained within VGA 130.

[0020] FIG. 3 illustrates further detail of VGA 130. VGA 130 uses variable gain to pre-amplify the input signal V.sub.IN, in a controllable or selectable manner, prior to output stage 132. In the present discussion, the input signal V.sub.IN is a differential input signal with a first + side and a second ? side is applied to the base terminals of transistors 140 and 142 at terminals 146 and 148, respectively. Capacitor 150 is coupled between the emitter terminals of transistors 140 and 142. Resistors 152 and 154 are coupled between the emitter terminals of transistors 140 and 142 and current source 156 referenced to power supply terminal 158 operating at ground potential. The collector terminal of transistor 140 is coupled to the emitter terminal of transistor 160 at node 157. The collector terminal of transistor 142 is coupled to the emitter terminal of transistor 161 at node 159. Capacitor 162 is coupled between the base of transistor 160 and ground terminal 158. Capacitor 163 is coupled between the base of transistor 161 and ground terminal 158. Transistor 164 has a collector coupled to power supply conductor 165 operating at V.sub.CC and an emitter coupled to node 157. Transistor 166 has a collector coupled to power supply conductor 165 and an emitter coupled to node 159. The base terminals of transistors 164 and 166 receive control signal or reference signal V.sub.CTRL to set the gain of VGA 130. The control signal V.sub.CTRL can be fixed within VGA 130 during the manufacturing process or field calibration. For example, control signals V.sub.CTRL received a fixed reference voltage. Alternatively, control signal V.sub.CTRL is selectable during the operation of VGA 130 with a register and/or controllable voltage source. Transistors 140, 142, 160, and 161 operate as a differential cascode pair. The collector terminals of transistors 160 and 161 are, relative to VGA 130, open-collectors or open-conduction outputs 170 and 172.

[0021] FIG. 4 illustrates further detail of output stage 132 coupled to open-collectors 170 and 172 of VGA 130. Output stage 132 includes a plurality of input transmission lines 180a-180d and 182a-182d and a plurality of output transmission lines 184a-184c and 186a-186c. Input transmission lines 180a-180d and 182a-182d and output transmission lines 184a-184c and 186a-186c can be represented as inductor 188 with inductive properties, as shown in FIG. 5. In one embodiment, inductor 188 can have a range of values between 50-200 pico-Henries.

[0022] A plurality of gain cells 190 and 192 is distributed and coupled between input transmission lines 180a-180d and 182a-182d and output transmission lines 184a-184c and 186a-186c, hence output stage 132 is a distributed amplifier. In one embodiment, gain cell 190 can be implemented with an emitter follower configured transistor and differential pair of transistors, see FIG. 7 for further information. Gain cell 190a is coupled between input transmission lines 180a-180b at node 194a and output transmission line 184a at node 196a. Gain cell 190b is coupled between input transmission lines 180b-180c at node 194b and output transmission lines 184a-184b at node 196b. Gain cell 190c is coupled between input transmission lines 180c-180d at node 194c and output transmission lines 184b-184c at node 196c. Gain cell 192a is coupled between input transmission lines 182a-182b at node 200a and output transmission line 186a at node 202a. Gain cell 192b is coupled between input transmission lines 182b-182c at node 200b and output transmission lines 186a-186b at node 202b. Gain cell 192c is coupled between input transmission lines 182c-182d at node 200c and output transmission lines 186b-186c at node 202c.

[0023] Termination network 208 is coupled to the end of input transmission lines 180 and 182, i.e., node 194d and 200d at the output of input transmission lines 180d and 182d. Termination network 208 can be implemented as a first resistor from node 194d to ground and a second resistor from node 200d to ground. Capacitor 210a is coupled between node 194a and ground terminal 158, capacitor 210b is coupled between node 194b and ground terminal 158, and capacitor 210c is coupled between node 194c and ground terminal 158. Capacitor 212a is coupled between node 200a and ground terminal 158, capacitor 212b is coupled between node 200b and ground terminal 158, and capacitor 212c is coupled between node 200c and ground terminal 158. In one embodiment, capacitors 210-212 represent effective input capacitance of gain cells 190-192. Output terminals 134a and 134b provide the differential output signal V.sub.OUT+ and V.sub.OUT? of amplifier 120.

[0024] FIG. 6 shows an example of one branch of open-collector 170, output lines 180a-180d, effective capacitors 210a-210c, and termination network 208. The impedance of termination network 208 is set to be equal to the impedance of input transmission lines 180a-180d.

[0025] FIG. 7 illustrates an implementation of gain cells 190a and 192a. Transistor 210 has a collector coupled to power supply conductor 212 operating at a positive power supply potential such as V.sub.CC, base coupled to node 194a, and emitter coupled through resistor 216 to power supply conductor 218. Transistor 220 has a collector coupled to node 196a and base coupled to node 222 to receive a biasing signal. Transistor 224 has a collector coupled to the emitter of transistor 220 and base coupled to the emitter of transistor 210. Transistor 230 has a collector coupled to power supply conductor 212, base coupled to node 200a, and emitter coupled through resistor 236 to power supply conductor 218. Transistor 240 has a collector coupled to node 202a and base coupled to node 242 to receive a biasing signal. Transistor 244 has a collector coupled to the emitter of transistor 240 and base coupled to the emitter of transistor 230. Resistors 246 and 248 are coupled between nodes 222 and 242. Capacitors 250 and 252 are coupled between nodes 222 and 242. Capacitor 254 is coupled between the emitter of transistor 224 and the emitter of transistor 244. Resistors 256 and 258 are coupled between the emitter of transistor 224 and the emitter of transistor 244. Current source 259 is coupled between resistors 256 and 258 and ground terminal. The input signal V.sub.IN is amplified through gain cells 190a and 192a between nodes 194a, 200a and nodes 196a, 202a. Gain cells 190b, 192b, 190c, and 192c would follow a similar construction.

[0026] FIG. 8 illustrates an implementation of termination network 208. Resistor 260 is coupled between node 194d and node 262. Resistor 264 is coupled between node 200d and node 262. Capacitor 268 is coupled between node 262 and power supply terminal 158. Voltage regulator 272 provides a regulated voltage VREG source from reference voltage V.sub.REF and power supply conductor 274.

[0027] FIG. 9 is a waveform plot of power gain versus frequency for a conventional VGA 278, as described in the background, VGA 130 and output stage 132 from FIG. 2-4. VGA 130 has an open-collector output coupled to output stage 132. The open-collector feature of VGA 130 eliminates the load resistance commonly found in the conventional VGA. VGA 130 and output stage 132 reduce the DC component needed to sufficiently drive the output stage resulting in a lower power consumption within the VGA, greater power transfer to the output stage, and an increase in gain.

[0028] The transistor described herein can be implemented as bipolar devices or metal oxide semiconductor (MOS) devices. For the bipolar transistor, the control terminal is the base and the first and second conduction terminals are the collector and emitter. For the MOS transistor, the control terminal is the gate and the first and second conduction terminals are the drain and source.

[0029] While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.