SYSTEMS AND METHODS FOR MANUFACTURING

Abstract

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.

Claims

1. A method of manufacturing a conductive pattern on a substrate, comprising: depositing a precursor comprising a material on a substrate; directing a beam toward a portion of the precursor on the substrate, wherein the material contacted by the beam is activated and a portion of the substrate proximal to the activated material is removed by the beam; and plating a first conductive material to the activated material.

2. The method of claim 1, wherein the precursor comprises a metal carboxylate.

3. The method of claim 1, wherein the material comprises at least one of Pd, Pt, Au, Ag, Rh, Cu, Ni, or Co, or mixtures thereof.

4. The method of claim 1, wherein the activated material comprises at least one of elemental Pd, Pt, Au, Ag, Rh, Cu, Ni, or Co, or mixtures thereof.

5. The method of claim 4, wherein the step of plating comprises electroless plating the first conductive material to the activated material.

6. The method of claim 5, further comprising the step of electrolytic plating a second conductive material to the first conductive material.

7. The method of claim 1, wherein at least a part of the portion of the substrate is selected from the group of a plastic, a glass, a ceramic, silicon, or a composite thereof.

8. The method of claim 1, wherein the activated material is affixed to the substrate.

9. The method of claim 1, wherein the beam has a resolution of less than 100 μm on the substrate.

10. The method of claim 1, wherein the beam is one of a laser, an electron beam, or a plasma beam.

11. The method of claim 10, wherein the laser is one of a CO.sub.2 laser, an excimer laser, a UV laser, or a YAG laser.

12. The method of claim 11, wherein the laser is pulsed for no more than 1 millisecond intervals.

13. The method of claim 11, wherein the laser has a wavelength selected between 120 nm and 10 μm.

14. The method of claim 13, wherein the laser has a peak pulse of less than 100W.

15. The method of claim 11, wherein the laser has a peak pulse of less than 100W.

16. The method of claim 10, where in the beam has a peak pulse of less than 100W.

17. The method of claim 1, further comprising a step of rinsing the activated material with a solution after the step of directing the beam.

18. The method of claim 17, wherein the rinsing solution comprises an organic solvent, an aqueous solution, or a mixed aqueous solution.

19. The method of claim 1, wherein removal of the portion of substrate proximal to the activated material by the beam forms a recessed pattern in the substrate.

20. The method of claim 19, wherein the recessed pattern has a depth of no more than 25 μm.

21. The method of claim 19, wherein the activated material is affixed to a surface of the recessed pattern.

22. The method of claim 19, wherein the first conductive material is plated in the recessed pattern.

23. The method of claim 1, wherein activating the material and removing a portion of the substrate proximal to the activated material is substantially simultaneous.

24. The method of claim 1, wherein the beam is pulsed at no more than 10 ms intervals.

25. A method of manufacturing a conductive pattern on a substrate, comprising: coating a substrate with a precursor comprising a metal carboxylate; using a beam to simultaneously (i) remove a portion of the substrate to form a recess and (ii) deposit a metal from the metal carboxylate as an electroless plating catalyst in the recess; and plating a first conductive material to the electroless plating catalyst.

26. The method of claim 25, wherein the coating step comprises spray coating the precursor.

27. The method of claim 25, wherein the precursor comprises an ink dissolved in an organic solvent.

28. The method of claim 25, wherein the metal carboxylate is complexed with an electron donor.

29. The method of claim 28, wherein the electron donor is selected from the group consisting of a primary amine, a secondary amine, a tertiary amine, a carbonyl, a sulfonyl, a nitryl, or a phosphoryl.

30. The method of claim 25, further comprising a step of using an organic solvent to remove the precursor from the substrate before the step of plating the first conductive material.

31. The method of claim 25, further comprising a step of electrolytic plating a second conductive material to the first conductive material.

32. The method of claim 25 where in the substrate is treated with a reducing agent.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0060] FIGS. 1A to 1E depict steps in a manufacturing process of the inventive subject matter.

[0061] FIGS. 2 and 3 depict steps in another manufacturing process of the inventive subject matter.

[0062] FIGS. 4A and 4B depict steps in a further manufacturing process of the inventive subject matter.

[0063] FIGS. 5A and 5B depict steps in yet another manufacturing process of the inventive subject matter

[0064] FIG. 6 depicts a conductor assembly of the inventive subject matter.

[0065] FIGS. 7A and 7B depict plating assemblies of the inventive subject matter.

[0066] FIG. 8 another plating assembly of the inventive subject matter.

[0067] FIG. 9A depicts a circuit board produced by steps of the inventive subject matter.

[0068] FIG. 9B depicts an anode used in manufacturing processes of the inventive subject matter.

[0069] FIG. 9C depicts further anodes used in manufacturing processes of the inventive subject matter.

DETAILED DESCRIPTION

[0070] Various methods, systems, and devices for manufacturing conductive circuits are disclosed.

[0071] ('211) Regarding conductive pattern formation by semi-additive process, the present invention relates to methods, systems and devices for manufacturing a portion of an electric circuit. The principles and operations for such methods and systems, according to the present invention, may be better understood with reference to the accompanying description and drawings.

[0072] FIG. 1A depicts step '211-100A of a manufacturing process of the inventive subject matter. Silver layer '211-120 is deposited onto substrate '211-110, typically to a thickness of 0.3 nm, 0.6 nm, less than 1 nm, less than 5 nm, less than 10 nm, or more. For instance, silver layer '211-120 is made from a silver carboxylate solution. The applied silver carboxylate solution is dried and deposits silver carboxylate over the substrate. The silver carboxylate thermally or chemically reduced, or both, to form a very thin (e.g., less than 30 nm, 20 nm, 15 nm, 10 nm, 5 nm, 1 nm, 0.6 nm, or no more than 0.3 nm, etc) and uniform silver layer '211-120 over the substrate surface.

[0073] FIG. 1B depicts step '211-100B of a manufacturing process of the inventive subject matter. Plating resist '211-130 is deposited over silver layer '211-120, and a negative pattern of the circuit is formed by exposing portions of the silver layer, such as exposed portion '211-122. In some embodiments plating resist '211-130 is deposited in the form of the negative pattern, but it is also contemplated that plating resist '211-130 is deposited as a solid layer, and the negative pattern is formed by removing portions of plating resist '211-130 in a separate step (e.g., laser ablation, mechanical ablation, etc).

[0074] FIG. 1C depicts step '211-100C of a manufacturing process of the inventive subject matter. Conductive material '211-140 (e.g., cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, an alloy thereof, etc) is plated onto exposed portion '211-122 of silver layer '211-120. Conductive material '211-140 cannot plate onto portions of silver layer '211-120 that are blocked by plating resist '211-130.

[0075] FIG. 1D depicts step '211-100D of a manufacturing process of the inventive subject matter. Plating resist '211-130 has been removed (e.g., solvent, laser ablation, mechanical ablation, etc), leaving behind conductive material '211-140 plated to exposed portion '211-122 of silver layer '211-120, as well as the rest of silver layer '211-120 deposited on substrate '211-110.

[0076] FIG. 1E depicts step '211-100E of a manufacturing process of the inventive subject matter. The portions of silver layer '211-120 that were not covered or plated to conductive material '211-140 have also been removed (e.g., mechanical ablation, etching, etc), leaving behind substrate '211-110, previously exposed portion '211-122 of silver layer '211-120, and conductive material '211-140 plated to the previously exposed portion '211-122 of silver layer '211-120. It should be appreciated that conductive material '211-140 forms the pattern of an electrical circuit.

[0077] ('223) The present invention further relates to methods, systems and devices for manufacturing conductive patterns on a substrate. The principles and operations for such methods and systems, according to the present invention, may be better understood with reference to the accompanying description and drawings.

[0078] FIG. 2 depicts schematic '223-100 of a manufacturing process of the inventive subject matter. A surface of substrate '223-110 is at least partially coated by precursor '223-120, which carries a metal carboxylate, preferably a carboxylate or at least one of Pd, Pt, Au, Ag, Rh, Cu, Ni, or Co. A beam, preferably a laser, is then directed at precursor '223-120 and substrate '223-110 in the shape of a pattern. Where the beam contacts precursor '223-120 and substrate '223-110, the substrate is removed (e.g., ablated, excised, etc) forming a recess or trench (e.g., recess '223-130), and the metal from the metal carboxylate is activated (e.g., activated metal '223-122) and affixed to a surface of recess '223-130. Conductive material '223-140 is then plated to activated metal '223-122 (e.g., via electroless plating to activated metal '223-122, via electroless plating to activated metal '223-122 followed by electrolytic plating to the conductive material, etc) to form a conductive pattern.

[0079] FIG. 3 depicts an optional step in the manufacturing process of schematic '223-100. After recess '223-130 is formed and the beam has activated the metal in precursor '223-120 to activated metal '223-122, an organic solvent, for example a carboxylate solvent or a solvent present in precursor120, is optionally used to rinse excess or remaining precursor 120 from substrate 110. Conductive material 140 is then plated to activated metal 122 (e.g., electroless plating catalyst) as described in FIG. 1.

[0080] ('086) The inventive subject matter provides conductive layers and methods for manufacture conductive layers, for example as part or all of an electric circuit. Methods of manufacturing a conductive layer include forming a surface topography on a surface of a substrate by laminating a layer of aluminum to the surface of the substrate. The layer of aluminum is removed from the substrate, and a catalyst is deposited over the surface topography of the substrate. A dielectric layer is then formed over the catalyst in a negative pattern of part (or most, or all) of the conductive layer. The part of the conductive layer is then deposited to the catalyst in the negative pattern.

[0081] Typically, the surface of the layer of aluminum interfacing (e.g., abutting, coupled to, adhered to, connected to, etc) with the surface of the substrate includes the surface topography. For example, the surface topography is present on the aluminum surface, and when laminated or pressed to the substrate surface, the surface topography is acquired by the substrate surface, in mirrored/imprinted form. The layer of aluminum is typically removed chemically or mechanically. In some embodiments, laminating the layer of aluminum to the substrate is done by at least one of heat, pressure, or adhesion. The surface topography can also a laminate film (e.g., resin).

[0082] The catalyst is typically at least one of a catalyst for electroless metal deposition, a sputtered catalyst, an aqueous treatment catalyst, for instance traditional tin palladium colloidal catalyst and ionic palladium catalyst, or an ink metal catalyst. The portions of the catalyst covered by the first dielectric layer are removed chemically, mechanically, thermally, photonically or combination processes of two or more thereof. The conductor of the conductive layer is preferably deposited to the catalyst in the negative pattern by electroless plating. The electrolytic plating can be used when the electrolessly deposited metal has enough conductivity. The substrate is preferably a porous dielectric, a semi-porous dielectric, or a non-porous dielectric. The surface topography is preferably a regular or irregular pattern of at least one of cones, spheroids, cylinders, cubes, tetrahedrons, pyramids, pits, ridges, crags, valleys, or waves. In some embodiments, the first surface topography has a maximum arithmetic average roughness (Rmax) of less than 15 microns, preferably less than 7.5 microns. Preferably, the surface topography has an arithmetic average roughness (Ra) less than 5 microns, preferably less than 2.5 microns, more preferably 1.0 micron. The layer of aluminum is typically at most 1000 microns thick.

[0083] In some embodiments, the conductive pattern can be formed on the opposite side of the substrate, either sequentially or simultaneously with the forming of the conductive pattern discussed above. For example, a second surface topography on a surface on the opposite side of the substrate is formed by laminating a layer of aluminum to the surface on the opposite side of the substrate. The layer of aluminum is removed from the opposite side of the substrate, and a catalyst is deposited over the surface topography on the opposite side of the substrate. The second dielectric layer is then formed over the catalyst in a negative pattern of part (or most, or all) of the conductive layer to be formed on the opposite side of the substrate. The conductive layer is then deposited to the catalyst in the negative pattern on the opposite side of the substrate and portions of the catalyst covered by the second dielectric layer.

[0084] It is contemplated that additional conductive patterns can be formed on the same side of the substrate, or on opposite sides of the substrate under the inventive subject matter. Further, where multiple conductive patterns are formed on the substrate, the aluminum layers, surface topographies, lamination methods, aluminum removal methods, catalysts, dielectric layers, negative patterns, or conductors in the conductive layer can be the same, different, or some combination thereof.

[0085] Contemplated methods of manufacturing conductive layers further include forming a surface topography on a surface of a substrate by laminating a layer of aluminum to the surface of the substrate. The layer of aluminum is then removed from the substrate (e.g., mechanically, chemically, etc). A catalyst is then deposited over the surface topography of the substrate, and a seed layer is formed over the first surface, for example by electrochemical deposition. A plating resist layer is then formed over (at least part of) the seed layer in a negative pattern of part (or most, or all) of the conductive layer. Part of the conductive layer is then deposited (e.g., via electrolytic deposition of a conductor) to the seed layer in the negative pattern. The plating resist layer, along with the portions of the seed layer and the catalyst covered by the plating resist layer, are then removed, either sequentially or simultaneously. The plating resist layer is preferably removed chemically, mechanically, thermally, photonically or combination processes or two or more thereof.

[0086] Methods of the inventive subject matter for manufacturing conductive layers include forming conductive layers on opposite sides, or disparate parts, of a common substrate. For example, a surface topography on the surface on the opposite side of the substrate is formed by laminating a layer of aluminum to the surface. The layer of aluminum is then removed from the opposite side of the substrate, and a catalyst is deposited over the surface topography on the opposite side of the substrate. A seed layer is then formed over the surface on the opposite side (e.g., via electrochemical deposition), and a plating resist layer is formed over the seed layer in a negative pattern of part (or most, or all) of the conductive layer. Part of the conductive layer is then deposited to the seed layer in the negative pattern (e.g., via electrolytic deposition). The plating resist layer, and the portions of the seed layer and the catalyst covered by the plating resist layer, are then removed.

[0087] Complete or partial conductive layers manufactured by the described processes, in whole or in part, are contemplated as within the inventive subject matter.

[0088] Devices of the inventive subject matter include cladded laminates having a topography on a dielectric substrate. An aluminum film has a surface that includes the topography. Another aluminum film also has a surface that includes the topography. A dielectric substrate is sandwiched between the topography-bearing surfaces of the two aluminum films, such that a surface of the dielectric substrate acquires the topography. The aluminum films can include a laminate layer (e.g., at the topographical surface), and can be sacrificial (e.g., easily removed mechanically or chemically). The cladded laminate can further include a resin and/or a reinforcement, for example in the laminate layer. Preferably, the resin includes at least one of epoxy, polyimide, cyanate ester, hydrocarbon, fluorinated hydrocarbon, bismaleimide triazine resin, or a combination of two or more thereof. The reinforcement preferably includes at least one of fabric, paper, particle, chopped fiber, or a combination of two or more thereof. The aluminum film (or films) is (are) preferably less than 5000 microns thick, and can be of the same or different thicknesses. The topography is preferably a regular or irregular pattern of at least one of cones, spheroids, cylinders, cubes, tetrahedrons, pyramids, pits, ridges, crags, valleys, or waves.

[0089] FIG. 4A depicts part of workflow '086-100A of an embodiment of the inventive subject matter. Workflow '086-100A includes steps A, B, C, D, and E, and is continued on Figure '086-1B in workflow '086-100B with steps F, G, and H. Starting materials for workflow '086-100A includes aluminum film '086-110, which includes aluminum layer '086-112 with roughened surface '086-114. In some embodiments, roughened surface '086-114 can further have a release treatment. Also roughened surface '086-114 can further include a laminate film. In step A, substrate '086-120 is sandwiched between two pieces of aluminum film '086-110, with roughened surfaces '086-113 and '086-114 facing toward substrate '086-120.

[0090] In step B, the two pieces of aluminum film '086-110 are pressed against substrate '086-120, which impresses the topography of roughened surfaces '086-113 and '086-114 into the surfaces of substrate '086-120. The substrate '086-120 can be used B-stage prepreg and it can be cured during lamination of the two pieces of aluminum film '086-110. In embodiments where roughened surfaces '086-113 and '086-114 further include a laminate film (e.g., resin), aluminum films are further heated or laminated to secure the laminate film to the surface of the substrate.

[0091] In step C, aluminum layers '086-111 and '086-112 of aluminum films '086-110 are removed, for example mechanically (e.g., peeled off) or chemically (e.g., etching). This leaves roughened surfaces '086-122 and '086-124 of the substrate, which bear a substantial (or complete) impression of roughened surfaces '086-113 and '086-114 of aluminum films '086-110. Again, in embodiments where aluminum films '086-110 further include a laminate film at roughened surfaces '086-113 and '086-114, the laminate remains on roughened surfaces '086-122 and '086-124 of substrate '086-120. A treatment (e.g., treatment with grafting agent, coupling agent, microetching agent, or combination of two or more thereof) for final conductor adhesion improvement can be applied over the roughened surfaces '086-122 and '086-124 of substrate '086-120.

[0092] In step D, seed layers '086-132 and '086-134 (e.g., conductive layers for electrolytic deposition) are deposited on roughened surfaces '086-122 and '086-124 of substrate '086-120. The seed layer can be formed by electroless deposition, spattering, PVD or CVD. In case of electroless deposition, a catalyst deposition is conducted prior to electroless deposition. The catalyst can be selected from Pd, Pt, Au, Ag, Rh or mixture of two or more thereof. The catalyst deposition can be used a process with tin or other metal colloid, ionic chelate or organometal. In embodiments where a laminate layer is in roughened surfaces '086-122 and '086-124, it is contemplated that the laminate layer improves the deposition of a seed layer on roughened surfaces '086-122 and '086-124 of the substrate. However, in all cases it is contemplated that the roughened nature of roughened surfaces '086-122 and '086-124 of substrate '086-120 improves deposition of seed layers '086-132 and '086-134, especially in comparison to deposition on substrates with smooth or non-roughened surfaces. Step E continues into Figure '086-1B.

[0093] FIG. 4B depicts workflow '086-100B of an embodiment of the inventive concept, which continues from workflow '086-100A of Figure '086-1A. In step E, plating resist layers '086-142, '086-144, '086-146, and '086-148 are deposited over seed layers '086-132 and '086-134 in a pattern that exposes seed layers '086-132 and '086-134 in a negative image of a desired conductive layer. In some embodiments, the plating resist layer is formed by depositing the plating resist layer, and then removing portions in the shape of the negative patter, for example by etching, ablation, photo exposure, dry film photoresist, etc. In step F, conductive layers '086-152 and '086-154 (e.g. copper for high conductivity) are plated to seed layers '086-132 and '086-134 in the shape of the negative pattern made by the plating resist layers. In preferred embodiments, the conductive layers are deposited by electrolytic plating.

[0094] In step G, plating resist layers '086-142, '086-144, '086-146, and '086-148 are removed (e.g., etching, ablation, photo exposure, etc), and in step H, portions of seed layers '086-132 and '086-134 previously covered by the plating resist layers are removed (e.g., chemically, mechanically, etc). The final product of workflows '086-100A and '086-100B is a substrate with a conductive pattern on two sides, with increased durability and adhesive of the conductive patterns to the substrate by virtue of the roughened surface of substrate '086-120, and in some embodiments by the presence of a laminate layer. As aluminum is of lower cost than other metal materials suited for making film, is easier to work with, and can easily be removed from a substrate surface (e.g., chemically, mechanically), the inventive subject matter is a vast improvement over known methods.

[0095] While FIGS. 4A and 4B are depicted treating the substrate on two opposite sides, it should be appreciated that treating two separate (e.g., disparate) portions of a substrate on the same side, or treating a portion of one side of the substrate with by the teachings herein is further contemplated as within the inventive subject matter.

[0096] FIG. 5A depicts workflow '086-200A, which includes steps A, B, C1, and D1. Starting materials for step A include substrate '086-220, aluminum layer '086-222, and roughened surface layer '086-224, having the surface topography from aluminum layer '086-222 transferred onto roughened surface '086-224. The surface of aluminum layer '086-222 has a roughened topography, which creates an impression of the roughened topography on the surface of substrate '086-220. This starting material is preferably derived by laminating an aluminum clad laminate comprising aluminum layer '086-222 having a roughened surface at an interface/surface '086-224 onto substrate '086-220, for example using heat and pressure. Also roughened surface '086-224 can be transferred during a lamination process utilizing B-stage resin of substrate '086-220.

[0097] In step A, aluminum layer '086-222 is removed from substrate '086-220, leaving behind surface topography of aluminum layer '086-222 on roughened surface '086-224 on the substrate '086-220. In step B, a particle form of catalyst '086-232 (e.g., electroless plating catalyst, sputtered catalyst, metal ink, etc) is deposited over roughened surface layer '086-224. In some embodiments, roughened surface layer '086-224 improves the quality of depositing and binding of catalyst '086-232 to the surface of substrate '086-220. Moreover, the roughened surface of substrate '086-220 impressed by the roughed surface of aluminum layer '086-222 improves the deposition and binding of catalyst '086-232 to the surface of the substrate.

[0098] In step C1, dielectric materials '086-242 and '086-244 are deposited over catalyst '086-232 in a negative pattern forming at least part (or most, or all) of a desired pattern for a conductive layer (e.g., circuit), leaving catalyst '086-232 exposed where the conductive layer is desired. In step D1, conductor '086-252 (e.g., copper) is plated to portions of catalyst '086-232 in the negative pattern created by dielectric materials '086-242 and '086-244. An electrolytic plating can be applied over electroless metal deposited over catalyst '086-232. This process can be repeated to create multilayer conductive patterns. The final product of workflow '086-200A is a substrate with a conductive pattern that has increased durability, forming intricate, micron and sub-micron scale conductive patterns in trenches, cavities, or holes with greatly improved resistance to physical damage during the conductive pattern formation process, and adhesion of the conductive pattern to the substrate by virtue of the roughened surface of substrate '086-220 at roughened surface layer '086-224.

[0099] FIG. 5B depicts workflow '086-200B, which is an alteration of workflow '086-200A, with modification beginning at step C2 and proceeding with steps D2, E, F, and G. In step C2, particle or film format catalyst '086-232 of the substrate '086-220 preceding step C1 in workflow '086-200A is used to deposit conductor '086-262 to roughened surface '086-224 (e.g., via electroless deposition). In step D2, plating resist layers '086-272 and '086-274 are formed over conductor '086-262, leaving a negative pattern exposing conductor '086-262 in the shape of the desired conductive layer (e.g., part of a circuit, most of a circuit, all of a circuit, etc).

[0100] In step E, conductive layer '086-282 is plated to conductor '086-262 (e.g., electrolytic plating) forming the desired pattern for a conductive layer. In step F, plating resist layers '086-272 and '086-274 are removed, and in step G, portions of conductor '086-262 not covered by conductive layer '086-282 are further removed. Optionally, palladium or other catalyst residue under removed conductor '086-262 removing process can be applied. It helps further surface finish process utilizing electrochemical metal deposition. The final product of workflow '086-200B is a substrate with a conductive pattern that has increased durability and adhesion of the conductive pattern to the substrate by virtue of the roughened surface of substrate '086-220 and the presence of roughened surface layer '086-224.

[0101] ('190) Regarding circuits formed on an aluminum heat sink, the present invention further relates to methods, systems and devices for forming a conductive layer with improved heat dissipation and improved adherence between the conductive layer and a heat sink, as well as reducing the thickness of thickness of a base dielectric layer.

[0102] FIG. 6 depicts a conductor composite '190-100 of the inventive subject matter. The base layer '190-140 is substantially (preferably entirely) of aluminum, though other anodizing metals or contemplated. In some embodiments, the base layer is further set on, adhered to, or embedded in a dielectric material (not pictured). Aluminum oxide layer '190-130 (or oxide of another anodized metal) is formed over aluminum layer '190-140, preferably between 50nm and 500μm thick. Catalyst layer '190-120 is then deposited over oxide layer '190-130. Preferably, the combined thickness of catalyst layer '190-120 and aluminum oxide layer '190-130 is minimized to improve thermal conductivity between the aluminum layer and the conductive layer. Catalyst layer '190-120 is then used to deposit conductive layer '190-110, for example by electroless deposition. Further conductive materials can then be plated to the conductive layer, for example by electrolytic deposition.

[0103] ('488) Regarding methods of electrolytic plating by controlling surface area of an anode, the present invention further relates to methods for electrolytic plating a conductor from an anode onto a cathode pattern across a substrate surface, and systems and devices for such plating.

[0104] FIG. 7A depicts plating assembly '488-100A, including anode region '488-110A, blockers '488-120A and '488-122A, and substrate '488-130A having cathode pattern region '488-132A. During electrolytic plating, the metal of anode region '488-110A (e.g., conductive metal, copper, etc) is electrodeposited onto cathode pattern region '488-132A. Anode region '488-110A is perforated by a plurality of openings to decrease the surface area of anode region '488-110A, and Thus, the relative amount of metal of anode region '488-110A available for electrodeposition onto cathode pattern region '488-132A. For example, where cathode pattern region '488-132A requires a greater amount of plated conductive metal (e.g., desired thickness of plated metal greater than 50 nm, 100 nm, 200 nm, 300 nm, 500 nm, surface area of cathode pattern is more than 50%, 60%, 70%, 80%, or 90% of region of substrate, etc), anode region '488-110A has relatively low density of perforations (e.g., less than 30%, 20%, or 10% surface area of region of anode has perforations, etc), such that the surface area of anode region '488-110A available for electrolytic plating (e.g., conductive metal available for electrodeposition) is proportional to the conductive metal desired to be plated to cathode pattern region '488-132A.

[0105] FIG. 7B depicts plating assembly '488-100B, including anode region '488-110B, blockers '488-120B and '488-122B, and substrate '488-130B having cathode pattern region '488-132B. Comparing cathode pattern region '488-132A of Figure '488-1A and cathode pattern region '488-132B of Figure '488-1B, cathode pattern region '488-132B has substantially less surface area (and Thus, need of conductor for electrolytic plating) than cathode pattern region '488-132A. Thus, anode region '488-110B will have a greater number of perforations, resulting in a lower surface area of anode region '488-110B corresponding to cathode pattern region '488-132B, such that the surface area of anode region '488-110B (and metal available for electrolytic plating) is proportional to the surface area of cathode region '488-132B (and conductive metal desired for plating).

[0106] FIG. 8 depicts plating assembly '488-200, including anode '488-210 having anode region '488-212 and anode region '488-214, blockers '488-220, '488-222, and '488-224, and substrate '488-230 having cathode pattern regions '488-232 and '488-234. In this embodiment, cathode region '488-232 has greater surface area, and Thus, greater need for conductive metal for electrolytic plating, than cathode region '488-234. Correspondingly, anode region '488-212 has fewer perforations (e.g., openings, gaps, slits, holes, etc), and Thus, more surface area and metal available for electrolytic plating, than anode region '488-214. Notably, the size and dimension (e.g., shape, width, length, etc) of anode region '488-212 approximately mirrors the size and dimension of cathode pattern region '488-232. Likewise, the size and dimension of anode region '488-214 approximately mirrors the size and dimension of cathode pattern region '488-234.

[0107] FIG. 9A depicts circuit board '488-300A divided into rows '488-311A, '488-312A, '488-313A, and '488-314A, and columns '488-321A, '488-322A, '488-323A, '488-324A, '488-325A, '488-326A, '488-327A, and '488-328A, for a total of 32 cells. Each of the 32 cells corresponds to a region of circuit board '488-300A having various cathode patterns with respective density of cathode pattern, or ratio of cathode pattern surface area to non-cathode pattern surface area in the cell. For example, the cells in column '488-321A have a lower density of cathode pattern than, for example, the cell at column '488-323A, row '488-311A. Likewise, the cell at column '488-323A, row '488-311A has lower density of cathode pattern than, for example, the cells in column '488-326A at rows '488-312A and '488-313A.

[0108] FIG. 9B depicts anode '488-300B divided into rows '488-311B, '488-312B, '488-313B, and '488-314B, and columns '488-321B, '488-322B, '488-323B, '488-324B, '488-325B, '488-326B, '488-327B, and '488-328B, for a total of 32 cells. Each of the 32 cells corresponds to a region of anode '488-300B with perforation patterns (e.g., holes, gaps, openings, channels, slits, combinations thereof, etc) resulting in a gradient of anode material surface area (e.g., density of perforations in each cell, ration of surface area of perforations in a cell to surface area of anode material in the cell, surface area of a cell less surface area of perforations in the cell, etc). For example, the cells in column '488-321B have a lower density of cathode pattern than, for example, the cell at column '488-323B, row '488-311B. Likewise, the cell at column '488-323B, row '488-311B has lower density of cathode pattern than, for example, the cells in column '488-326B at rows '488-312B and '488-313B. Further, the surface area of anode material in each cell of anode '488-300B is proportional to the density of cathode pattern in each cell of circuit board '488-300A.

[0109] Anode '488-300B is placed over circuit board '488-300A in an electrolyte bath for electrolytic plating of the conductor patterns on circuit board '488-300A. Anode '488-300B and circuit board '488-300A are aligned substantially parallel such that each cell of anode '488-300B is aligned (e.g., overlaps) with each corresponding cell of circuit board '488-300A. Such an assembly of circuit board '488-300A, with cells of carrying density of cathode pattern in conjunction with anode '488-300B, with cells of anode surface area proportional to the density of cathode pattern in respective cells of circuit board '488-300A, improves plating uniformity of conductor to cathode patterns of circuit board '488-300A, as well as reducing cost and waste of electrolytic plating materials.

[0110] FIG. 9C depicts array '488-300C of perforated anode regions '488-330, '488-340, and '488-350. Each anode region includes anode material '488-332, '488-342, and '488-352 (e.g., conductive metal, copper, etc), respectively, with each region having a pattern of perforations '488-334, '488-344, and '488-354 (hexagonal holes). The shade of each anode region corresponds with a pattern of perforations present in each cell of anode '488-300B. For example, anode region '488-330 is representative of a pattern in row '488-321B of anode '488-300B, anode region '488-340 is representative of a pattern in the cell at column '488-323B, row '488-311B, and anode region '488-350 is representative of a pattern in the cells in column '488-326B at rows '488-312B and '488-313B.

[0111] The following discussion provides many example embodiments of the inventive subject matter. Although each embodiment represents a single combination of inventive elements, the inventive subject matter is considered to include all possible combinations of the disclosed elements. Thus, if one embodiment comprises elements A, B, and C, and a second embodiment comprises elements B and D, then the inventive subject matter is also considered to include other remaining combinations of A, B, C, or D, even if not explicitly disclosed.

[0112] As used herein, and unless the context dictates otherwise, the term “coupled to” is intended to include both direct coupling (in which two elements that are coupled to each other contact each other) and indirect coupling (in which at least one additional element is located between the two elements). Therefore, the terms “coupled to” and “coupled with” are used synonymously.

[0113] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0114] Unless the context dictates the contrary, all ranges set forth herein should be interpreted as being inclusive of their endpoints, and open-ended ranges should be interpreted to include only commercially practical values. Similarly, all lists of values should be considered as inclusive of intermediate values unless the context indicates the contrary.

[0115] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.

[0116] All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.

[0117] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified Thus, fulfilling the written description of all Markush groups used in the appended claims.

[0118] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C . . . and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.