HIGH SPEED PROTECTION FOR PHASE BALANCER WITH ZIG-ZAG TRANSFORMER

Abstract

A zero-sequence current balancer for a controlling zero-sequence current in a three-phase power system includes a zig-zag transformer coupled to the three-phase power system, an inverter coupled to an output of the zig-zag transformer, and at least one of: (i) a clamp device operating as a normally open switch, the clamp device being provided in between the output of the zig-zag transformer and a neutral conductor (which may be grounded) and being connected in parallel with the inverter, and (ii) a load-break switch provided between the output end of the zig-zag transformer and an input of inverter. A controller is structured and configured to detect a fault condition in the three-phase power system, and in response cause at least one of the closing of the clamp device or the opening of the load-break switch in order to protect the system.

Claims

1. A zero-sequence current balancer for a controlling zero-sequence current in a three-phase power system, comprising: a zig-zag transformer coupled to the three-phase power system; an inverter coupled to an output of the zig-zag transformer; and at least one of: (i) a clamp device operating as a normally open switch, the clamp device being provided in between the output of the zig-zag transformer and a neutral conductor and being connected in parallel with the inverter, and (ii) a load-break switch provided between the output end of the zig-zag transformer and an input of inverter.

2. The zero-sequence current balancer according to claim 1, comprising both the clamp device and the load-break switch.

3. The zero-sequence current balancer according to claim 1, comprising the clamp device but not the load-break switch.

4. The zero-sequence current balancer according to claim 1, comprising the load-break switch but not the clamp device.

5. The zero-sequence current balancer according to claim 1, further comprising a controller coupled to the at least one of the clamp device and the load-break switch, and structured and configured to control operation of the at least one of the clamp device and the load-break switch responsive to detection of a fault condition in the three-phase power system.

6. The zero-sequence current balancer according to claim 5, wherein the zero-sequence current balancer includes the clamp device, and wherein the clamp device comprises one or more semiconductor devices.

7. The zero-sequence current balancer according to claim 6, wherein the one or more semiconductor devices comprises a thyristor.

8. The zero-sequence current balancer according to claim 7, wherein the thyristor comprises an antiparallel thyristor.

9. The zero-sequence current balancer according to claim 7, wherein the thyristor comprises a silicon controlled rectifier.

10. The zero-sequence current balancer according to claim 6, wherein the controller and the clamp device are structured and configured such that the controller will cause the clamp device to close responsive to a current and/or a voltage in the zero-sequence current balancer exceeding a threshold level.

11. The zero-sequence current balancer according to claim 6, wherein the controller and the clamp device are structured and configured such that the controller will cause the clamp device to close within <2 ms of detection of the fault condition.

12. The zero-sequence current balancer according to claim 5, wherein the zero-sequence current balancer includes the clamp device, and wherein the clamp device comprises metal-oxide-semiconductor device, a very high-speed mechanical contactor, or an explosive charge.

13. The zero-sequence current balancer according to claim 5, wherein the zero-sequence current balancer includes the clamp device, wherein the clamp device comprises a very high-speed mechanical contactor made from Micro Electro-Mechanical Switches (MEMS).

14. The zero-sequence current balancer according to claim 5, wherein the zero-sequence current balancer includes the load-break switch, and wherein the load-break switch is a single-phase semiconductor switch.

15. The zero-sequence current balancer according to claim 5, wherein the zero-sequence current balancer includes the load-break switch, and wherein the load-break switch is structured and configured to carry a rated current of the inverter.

16. The zero-sequence current balancer according to claim 5, wherein the zero-sequence current balancer includes the load-break switch, and wherein the load-break switch comprises a Thyristor structured and configured to block a voltage present during a grid fault in the three-phase power system.

17. A method for a controlling zero-sequence current in a three-phase power system, the method comprising: providing: (i) a zig-zag transformer coupled to the three-phase power system, (ii) an inverter coupled to an output of the zig-zag transformer, and (iii) at least one of: (a) a clamp device operating as a normally open switch, the clamp device being provided in between the output of the zig-zag transformer and a neutral conductor and being connected in parallel with the inverter, and (b) a load-break switch provided between the output end of the zig-zag transformer and an input of inverter; detecting a fault condition in the three-phase power system; and responsive to detecting the fault condition, causing at least one of closing of the clamp device or opening of the load-break switch.

18. The method according to claim 17, comprising providing both the clamp device and the load-break switch.

19. The method according to claim 17, comprising the providing clamp device but not the load-break switch.

20. The method according to claim 17, comprising providing the load-break switch but not the clamp device.

21. The method according to claim 17, comprising providing the clamp device, wherein the clamp device comprises one or more semiconductor devices.

22. The method according to claim 21, wherein the one or more semiconductor devices comprises a thyristor.

23. The method according to claim 22, wherein the thyristor comprises an antiparallel thyristor.

24. The method according to claim 22, wherein the thyristor comprises a silicon controlled rectifier.

25. The method according to claim 17, comprising providing the clamp device, wherein the fault condition includes a current and/or a voltage in the zero-sequence current balancer exceeding a threshold level.

26. The method according to claim 17, comprising providing the clamp device, wherein responsive to the fault condition the clamp device is closed within <2 ms of detection of the fault condition.

27. The method according to claim 17, comprising providing the load-break switch, wherein the load-break switch is a single-phase semiconductor switch.

28. The method according to claim 17, comprising providing the load-break switch, wherein the load-break switch is structured and configured to carry a rated current of the inverter.

29. The method according to claim 17, comprising providing the load-break switch, wherein the load-break switch comprises a Thyristor structured and configured to block a voltage present during a grid fault in the three-phase power system.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A full understanding of the invention can be gained from the following description of the preferred embodiments when read in conjunction with the accompanying drawings in which:

[0013] FIG. 1 is a schematic diagram of a prior art phase balancing system that utilizes a zig-zag grounding transformer for minimizing zero-sequence currents;

[0014] FIG. 2 is a schematic diagram of a zero-sequence current balancer according to a first embodiment of the disclosed concept;

[0015] FIG. 3 is a schematic diagram of a zero-sequence current balancer according to a second embodiment of the disclosed concept; and

[0016] FIG. 4 is a schematic diagram of a zero-sequence current balancer according to a third embodiment of the disclosed concept.

DETAILED DESCRIPTION OF THE INVENTION

[0017] FIG. 2 is a schematic diagram of a zero-sequence current balancer 55 according to a first embodiment of the disclosed concept that is coupled to the phase lines a, b, and c and the neutral conductor (shown as equivalent to the ground connection in this case for ease of illustration) of a three-phase, four wire power system. Zero-sequence current balancer 55 is similar to zero-sequence current balancer 5, and like parts are labelled with like refence numerals. However, in this first embodiment, as described in greater detail below, zero-sequence current balancer 55 differs from zero-sequence current balancer 5 in that it further includes a high-speed clamp device to bypass inverter 30. More specifically, as shown in FIG. 2, zero-sequence current balancer 55 includes a four terminal zig-zag transformer 10, a main contactor 15 inserted between zig-zag transformer 10 and phase a, phase b, and phase c of the three-phase, four wire power system, an inverter 30 coupled to the output end of zig-zag transformer 10, a real power injector 40 coupled to inverter 30 and phase a, phase b, and phase c of the three-phase, four wire power system, a clamping device 60 that is provided in parallel with inverter 30 between the output end of zig-zag transformer 10 and the neutral conductor (shown as equivalent to the ground connection in this case for ease of illustration) to enable selective bypass of inverter 30, and a controller 50 structured and configured for controlling operation of the components of zero-sequence current balancer 55.

[0018] Clamp device 60 functions as a normally-open switch, which is closed when the current and/or voltage reaches a certain predetermined level (the voltage leads the current in time due to the inductive nature of the transformer, and may generally be achieved with semiconductor device(s) to achieve the speed required to bypass inverter 30 before the current can rise within inverter 30 to a level that would damage the semiconductors in inverter 30. The rate-of-rise of the current in inverter 30 is limited by the impedance of zig-zag transformer 10. As a result, there is a small window of time, e.g., <2 ms in the exemplary embodiment (or in the range of 1-2000 ?s in one non-limiting particular implementation), during which this bypass can be achieved. In particular, the fault can be readily detected by the controller 50, which generally has high-bandwidth measurements of the terminal voltage and current needed for the control of inverter 30. The most likely embodiment of clamp device 60 would be an antiparallel thyristor in a triac-like arrangement. This would allow the clamp to block voltage in either direction when untriggered and carry current in either direction when triggered. Thyristor devices, specifically the subtype referred to as Silicon Controlled Rectifiers (SCRs), are commercially available with very high voltage and peak current ratings, and a much lower cost when compared to the semiconductors used in inverter 30. Alternate embodiments of clamp device 60 may be based on metal-oxide-semiconductor technology, such as MOSFETs, IGBTs, and HEMT-FETs; or a very high-speed mechanical contactor such as those made from Micro Electro-Mechanical Switches (MEMS) or those utilizing explosive charges.

[0019] FIG. 3 is a schematic diagram of a zero-sequence current balancer 65 according to a second embodiment of the disclosed concept that is coupled to the phase lines a, b, and c and the neutral conductor (shown as equivalent to the ground connection in this case for ease of illustration) of a three-phase, four wire power system. Zero-sequence current balancer 65 is similar to zero-sequence current balancer 5, and like parts are labelled with like refence numerals. However, in this second embodiment, as described in greater detail below, zero-sequence current balancer 65 differs from zero-sequence current balancer 5 in that it further includes a single-phase load-break switch (normally closed) that interrupts the current flowing into inverter 30 and blocks the applied voltage (by opening the load-break switch). More specifically, as shown in FIG. 3, zero-sequence current balancer 65 includes a four terminal zig-zag transformer 10, a main contactor 15 inserted between zig-zag transformer 10 and phase a, phase b, and phase c of the three-phase, four wire power system, an inverter 30 coupled to the output end of zig-zag transformer 10, a real power injector 40 coupled to inverter 30 and phase a, phase b, and phase c of the three-phase, four wire power system, a load-break switch 70 provided in series between the output end of zig-zag transformer 10 and the input of inverter 30 (to block applied voltage), and a controller 50 structured and configured for controlling operation of the components of zero-sequence current balancer 65. Load-break switch 70 in this embodiment would only need to carry the rated current of inverter 30, not the more extreme fault current, but similar to clamp device 60, may utilize low-cost Thyristor or other semiconductor technology able to block the high voltage present during the grid fault.

[0020] FIG. 4 is a schematic diagram of a zero-sequence current balancer 75 according to a third embodiment of the disclosed concept that is coupled to the phase lines a, b, and c and the neutral conductor (shown as equivalent to the ground connection in this case for ease of illustration) of a three-phase, four wire power system. Zero-sequence current balancer 75 is similar to zero-sequence current balancer 5, and like parts are labelled with like refence numerals. However, in this third embodiment, as described in greater detail below, zero-sequence current balancer 75 differs from zero-sequence current balancer 5 in that it further includes both a high-speed clamp device to bypass inverter 30 as described in connection with FIG. 2, and a load-break switch 70 for blocking voltages to inverter as described in connection with FIG. 3. Either of the two devices, clamp device 60 or load switch 70, can individually protect inverter 30. However, only clamp device 60 would allow zig-zag transformer 10 to contribute to the short-circuit current of the grid, potentially helping the power utility's overall system protection scheme. Carrying both devices allows controller 50 to be programmed to specify the behavior in the event of detected fault, based on the specific system requirements, which may change over time.

[0021] While specific embodiments of the invention have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of disclosed concept which is to be given the full breadth of the claims appended and any and all equivalents thereof.