METHOD OF CONTROLLING BOW IN A SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR DEVICE

Abstract

A method of controlling bow in a layered semiconductor structure comprises the steps of: providing a layered semiconductor structure comprising a first layer of III-nitride semiconductor material on a substrate, the layered semiconductor structure having a first bow, and forming a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material, in which the layered semiconductor structure comprising the porous region has a second bow different from the first bow. A semiconductor structure having controllable bow comprises a first layer of III-nitride semiconductor material on a substrate, and a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material. The layered semiconductor structure comprising the porous region has a second bow, and the second bow is tunable by tuning a porosity and/or thickness of the porous region.

Claims

1. A method of controlling bow in a layered semiconductor structure, the method comprising the steps of: providing a layered semiconductor structure comprising a first layer of III-nitride semiconductor material on a substrate, the layered semiconductor structure having a first bow; and forming a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material, in which the layered semiconductor structure comprising the porous region has a second bow different from the first bow.

2. A method according to claim 1, in which the bow of the semiconductor structure is the deviation of the centre point of the median surface of a free, un-clamped semiconductor structure from a reference plane.

3. A method according to claim 2, in which the reference plane is defined by three corners of an equilateral triangle.

4. A method according to claim 1, in which the second bow is closer to zero bow than the first bow.

5. A method according to claim 1, in which the first bow is a concave bow, and in which the second bow is less concave than the first bow.

6. A method according to claim 1, in which the first bow is a convex bow, and in which the second bow is less convex than the first bow.

7. A method according to claim 1, in which the second bow is between 1% and 80% less than the first bow, preferably between 3% and 70% less than the first bow, particularly preferably between 8% and 65% less than the first bow.

8. A method according to claim 1, in which the second bow is between 5 ?m and 150 ?m less than the first bow, preferably between 10 ?m and 100 ?m less than the first bow, particularly preferably between 25 ?m and 50 ?m less than the first bow.

9. A method according to claim 1, in which the overall porosity of the semiconductor structure positioned on the substrate, including the first III-nitride layer and the porous region, is between 5% and 90% porous, or between 10% and 80% porous, or between 20% and 70% porous

10. A method according to claim 1, including the step of tuning the second bow, in which tuning the second bow comprises tuning at least one of the porosity or the thickness of the porous region

11. A method according to claim 1, wherein the tuning the second bow comprises compensating the first bow that results from the substrate and the first layer of III-nitride material having different thermal coefficients of expansion.

12. A method according to claim 1, in which the step of forming a porous layer of III-nitride semiconductor material over the first layer of III-nitride semiconductor material comprises depositing an n-doped region of III-nitride material over the first layer of semiconductor material, and electrochemically porosifying the n-doped region of III-nitride material to form the porous region of III-nitride material.

13. A method according to claim 1, comprising the step of forming the porous region of III-nitride material by electrochemical porosification through a non-porous layer of III-nitride material, such that the non-porous layer of III-nitride material forms a non-porous intermediate layer over the porous region.

14. A method according to claim 1, in which the porous region has a porosity of between 10% and 80% porous.

15. A method according to claim 1, in which the porous region has a thickness of between 100 nm and 10000 nm, preferably at least 1000 nm.

16. A method according to claim 1, in which the porous region is a continuous porous layer having a uniform porosity, which extends over the lateral width of the first layer of III-nitride material.

17. A method according to claim 1, in which the porous region extends over only a portion of the lateral width of the first layer of III-nitride material, for example in which the porous region is patterned on the first layer.

18. A method according to claim 1, in which the porous region of III-nitride material comprises a porous layer of III-nitride material.

19. A method according to claim 1, in which the porous region of III-nitride material comprises a stack of multiple porous layers of III-nitride material.

20. A method according to claim 19, in which the stack of porous layers is a stack of alternating porous and non-porous layers, preferably in which the stack comprises between 2 and 100 pairs of porous and non-porous layers.

21. A method according to claim 20, in which the porous layers in the stack have a thickness of between 5 nm and 200 nm, and the non-porous layers have a thickness of between 2 nm and 180 nm.

22. A method according to claim 1, in which the first III-nitride layer contains one or more layers or stacks of the following in any sequence: GaN, Al.sub.xGa.sub.1-xN in which x=0-1, or In.sub.yGa.sub.1-yN in which y=0-1.

23. A method according to claim 1, in which the substrate is one of: sapphire, silicon, silicon carbide, GaN, AlN, InGaN bulk, oxidized & porous silicon or glass/fused silica.

24. A method of manufacturing a semiconductor device, the method comprising the steps of manufacturing a layered semiconductor structure having a porous region according to claim 1; and forming, over the porous region, a semiconductor device structure.

25. A method according to claim 24, comprising the step of forming a second layer of III-nitride material over the porous region before forming the semiconductor device structure on the second layer of III-nitride material.

26. A method according to claim 24, in which the semiconductor structure is an LED, a mini-LED, a micro-LED, a power electronics device, or an RF electronics device.

27. A semiconductor structure having controllable bow comprising: a first layer of III-nitride semiconductor material on a substrate; and a porous region of III-nitride semiconductor material over the first layer of III-nitride semiconductor material, in which the layered semiconductor structure comprising the porous region has a second bow, and wherein the second bow is tunable by tuning a porosity and/or thickness of the porous region.

28. A semiconductor structure according to claim 27, wherein the substrate and the first layer of III-nitride semiconductor material have different thermal coefficients of expansion.

29. A semiconductor structure according to claim 27, wherein the first III-nitride layer contains one or more layers or stacks of the following in any sequence: GaN, Al.sub.xGa.sub.1-xN in which x=0-1, or In.sub.yGa.sub.1-yN in which y=0-1.

30. A semiconductor structure according to claim 27, wherein the porous region comprises one or more porous layers or stacks of the following in any sequence: GaN, Al.sub.xGa.sub.1-xN in which x=0-1, or In.sub.yGa.sub.1-yN in which y=0-1.

31. A semiconductor structure according to claim 27, comprising a second layer of III-nitride material over the porous region.

32. A semiconductor structure according to claim 27, wherein the second III-nitride layer contains one or more layers or stacks of the following in any sequence: GaN, Al.sub.xGa.sub.1-xN in which x=0-1, or In.sub.yGa.sub.1-yN in which y=0-1.

33. A semiconductor structure according to claim 27, in which the porous region has a porosity of between 10% and 80% porous.

34. A semiconductor structure according to claim 27, in which the overall porosity of the semiconductor structure positioned on the substrate, including the first III-nitride layer and the porous region, is between 5% and 90% porous, or between 10% and 80% porous, or between 20% and 70% porous

35. A semiconductor structure according to claim 27, in which the porous region has a thickness of between 100 nm and 10000 nm, preferably at least 1000 nm.

36. A semiconductor structure according to claim 27, in which the porous region is a continuous porous layer having a uniform porosity, which extends over the lateral width of the first layer of III-nitride material.

37. A semiconductor structure according to claim 27, in which the porous region extends over only a portion of the lateral width of the first layer of III-nitride material, for example in which the porous region is patterned on the first layer.

38. A semiconductor structure according to claim 27, in which the porous region of III-nitride material comprises a stack of porous and non-porous layers of III-nitride material.

39. A semiconductor device, comprising: a semiconductor structure having a porous region according to claim 27; and a semiconductor device structure over the porous region of III-nitride material.

40. A semiconductor device according to claim 39, comprising a second layer of III-nitride material between the porous region and the semiconductor device structure.

41. A semiconductor device according to claim 39, in which the semiconductor structure is an LED, a mini-LED, a micro-LED, a power electronics device, or an RF electronics device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0107] Specific embodiments of the invention will now be described with reference to the figures, in which:

[0108] FIG. 1A is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate and a first III-nitride layer;

[0109] FIG. 1B is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate and a first III-nitride layer, with a convex bow;

[0110] FIG. 1C is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate and a first III-nitride layer, with a concave bow;

[0111] FIG. 2A is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate, a first III-nitride layer and a porous region over the first III-nitride layer;

[0112] FIG. 2B is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate, a first III-nitride layer and a porous region over the first III-nitride layer, with a convex bow;

[0113] FIG. 2C is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate, a first III-nitride layer and a porous region over the first III-nitride layer, with a concave bow;

[0114] FIG. 3A is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate, a first III-nitride layer, a porous region over the first III-nitride layer, and further epitaxial semiconductor layers or structures formed over the porous region;

[0115] FIG. 3B is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate, a first III-nitride layer, a porous region over the first III-nitride layer, and further epitaxial semiconductor layers or structures formed over the porous region, with a convex bow;

[0116] FIG. 3C is a schematic side-on cross-section of a layered semiconductor structure comprising a substrate, a first III-nitride layer, a porous region over the first III-nitride layer, and further epitaxial semiconductor layers or structures formed over the porous region, with a concave bow;

[0117] FIG. 4 shows the reduction in wafer bow on formation of a porous region, measured for a variety of different layered semiconductor structures according to the present invention;

[0118] FIG. 5A shows an example Bow map of a GaN layered semiconductor template before porosification of the porous region;

[0119] FIG. 5B shows a Bow map of the structure of FIG. 5A, after porosification of the porous region.

[0120] FIGS. 1A, 1B and 1C schematically illustrate three different cases of a first III-nitride layer 20 formed on a substrate 10.

[0121] In FIG. 1A, the wafer bow is zero, or close to zero, so the wafer, in other words the semiconductor structure consisting of the substrate and the first III-nitride layer, is flat.

[0122] In FIG. 1B, the wafer has a convex bow, such that the centre of the wafer is curved upwards to a height above the edges of the wafer. In this configuration, the upper surface of the wafer is under tensile stress. This means that the wafer does not sit flat upon a flat surface, as is desirable for further processing and further overgrowth.

[0123] The curvature, or bow, of the wafer, can be quantified by measuring the height profile across the wafer and calculating the bow according to conventional techniques.

[0124] In FIG. 1C, the wafer has a concave bow, such that the edges of the wafer are curved upwards to a height above the centre of the wafer. In this configuration, the upper surface of the wafer is under compressive stress. This means that the wafer does not sit flat upon a flat surface, as is desirable for further processing and further overgrowth.

[0125] FIGS. 2A, 2B and 2C illustrate the structures of FIGS. 1A, 1B and 1C after formation of porous regions 30 (illustrated as porous layers) above the first III-nitride layers 10. Non-porous intermediate layers 40 of III-nitride material are positioned over the porous region 30.

[0126] As described above, electrochemical porosification of the porous region 30 is preferably carried out by porosification of n-doped III-nitride material through the undoped, non-porous intermediate layer 40. The intermediate layer 40 then forms a smooth surface for overgrowth of further epitaxial layers or device structures.

[0127] As described above, the formation of the porous region 30 in the semiconductor structure reduces the stress in the layered structure, and reduces the curvature or bow of the overall structure. Thus the bow of the structures in FIGS. 2B and 2C is advantageously less than that of the corresponding structures in FIGS. 1B and 1C. The structure in FIG. 2A also advantageously experiences a reduction in the stresses and strains in the semiconductor structure relative to FIG. 1A.

[0128] FIGS. 3A, 3B and 3C illustrate the structures of FIGS. 2A, 2B and 2C after formation of further epitaxial semiconductor structures or layers over the non-porous intermediate layers 40.

[0129] These further epitaxial semiconductor structures or layers may comprise a second layer of III-nitride material, and/or a semiconductor device structure. Whatever layer or device structure is overgrown will advantageously benefit from the reduced stress and bow of the underlying layered semiconductor structure. This has benefits both in ease of manufacturing and processing steps during device growth, and in superior performance of the resulting devices, as the resulting devices do not contain stresses and strains inherited from growth over a stressed underlying structure.

[0130] The stress and bow reduction that is obtained in the structures after formation of the porous region may be controlled by varying, or tuning, the size and shape, thickness and/or porosity of the porous region. For example the size and shape of the porous region(s) may be controlled by controlling epitaxial deposition of the n-doped region(s) that will be porosified, and the pore size and % porosity of the porous region(s) may be controlled by varying the electrochemical porosification parameters and the charge carrier concentration of the porous region, as described in international patent applications PCT/GB2017/052895 (published as WO2019/063957) and PCT/GB2019/050213 (published as WO2019/145728).

[0131] FIG. 4 shows the reduction in wafer bow on formation of a porous region, measured for a variety of different layered semiconductor structures according to the present invention. For all structures tested, the layered semiconductor structure experienced a reduction in wafer bow following formation of the porous region. The smallest wafer bow reduction was a 3% reduction, corresponding to a reduction of around 7 ?m of wafer bow. The largest wafer bow reduction was a 31% reduction in wafer bow, corresponding to a reduction of around 75 ?m of wafer bow. This clearly demonstrates that the formation of a porous layer of III-nitride material over a first III-nitride layer on a substrate, leads to a reduction in the stress and resulting wafer bow of the semiconductor structure.

[0132] FIG. 5A shows an example Bow map of a GaN layered semiconductor template before porosification of the porous region, while FIG. 5B shows a Bow map of the structure of FIG. 5A, after porosification of the porous region. Comparison of these bow maps shows that after porosification, the wafer (consisting of a GaN layer on a substrate) was significantly less bowed.