SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Abstract

A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

Claims

1. A semiconductor device, comprising: a substrate having a flash memory region and a logic device region; at least one logic transistor disposed in the logic device region; and at least one flash memory transistor disposed in the flash memory region, wherein the at least one flash memory transistor comprises a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate, respectively.

2. The semiconductor device according to claim 1, wherein the at least one logic transistor comprises a metal gate.

3. The semiconductor device according to claim 2, wherein the metal gate and the metal select gate have the same gate structure.

4. The semiconductor device according to claim 2, wherein each of the metal gate and the metal select gate comprises a high-k gate dielectric layer and a conductive gate electrode.

5. The semiconductor device according to claim 2, wherein a top surface of the metal gate is coplanar with a top surface of the metal select gate.

6. The semiconductor device according to claim 4 further comprising: two charge storage structures disposed on the two opposite sidewalls of the metal select gate, respectively.

7. The semiconductor device according to claim 6, wherein each of the two charge storage structures comprises an oxide-nitride-oxide (ONO) storage structure.

8. The semiconductor device according to claim 6, wherein the two charge storage structures are in direct contact with the high-k gate dielectric layer.

9. The semiconductor device according to claim 1, wherein the two memory gates are polysilicon gates.

10. The semiconductor device according to claim 1 further comprising: two source/drain doping regions in the substrate and adjacent to the two memory gates, respectively.

11. A method for forming a semiconductor device, comprising: providing a substrate having a flash memory region and a logic device region; forming at least one logic transistor in the logic device region; and forming at least one flash memory transistor in the flash memory region, wherein the at least one flash memory transistor comprises a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

12. The method according to claim 11, wherein the at least one logic transistor comprises a metal gate.

13. The method according to claim 12, wherein the metal gate and the metal select gate have the same gate structure.

14. The method according to claim 12, wherein each of the metal gate and the metal select gate comprises a high-k gate dielectric layer and a conductive gate electrode.

15. The method according to claim 12, wherein a top surface of the metal gate is coplanar with a top surface of the metal select gate.

16. The method according to claim 14 further comprising: forming two charge storage structures on the two opposite sidewalls of the metal select gate, respectively.

17. The method according to claim 16, wherein each of the two charge storage structures comprises an oxide-nitride-oxide (ONO) storage structure.

18. The method according to claim 16, wherein the two charge storage structures are in direct contact with the high-k gate dielectric layer.

19. The method according to claim 11, wherein the two memory gates are polysilicon gates.

20. The method according to claim 11 further comprising: forming two source/drain doping regions in the substrate and adjacent to the two memory gates, respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 to FIG. 6 are schematic diagrams of a method for manufacturing a semiconductor device 1 according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0027] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0028] Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0029] Please refer to FIG. 1 to FIG. 6. FIG. 1 to FIG. 6 are schematic diagrams of a method for manufacturing a semiconductor device 1 according to an embodiment of the present invention. As shown in FIG. 1, a substrate 100 such as a silicon substrate is provided. The substrate 100 has a flash memory region MR and a logic device region DR. A gate dielectric layer 110 and a gate material layer 120 are formed on the substrate 100. For example, the gate dielectric layer 110 may include silicon oxide or silicon oxynitride, but is not limited thereto. For example, the gate material layer 120 may include polysilicon, but is not limited thereto. Next, lithography and etching processes are performed to pattern the gate dielectric layer 110 and the gate material layer 120 in the flash memory region MR to form at least one select gate SG. The select gate SG has two opposite sidewalls SW.

[0030] As shown in FIG. 2, left-right symmetrical charge storage structures CS and memory gate MG are formed on two opposite sidewalls SW of the select gate SG in the flash memory region MR. According to an embodiment of the present invention, the charge storage structure CS may include an oxide-nitride-oxide (ONO) storage structure. According to an embodiment of the present invention, the charge storage structure CS extends from two opposite sidewalls SW of the select gate SG to the substrate 100 to form an L-shaped profile. According to an embodiment of the present invention, the memory gate MG may be a polysilicon gate, but is not limited thereto.

[0031] As shown in FIG. 3, lithography and etching processes are then performed to pattern the gate dielectric layer 110 and the gate material layer 120 in the logic device region DR to form at least one dummy gate DP. Subsequently, an ion implantation process is performed to form source/drain doped regions 101 and source/drain doped regions 102 in the substrate 100 in the logic device region DR and the flash memory region MR, respectively. The source/drain doped regions 102 are adjacent to the memory gates MG. A chemical vapor deposition (CVD) process is then performed to deposit a dielectric layer 130 on the substrate 100 in a blanket manner. The dielectric layer 130 may be a silicon oxide layer, but not limited to. A planarization process, such as a chemical mechanical polishing (CMP) process, is then performed to level the top surface S1 of the dummy gate DP, the top surface S3 of the select gate SG and the top surface S2 of the dielectric layer 130.

[0032] Subsequently, a replacement metal gate (RMG) process is performed. As shown in FIG. 4, a photoresist pattern PR is first formed. The photoresist pattern PR has an opening OP1 and an opening OP2. The opening OP1 reveals the logic device region DR, and the opening OP2 reveals the select gate SG in the flash memory region MR.

[0033] As shown in FIG. 5, an etching process is performed to remove the dummy gate DP in the logic device region DR and the select gate SG in the flash memory region MR, thereby forming a gate trench GT1 and a gate trench GT2, respectively. Subsequently, the photoresist pattern PR is removed.

[0034] As shown in FIG. 6, the metal gate LGM and the metal select gate SGM are respectively formed in the gate trench GT1 and the gate trench GT2, so that at least one logic transistor TL is formed in the logic device region DR, and at least one flash memory transistor TM is formed in the flash memory region MR. According to an embodiment of the present invention, in the flash memory region MR, the two memory gates MG are disposed on two opposite sidewalls SWM of the metal select gate SGM, respectively.

[0035] According to an embodiment of the present invention, the metal gate LGM and the metal select gate SGM have the same gate structure. According to an embodiment of the present invention, both the metal gate LGM and the metal select gate SGM include a high-k gate dielectric layer 210 and a conductive gate electrode 220. According to an embodiment of the present invention, the high-k gate dielectric layer 210 may include hafnium oxide, but is not limited thereto. According to an embodiment of the present invention, the conductive gate electrode 220 may include tungsten, copper, aluminum, titanium, titanium nitride, or any combination thereof.

[0036] According to an embodiment of the present invention, the top surface S4 of the metal gate LGM is flush with the top surface S5 of the metal select gate SGM. According to an embodiment of the present invention, the two charge storage structures CS are in direct contact with the high-k gate dielectric layer 210, respectively.

[0037] Structurally, as shown in FIG. 6, the semiconductor device 1 includes a substrate 100 with a flash memory region MR and a logic device region DR. At least one logic transistor TL is disposed in the logic device region DR, and at least one flash memory transistor TM is disposed in the flash memory region MR. The flash memory transistor TM includes a metal select gate SGM with two opposite sidewalls SWM and two memory gates MG disposed on the two opposite sidewalls SWM of the metal select gate SGM, respectively. According to an embodiment of the present invention, the memory gates MG are polysilicon gates. According to an embodiment of the present invention, the semiconductor device 1 further includes two source/drain doped regions disposed in the substrate 100 and adjacent to the two memory gates MG respectively.

[0038] According to an embodiment of the present invention, the logic transistor TL includes a metal gate LGM. The metal gate LGM and the metal select gate SGM have the same gate structure. Both the metal gate LGM and the metal select gate SGM include a high-k gate dielectric layer 210 and a conductive gate electrode 220. The top surface S4 of the metal gate LGM is flush with the top surface S5 of the metal select gate SGM.

[0039] According to an embodiment of the present invention, two charge storage structures CS are disposed on two opposite sidewalls SWM of the metal select gate SGM, respectively. Each of the charge storage structures CS comprises an oxide-nitride-oxide (ONO) storage structure. The two charge storage structures CS are in direct contact with the high-k gate dielectric layers 210.

[0040] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.