Amplifier including magnetically coupled feedback loop and stacked input and output stages adapted for DC current reuse

Abstract

A stacked amplifier circuit includes an input stage having first and second input ports respectively defined by inputs of first and second transistors. A transformer arrangement includes first and second primary windings and first and second secondary windings. The first secondary winding is connected to an output of the first input transistor and the second secondary winding is connected to an output of the second input transistor. Portions of the magnetic fields generated by the primary windings couple to their respective secondary windings. An output stage is AC coupled to the first and second secondary windings and has an output connected to the first and second primary windings. The input stage and the output stage are arranged in a stacked configuration such that a bias current of the output stage is reused as bias current for the input stage.

Claims

1. A stacked amplifier circuit, comprising: an input stage including first and second input ports respectively defined by inputs of first and second transistors; a transformer arrangement having first and second primary windings and first and second secondary windings wherein a first end of the first secondary winding is connected to an output of the first transistor of the input stage and a first end of the second secondary winding is connected to an output of the second transistor of the input stage; wherein the first primary winding and the first secondary winding are arranged such that a portion of a first magnetic field generated by the first primary winding couples to the first secondary winding; wherein the second primary winding and the second secondary winding are arranged such that a portion of a second magnetic field generated by the second primary winding couples to the second secondary winding; and an output stage having a differential input AC coupled to the first and second secondary windings and an output connected to the first and second primary windings wherein the input stage and the output stage are arranged in a stacked configuration such that a bias current of the output stage is provided by the output stage to the input stage; wherein the transformer arrangement is configured to provide a signal for driving a load.

2. The stacked amplifier circuit of claim 1 wherein the output stage is implemented as a cascode stage.

3. The stacked amplifier circuit of claim 1 wherein the stacked amplifier is implemented as an integrated circuit and wherein the first and second primary windings are integrated in a first metal layer of the integrated circuit and the first and second secondary windings are integrated in a second metal layer of the integrated circuit.

4. The stacked amplifier of claim 1 wherein the differential input of the output stage is capacitively connected to the output of the first transistor of the input stage and to the output of the second transistor of the input stage.

5. The stacked amplifier of claim 1 wherein the transformer arrangement is configured such that a degree of coupling between the first primary winding and the first secondary winding and between the second primary winding and the second secondary winding is selected based upon a target current gain of the stacked amplifier.

6. The stacked amplifier circuit of claim 1 wherein the stacked amplifier is implemented as an integrated circuit and wherein the first and second primary windings are integrated in a single metal layer of the integrated circuit and the first and second secondary windings are integrated in a same metal layer of the integrated circuit.

7. The stacked amplifier circuit of claim 1 further including an output balun connected to the first and second primary windings of the transformer arrangement.

8. A stacked amplifier circuit, comprising: an input stage; an output stage including a first output and a second output wherein the input stage and the output stage are arranged in a stacked configuration such that a bias current of the output stage is provided by the output stage to the input stage; a transformer arrangement including a first transformer having a first primary winding and a first secondary winding configured to provide feedback from the first output to a first input of the output stage and further including a second transformer having a second primary winding and a second secondary winding configured to provide feedback from the second output to a second input of the output stage; wherein the transformer arrangement is configured to provide a signal for driving a load and is further configured such that a degree of coupling between the first primary winding and the first secondary winding and between the second primary winding and the second secondary winding is selected based upon a target current gain of the stacked amplifier circuit.

9. The stacked amplifier circuit of claim 8 further including a balun coupled between the transformer arrangement and the load.

10. The stacked amplifier circuit of claim 8 wherein the first transformer is configured to establish a first magnetically coupled feedback loop from the first output to the first input of the output stage and wherein the second transformer is configured to establish a second magnetically coupled feedback loop from the second output to the second input of the output stage; wherein a loop gain of the first magnetically coupled feedback loop is independent of an impedance of the load and is defined at least in part by a coupling factor and turn-ratio of the first transformer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The features, nature and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

(2) FIG. 1 depicts a block diagram of a conventional feed-forward error correction system which may be used to linearize a PA.

(3) FIG. 2 depicts a block diagram of a so called Cartesian feedback system for amplifier linearization.

(4) FIG. 3 depicts a diagram of a linear feedback system for amplifier linearization.

(5) FIG. 4 illustrates a typical CMOS-based PA implementation.

(6) FIGS. 5A and 5B illustrate generic voltage amplifier circuit implementations of the direct negative feedback approach to linearization shown in FIG. 3.

(7) FIG. 6 illustrates a generic transconductance amplifier system configured to linearize a PA in a manner which avoids stability issues due to varying load impedance.

(8) FIG. 7 illustrates a functional diagram of an embodiment of an amplifier linearization system using magnetically coupled feedback in accordance with the disclosure.

(9) FIG. 8 illustrates a functional diagram of an amplifier linearization system which uses magnetically coupled feedback and lacks a balun at its output.

(10) FIG. 9 is a circuit-level representation of CMOS-based implementation of an amplifier linearization system using magnetically coupled feedback in accordance with the disclosure.

(11) FIGS. 10A and 10B are circuit-level illustrations of a single-ended version of a CMOS-based implementation of an amplifier linearization system using magnetically coupled feedback.

(12) FIG. 11 illustrates an implementation of a linearized power amplifier having stacked input and output stages.

DETAILED DESCRIPTION

(13) Attention is now directed to FIG. 7, which illustrates a functional diagram of an embodiment of an amplifier linearization system 100 using magnetically coupled feedback in accordance with the disclosure. The system 100 comprises a PA 102 having an input 104 and an output 106. A shunt inductance (L.sub.in) 108 is placed at the input 104 of the amplifier to create a parallel resonance with an input capacitance (C.sub.in) of the amplifier 102. In the embodiment of FIG. 7 this parallel resonance is represented by R.sub.in, L.sub.in and C.sub.in, where R.sub.in represent the losses of the parallel resonance circuit. The input from the previous stage driving the amplifier linearization system 100 is typically a current i.sub.s which generates an input voltage to the amplifier 102. An inductor 112 (L.sub.out) is in series with the output 106 of the amplifier 102 and laid out or otherwise arranged in such a way that some of the magnetic field which it generates couples to the inductor 108. When arranged in this way the inductor 112 forms the primary winding of a transformer which includes a secondary winding comprised of the inductor 108.

(14) During operation of the system 100 the magnetic field generated by the transformer primary winding (inductor 112) couples to the secondary winding (shunt inductance 108) through a magnetically coupled feedback loop 116, thereby providing feedback from the amplifier output 106 to the amplifier input 104. The amplifier 102 generates an output signal to an output load arrangement 120 connected to the transformer primary winding (inductor 112). In one embodiment the output load arrangement includes a balun 122 operative to convert a differential signal into a single-ended signal driving an external load impedance Z.sub.L 124.

(15) Implementations of the amplifier system 100 are suitable for chip level integration where the two inductors L.sub.in and L.sub.out are preferably drawn in different metal layers and laid out on top of each other. This magnetic coupling from the output 106 to the input 104 of the power amplifier 102 generates direct feedback which is not believed to be present in state-of-the-art power amplifiers.

(16) The amplifier system 100 can be implemented using either a single ended or differential amplifier configuration. In general it will be important to ensure that the parasitic capacitance between the amplifier output 106 and ground is small, else an excessive phase shift of up to 180 degrees will result and cause instability. Small parasitic capacitance at the amplifier output 106 is possible when integrating the power amplifier 102 on silicon, especially when a so called all (Silicon-On-Isolator) technology is used, where the parasitic device capacitances are extremely small.

(17) Turning now to FIG. 8, there is illustrated which a functional diagram of an amplifier linearization system 100 using magnetically coupled feedback in accordance with the disclosure. As shown, the linearization system 100 of FIG. 8 is substantially similar to the linearization system 100 of FIG. 7 with the exception that the linearization system 100 is configured with an output load arrangement comprised solely of an external load impedance Z.sub.L 124; that is, the output load arrangement of the system 100 lacks a balun. In this case the output signal produced by the system 100 consists of the output voltage V.sub.out across the external load impedance Z.sub.L 124.

CMOS-Based Implementation of Amplifier Linearization System

(18) Reference is now made to FIG. 9, which is a circuit-level representation of CMOS-based implementation of an amplifier linearization system 200 using magnetically coupled feedback in accordance with the disclosure. In the CMOS-based system 200 the power amplifier 202 is implemented with a Cascode stage (transistors M1 and M2). In the embodiment of FIG. 9 the input signal is differential and represented by the current source i.sub.s. A transformer 214 having a primary winding 212 and a secondary winding 208 functions as a magnetically coupled feedback loop to effect feedback from an output 206 to an input 204 of amplifier 202. In one embodiment the transformer 214 is comprised of a first transformer component 214A and a second transformer component 214B, which may or may not be intertwined. The first transformer component 214A includes a primary winding 212A and a secondary winding 208A and the second transformer component 214B includes a primary winding 212B and a secondary winding 208B. An output load arrangement 220 includes a balun 222 connected to the primary winding 212A, 212B of the transformer components 214A, 214B. The balun 222 converts the output current provided by the primary transformer windings 212A, 212B into a single ended current, which generates power upon reaching an external load impedance 224 included within the output load arrangement 220.

Mathematical Characterization of Amplifier Linearization System

(19) Attention is now directed to FIGS. 10A and 10B, which illustrate a single-ended version of a CMOS-based implementation of an amplifier linearization system 300 using magnetically coupled feedback. FIG. 10A depicts components present in an exemplary physical realization of the system 300 while FIG. 10B further illustrates additional components to which reference will be made in the mathematical characterization of the system 300 set forth below. With reference to FIG. 10B, the input signal is, as in the differential case of FIG. 9, represented by the current source i.sub.s. The capacitance C.sub.g is the total parasitic capacitance from the input node 304 of the amplifier 302 to ground, which is dominated by the gate capacitance of M1. The inductance L.sub.2 of the secondary winding 308 of the transformer 314 should in combination with the capacitance C.sub.g be selected such that resonance occurs at the frequency of operation according to Equation 1.

(20) $\begin{array}{cc}{f}_0=\frac{1}{2?\sqrt{L_2{C}_g}}& \mathrm{Equation}1\end{array}$

(21) The resistance R.sub.p (FIG. 10B) is not a physical resistance, instead it is a model of the losses from the resonance circuit at the input of the amplifier 302, which is primarily determined by the losses of the inductance L.sub.2 of the secondary winding 308 of the transformer 314 according Equation 2, where QL.sub.2 is the quality factor of L.sub.2.
R.sub.p=Q.sub.L22?fL.sub.2Equation 2:

(22) The device M1 converts the voltage at its gate (v.sub.in) into a current with the transconductance (g.sub.m) of M1. The inductance of the primary winding 312 of the transformer 314 is L.sub.1 and the so called turn-ratio of the transformer is defined by Equation 3.

(23) $\begin{array}{cc}n=\sqrt{\frac{L_2}{L_1}}& \mathrm{Equation}3\end{array}$

(24) The transformer 314 may also be characterized by its so-called coupling factor k, which is a measure of the amount of inductive coupling that exists between the two coils 308, 312 and is expressed as a fractional number between 0 and 1, where 0 indicates zero or no inductive coupling, and 1 indicating full or maximum inductive coupling.

(25) The load inductance L.sub.o and capacitance C.sub.o are chosen such that resonance occurs at the frequency of operation according Equation 4. The AC coupling capacitance C.sub.ac is selected such that its impedance is low compared to the load impedance R.sub.L. Hence, the load seen by the output current i.sub.o can, at the frequency of operation, be represented by the load impedance R.sub.L.

(26) $\begin{array}{cc}{f}_0=\frac{1}{2?\sqrt{L_o{C}_o}}& \mathrm{Equation}4\end{array}$

(27) With the definitions made above, it is possible to calculate the current gain, which results in Equation 5.

(28) $\begin{array}{cc}{A}_i=\frac{i_o}{i_s}=A_{i?}\frac{A?}{1-A?}& \mathrm{Equation}5\end{array}$

(29) Where A? is the loopgain of the feedback loop as defined in Equation 6 and A.sub.i? is the current gain with infinite loop gain as defined in Equation 7.

(30) $\begin{array}{cc}A?=-g_m{R}_p\frac{k}{n}& \mathrm{Equation}6\\ A_{i?}=\frac{n}{k}& \mathrm{Equation}7\end{array}$

(31) As may be appreciated from Equation 7, when the loop gain A? is infinite the gain of the amplifier system 300 depends only on the characteristics of the transformer 314 as expressed by A.sub.i?. This means that under these conditions the gain is substantially independent of the inherent gain characteristics of the amplifier 302, i.e. it is substantially independent of g.sub.m. This brings significant advantages as g.sub.m is to large extent dependent on temperature, bias current, silicon technology behavior, loading effects, and supply voltage variations. In practice, it is of course not possible to realize an infinite loop gain. However, the inventor has found that when the loop gain is on the order of 10 dB the amplifier system 300 generally exhibits the desired behavior.

Key Features of Amplifier Linearization System

(32) From the above equations various features and advantages of the present amplifier linearization system are apparent. First, one key advantage of the present system is that the load impedance is not found in any of the preceding expressions. Hence, stability is much easier to accomplish in the present system relative to conventional power amplifier systems since the loop gain is independent on the load impedance; that is, any variation of the load impedance in the present system will not impact loop stability. Second, another important aspect of the present system is that the gain is defined by the coupling factor and the turn-ratio of the transformer, which are constant across both temperature and signal level variations. In a Cascode amplifier without this feedback, the gain is achieved by converting the input voltage of the Cascode into current by the transconductance of the Common Source stage of the Cascode, which is both temperature as well as signal level dependent. A gain which is dependent on the signal level results in distortion, which is typically solved by backing off the signal level from the compression point of the amplifier. However, the presently disclosed feedback topology enables an amplifier to operate closer to compression without degrading its linearity performance. Yet another key advantage of the present system is that its input impedance is low due to the magnetically coupled feedback, which results in a lower voltage swing at the input of the Cascode. Since the input current is generated by a driver stage, low voltage swing at the driver output reduces its distortion and makes the overall system more linear.

Additional Novel Features and Advantages

(33) As can be seen in FIGS. 9, 10A and 10B, assuming the presence of a shunt inductance at the input of the amplifier 302 (FIGS. 10A, 10B), the magnetically coupled feedback network does not require any additional circuitry other than the series inductance 312 located at the output of the amplifier 302. Furthermore, no additional DC current is required to bias the magnetically coupled feedback network.

(34) From Equation 6, it can be seen that the loop gain is proportional to the transconductance of the Common Source stage, which offers important advantages. For example, since g.sub.m is dependent on the current flowing in the Common Source stage, the loop gain will increase when the signal is increased, i.e., the loop gain will become large when the signal level is large. This is a preferred characteristic from a linearity point of view.

(35) It is known that state-of-the-art power amplifiers often operate in so called class AB operation, which means that DC power dissipation increases with the signal level. Due to the magnetically coupled feedback topology described herein, the amplifier can be biased in class A operation, which means that the DC power dissipation remains constant independent on the signal level. In many applications this is a very important feature. One such application is in WiFi power amplifiers, where a high output power is typically transmitted when the link is established. In accordance with the present disclosure, a high output power can be transmitted without increasing the power dissipation.

(36) It is also observed that the signal transfer function of the present linearized power amplifier system is defined by passive layout structures (i.e., one or more transformers) which are independent of signal level and temperature. This feature can be used to program the power amplifier system for different use cases. For example, when very good linearity is required the DC bias current can be increased to provide improved linearity without impacting the transfer gain of the amplifier system. In contrast, changing the bias conditions of state-of-the-art amplifiers will also impact the gain of such amplifiers.

(37) It is further observed that the load impedance has little or no direct impact on loop stability. In addition, the input impedance of the output stage is low, which reduces the voltage swing at the input. Finally, the disclosed feedback concept is suitable for chip-integration, both in CMOS and Bipolar technologies.

Stacked Input and Output Stages

(38) Turning now to FIG. 11, an implementation is shown of a linearized power amplifier system 600 having an input stage 610, an output stage 620, a transformer arrangement 630 and an output balun 640. The input stage 610 and the output stage 620 are realized in different integrated circuit layers and are laid out so as to be stacked on each other. The transformer arrangement 630 effects magnetically coupled feedback from first and second outputs 644A, 644B of the output stage 620 to an input 648 of the output stage 620630. As shown, the output stage 620 has a differential input 652A, 652B which is AC coupled 656A, 656B to first and second secondary windings 662A, 662B of the transformer arrangement 630. One key advantage of this stacked configuration is that the bias current of the output stage 620 is reused as bias current for the input stage 610, which improves efficiency of the power amplifier system 600.

(39) Where methods described above indicate certain events occurring in certain order, the ordering of certain events may be modified. Additionally, certain of the events may be performed concurrently in a parallel process when possible, as well as performed sequentially as described above. Accordingly, the specification is intended to embrace all such modifications and variations of the disclosed embodiments that fall within the spirit and scope of the appended claims.

(40) The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the claimed systems and methods. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the systems and methods described herein. Thus, the foregoing descriptions of specific embodiments of the described systems and methods are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the claims to the precise forms disclosed; obviously, many modifications and variations are possible in view of the above teachings. The embodiments were chosen and described in order to best explain the principles of the described systems and methods and their practical applications, they thereby enable others skilled in the art to best utilize the described systems and methods and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the following claims and their equivalents define the scope of the systems and methods described herein.

(41) Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

(42) All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

(43) The indefinite articles a and an, as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean at least one.

(44) The phrase and/or, as used herein in the specification and in the claims, should be understood to mean either or both of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with and/or should be construed in the same fashion, i.e., one or more of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the and/or clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to A and/or B, when used in conjunction with open-ended language such as comprising can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

(45) As used herein in the specification and in the claims, or should be understood to have the same meaning as and/or as defined above. For example, when separating items in a list, or or and/or shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as only one of or exactly one of, or, when used in the claims, consisting of, will refer to the inclusion of exactly one element of a number or list of elements. In general, the term or as used herein shall only be interpreted as indicating exclusive alternatives (i.e. one or the other but not both) when preceded by terms of exclusivity, such as either, one of, only one of, or exactly one of. Consisting essentially of, when used in the claims, shall have its ordinary meaning as used in the field of patent law.

(46) As used herein in the specification and in the claims, the phrase at least one, in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase at least one refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, at least one of A and B (or, equivalently, at least one of A or B, or, equivalently at least one of A and/or B) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

(47) In the claims, as well as in the specification above, all transitional phrases such as comprising, including, carrying, having, containing, involving, holding, composed of, and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases consisting of and consisting essentially of shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.