TRANSMITTER CIRCUIT, CORRESPONDING ISOLATED DRIVER DEVICE, ELECTRONIC SYSTEM AND METHOD OF ENCODING A PULSE-WIDTH MODULATED SIGNAL INTO A DIFFERENTIAL PULSED SIGNAL

Abstract

A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.

Claims

1. A circuit, comprising: a first input node configured to receive a pulse-width modulated input signal; a second input node configured to receive a clock signal having a frequency higher than a frequency of said pulse-width modulated input signal; a logic circuit sensitive to said clock signal and configured to generate a control signal as a function of said clock signal, wherein said control signal is normally set to a first logic value, and is periodically set to a second logic value for a transmission time interval in response to an edge being detected in said clock signal, said transmission time interval being shorter than a half clock period of said clock signal; a tri-state transmitter coupled to the first input node to receive said pulse-width modulated input signal and sensitive to said control signal, the tri-state transmitter being configured to produce a first output signal at a first transmitter output node and a second output signal at a second transmitter output node, the first output signal and the second output signal having a voltage swing between a positive supply voltage and a reference supply voltage; an output control circuit sensitive to said control signal and coupled to said first transmitter output node and said second transmitter output node; wherein: in response to said control signal having said first logic value, said tri-state transmitter sets said first transmitter output node and said second transmitter output node to a high impedance state, and said output control circuit drives said first transmitter output node and said second transmitter output node to an intermediate voltage level between said positive supply voltage and said reference supply voltage; and in response to said control signal having said second logic value, said tri-state transmitter drives said first transmitter output node to said positive supply voltage or to said reference supply voltage according to the logic value of said pulse-width modulated input signal, and drives said second transmitter output node to said positive supply voltage or to said reference supply voltage according to the inverted logic value of said pulse-width modulated input signal, wherein said tri-state transmitter is faster than said output control circuit in driving said first transmitter output node and said second transmitter output node.

2. The circuit of claim 1, wherein said tri-state transmitter is configured to drive said first transmitter output node and said second transmitter output node to said positive supply voltage and to said reference supply voltage with a respective transition time that is at least 100 times shorter than the transition time with which said output control circuit drives said first transmitter output node and said second transmitter output node to said intermediate voltage level.

3. The circuit of claim 1, wherein said tri-state transmitter is configured to drive said first transmitter output node and said second transmitter output node to said positive supply voltage and to said reference supply voltage with a respective transition time in the range of 10 ps to 100 ps, and wherein said output control circuit drives said first transmitter output node and said second transmitter output node to said intermediate voltage level with a respective transition time in the range of 30 ns to 40 ns.

4. The circuit of claim 1, wherein said logic circuit includes: a first delay circuit element configured to produce a delayed replica of said clock signal; a first XOR gate configured to receive said clock signal and said delayed replica of said clock signal as input; and an inverter circuit configured to invert the output signal from said first XOR gate to produce said control signal.

5. The circuit of claim 1, wherein said logic circuit is further sensitive to said pulse-width modulated input signal and is configured to generate said control signal further as a function of said pulse-width modulated input signal, wherein said control signal is set to said second logic value for said transmission time interval is in response to an edge being detected in said pulse-width modulated input signal.

6. The circuit of claim 5, wherein said logic circuit includes: a first delay circuit element configured to produce a delayed replica of said clock signal; a first XOR gate configured to receive said clock signal and said delayed replica of said clock signal as input; a second delay circuit element configured to produce a delayed replica of said pulse-width modulated input signal; a second XOR gate configured to receive said pulse-width modulated input signal and said delayed replica of said pulse-width modulated input signal as input; and a NOR gate configured to receive the output signals from said first XOR gate and said second XOR gate to produce said control signal.

7. The circuit of claim 1, wherein said tri-state transmitter includes: a first half-bridge circuit arranged between said positive supply voltage and said reference supply voltage and having an intermediate node coupled to said first transmitter output node; and a second half-bridge circuit arranged between said positive supply voltage and said reference supply voltage and having an intermediate node coupled to said second transmitter output node; wherein: a high-side switch of said first half-bridge circuit is conductive in response to said control signal having said second logic value and said pulse-width modulated input signal having a high logic value; a low-side switch of said first half-bridge circuit is conductive in response to said control signal having said second logic value and said pulse-width modulated input signal having a low logic value; a high-side switch of said second half-bridge circuit is conductive in response to said control signal having said second logic value and said pulse-width modulated input signal having a low logic value; a low-side switch of said second half-bridge circuit is conductive in response to said control signal having said second logic value and said pulse-width modulated input signal having a high logic value; and said high-side switch and said low-side switch of said first half-bridge circuit, as well as said high-side switch and said low-side switch of said second half-bridge circuit, are non-conductive in response to said control signal having said first logic value.

8. The circuit of claim 1, wherein said output control circuit includes: a voltage divider arranged between said positive supply voltage and said reference supply voltage; and respective switches configured to selectively couple an intermediate node of said voltage divider to said first transmitter output node and said second transmitter output node in response to said control signal having said first logic value.

9. The circuit of claim 1, comprising a protection circuit, wherein the protection circuit includes a first protection capacitance, a second protection capacitance, and protection circuitry configured to: charge said first protection capacitance to said positive supply voltage in response to said control signal having said second logic value and said pulse-width modulated input signal having a high logic value; charge said first protection capacitance to said reference supply voltage in response to said control signal having said second logic value and said pulse-width modulated input signal having a low logic value; charge said second protection capacitance to said positive supply voltage in response to said control signal having said second logic value and said pulse-width modulated input signal having a low logic value; charge said second protection capacitance to said reference supply voltage in response to said control signal having said second logic value and said pulse-width modulated input signal having a high logic value; and couple said first protection capacitance to said first transmitter output node and couple said second protection capacitance to said second transmitter output node in response to said control signal having said first logic value.

10. The circuit of claim 1, comprising: a first differential output node and a second differential output node; a first isolation capacitance coupled between said first transmitter output node and said first differential output node; and a second isolation capacitance coupled between said second transmitter output node and said second differential output node, wherein a differential output signal indicative of said pulse-width modulated input signal is produced between said first differential output node and said second differential output node.

11. An isolated driver device, comprising: a first semiconductor die having a transmitter circuit implemented thereon, the transmitter circuit including: a first input node configured to receive a pulse-width modulated input signal; a second input node configured to receive a clock signal having a frequency higher than a frequency of said pulse-width modulated input signal; a logic circuit sensitive to said clock signal and configured to generate a control signal as a function of said clock signal, wherein said control signal is normally set to a first logic value, and is periodically set to a second logic value for a transmission time interval in response to an edge being detected in said clock signal, said transmission time interval being shorter than a half clock period of said clock signal; a tri-state transmitter coupled to the first input node to receive said pulse-width modulated input signal and sensitive to said control signal, the tri-state transmitter being configured to produce a first output signal at a first transmitter output node and a second output signal at a second transmitter output node, the first output signal and the second output signal having a voltage swing between a positive supply voltage and a reference supply voltage; an output control circuit sensitive to said control signal and coupled to said first transmitter output node and said second transmitter output node; wherein: in response to said control signal having said first logic value, said tri-state transmitter sets said first transmitter output node and said second transmitter output node to a high impedance state, and said output control circuit drives said first transmitter output node and said second transmitter output node to an intermediate voltage level between said positive supply voltage and said reference supply voltage; and in response to said control signal having said second logic value, said tri-state transmitter drives said first transmitter output node to said positive supply voltage or to said reference supply voltage according to the logic value of said pulse-width modulated input signal, and drives said second transmitter output node to said positive supply voltage or to said reference supply voltage according to the inverted logic value of said pulse-width modulated input signal, wherein said tri-state transmitter is faster than said output control circuit in driving said first transmitter output node and said second transmitter output node; and a second semiconductor die having a first receiver input node and a second receiver input node, the first receiver input node being electrically coupled to the first differential output node of the transmitter circuit and the second receiver input node being electrically coupled to the second differential output node of the transmitter circuit to receive said differential output signal; wherein the second semiconductor die has a receiver circuit implemented thereon, the receiver circuit being configured to receive said differential output signal, and to set a driving signal to a first logic value in response to a positive pulse being detected in said differential output signal and to a second logic value in response to a negative pulse being detected in said differential output signal.

12. The isolated driver device of claim 11, wherein the second semiconductor die has a driver circuit implemented thereon, the driver circuit including a half-bridge circuit arranged between a positive supply voltage pin and a reference supply voltage pin and driven by said driving signal to produce an output switching signal.

13. The isolated driver device of claim 11, wherein said tri-state transmitter is configured to drive said first transmitter output node and said second transmitter output node to said positive supply voltage and to said reference supply voltage with a respective transition time that is at least 100 times shorter than the transition time with which said output control circuit drives said first transmitter output node and said second transmitter output node to said intermediate voltage level.

14. The isolated driver device of claim 11, wherein said tri-state transmitter is configured to drive said first transmitter output node and said second transmitter output node to said positive supply voltage and to said reference supply voltage with a respective transition time in the range of 10 ps to 100 ps, and wherein said output control circuit drives said first transmitter output node and said second transmitter output node to said intermediate voltage level with a respective transition time in the range of 30 ns to 40 ns.

15. The isolated driver device of claim 11, wherein said logic circuit includes: a first delay circuit element configured to produce a delayed replica of said clock signal; a first XOR gate configured to receive said clock signal and said delayed replica of said clock signal as input; and an inverter circuit configured to invert the output signal from said first XOR gate to produce said control signal.

16. An electronic system, comprising: an isolated driver device according to claim 11; and processing circuitry configured to generate said pulse-width modulated input signal and said clock signal, the isolated driver device coupled to the processing unit to receive said pulse-width modulated input signal and said clock signal.

17. The electronic system of claim 16, wherein the second semiconductor die has a driver circuit implemented thereon, the driver circuit including a half-bridge circuit arranged between a positive supply voltage pin and a reference supply voltage pin and driven by said driving signal to produce an output switching signal.

18. The electronic system of claim 16, wherein said tri-state transmitter is configured to drive said first transmitter output node and said second transmitter output node to said positive supply voltage and to said reference supply voltage with a respective transition time that is at least 100 times shorter than the transition time with which said output control circuit drives said first transmitter output node and said second transmitter output node to said intermediate voltage level.

19. A method of encoding a pulse-width modulated signal into a differential pulsed signal, the method comprising: receiving said pulse-width modulated signal; providing a clock signal having a frequency higher than the frequency of said pulse-width modulated signal; generating a control signal as a function of said clock signal, wherein said control signal is normally set to a first logic value, and is periodically set to a second logic value for a transmission time interval in response to an edge being detected in said clock signal, said transmission time interval being shorter than a half clock period of said clock signal; producing a first output signal and a second output signal, the first output signal and the second output signal having a voltage swing between a positive supply voltage and a reference supply voltage; and applying capacitive filtering to said first output signal and said second output signal to produce respective first and second filtered output signals, wherein said differential pulsed signal is produced as a difference between said first filtered output signal and said second filtered output signal, wherein producing said first output signal and said second output signal includes: in response to said control signal having said first logic value, setting said first output signal and said second output signal to an intermediate voltage level between said positive supply voltage and said reference supply voltage; and in response to said control signal having said second logic value, setting said first output signal to said positive supply voltage or to said reference supply voltage according to the logic value of said pulse-width modulated input signal, and setting said second output signal to said positive supply voltage or to said reference supply voltage according to the inverted logic value of said pulse-width modulated input signal, wherein a time interval for setting said first output signal and said second output signal to said positive supply voltage or to said reference supply voltage is shorter than a time interval for setting said first output signal and said second output signal to said intermediate voltage level.

20. The method of claim 19, wherein generating the control signal includes generating said control signal further as a function of said pulse-width modulated input signal, wherein said control signal is set to said second logic value for said time interval in response to an edge being detected in said pulse-width modulated input signal.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0024] One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein:

[0025] FIG. 1 is a circuit block diagram exemplary of an isolated gate driver device;

[0026] FIGS. 2 and 3 are time diagrams of signals in the isolated gate driver device of FIG. 1;

[0027] FIGS. 4, 5 and 6 are diagrams schematically illustrating using on-off keying (OOK) modulation of the input signal of the isolated gate driver device of FIG. 1;

[0028] FIG. 7 is exemplary of time diagrams of signals in one or more embodiments of the present description;

[0029] FIG. 8 is a circuit block diagram exemplary of a transmitter circuit according to one or more embodiments of the present description;

[0030] FIG. 9 is exemplary of time diagrams of signals in one or more embodiments of the present description;

[0031] FIGS. 10 and 11 are circuit diagrams exemplary of implementation details of transmitter circuits according to one or more embodiments of the present description; and

[0032] FIG. 12 is exemplary of a comparison between time diagrams of signals in one or more embodiments of the present description and time diagrams of signals in a transmitter circuit based on on-off keying modulation.

DETAILED DESCRIPTION

[0033] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0034] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0035] The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0036] Throughout the figures annexed herein, unless the context indicates otherwise, like parts or elements are indicated with like references/numerals and a corresponding description will not be repeated for the sake of brevity.

[0037] FIG. 1 is a circuit block diagram exemplary of an isolated gate driver device. FIGS. 2 and 3 are time diagrams of signals in the isolated gate driver device of FIG. 1, which are exemplary of possible operation of the gate driver device.

[0038] As exemplified in FIG. 1, the isolated gate driver device 10 comprises a low voltage die 10a and a high voltage die 10b in the same package. The gate driver device 10 comprises an input pin 101 configured to receive a single ended pulse-width modulated input signal PWM.sub.IN (e.g., from a microcontroller, not visible in FIG. 1). The frequency of the input signal PWM.sub.IN may be, for instance, in the range of 15 kHz to 5 MHz. The low voltage die 10a comprises a transmitter circuit 102 coupled to the input pin 101 and configured to convert the received single ended signal PWM.sub.IN into a pair of differential pulse-width modulated signals OUT.sub.P, OUT.sub.N. For instance, signal OUT.sub.P may be generated at the output of a buffer circuit that receives the input signal PWM.sub.IN at input, and signal OUT.sub.N may be generated at the output of another buffer circuit that receives an inverted replica of the input signal PWM.sub.IN at input. The low voltage die 10a further comprises a first high voltage capacitance 103P (e.g., an isolation capacitance) having a first terminal coupled to the first output of the transmitter circuit 102 to receive signal OUT.sub.P, and a second high voltage capacitance 103N (e.g., an isolation capacitance) having a first terminal coupled to the second output of the transmitter circuit 102 to receive signal OUT.sub.N. The second terminals of the capacitances 103P and 103N provide the output nodes of the low voltage die 10a, which are connected (e.g., via bonding wires) to the input nodes of the high voltage die 10b. The signals OUT.sub.P, OUT.sub.N are filtered by the isolation capacitances 103P, 103N so that a pulsed differential signal V.sub.d reaches the high voltage die 10b. The differential signal V.sub.d comprises a train of pulses (positive and negative) corresponding to the edges (rising and falling, respectively) of the input PWM signal PWM.sub.IN, as exemplified in FIG. 2. The high voltage die 10b comprises a receiver circuit 104 coupled to the input nodes of the die 10b to receive the differential signal V.sub.d, and configured to produce a reconstructed pulse-width modulated signal PWM.sub.RX as a function of the received differential signal V.sub.d. For instance, the receiver circuit 104 may be configured to set the signal PWM.sub.RX to a high logic value (‘1’) as a result of a positive pulse being detected in the differential signal V.sub.d, and to a low logic value (‘0’) as a result of a negative pulse being detected in the differential signal V.sub.d, as exemplified in FIG. 2. Therefore, the reconstructed signal PWM.sub.RX may substantially correspond to a (slightly) delayed copy of the transmitted signal PWM.sub.IN, as exemplified in FIG. 2. The high voltage die 10b comprises a driver stage 105 including a pre-driver circuit (e.g., buffers 1051, 1052, 1053) configured to receive the reconstructed signal PWM.sub.RX and drive an output switching circuit as a function thereof (e.g., inverting at inverter 1051 and/or amplifying at buffers 1052, 1053 the reconstructed signal PWM.sub.RX). For instance, the output switching circuit may comprise a half-bridge driving stage comprising a high-side transistor and a low-side transistor arranged in series between a high voltage supply pin VH and a high voltage reference pin VL of the gate driver device 10. A node intermediate the high-side transistor and the low-side transistor may be electrically coupled to an output pin 106 of the gate driver device 10. The high-side transistor and the low-side transistor are driven by the pre-driver circuit 1051, 1052, 1053 so that an output switching signal OUT is produced at the output pin 106 (e.g., the high-side transistor is in a conductive state when PWM.sub.RX=1 and the low-side transistor is in a conductive state when PWM.sub.RX=0).

[0039] In various applications, a gate driver device as exemplified in FIG. 1 may be placed (e.g., operated) in a noisy environment. Therefore, for some unpredictable and/or unforeseen reason (e.g., disturbances, interferences, spurious spikes, etc.), one or more pulses in the differential signal V.sub.d may occasionally not be decoded (e.g., detected) by the receiver circuit 104, as exemplified in the time diagrams of FIG. 3, where a negative pulse MP3 of signal V.sub.d is not detected by the receiver circuit 104. In such cases, the reconstructed signal PWM.sub.RX may not switch to the expected value and may retain its last value (as exemplified by signal PWM.sub.RX that remains stationary at a high logic value at instant t.sub.M, when it should switch to a low logic value instead). The reconstructed signal PWM.sub.RX switches again at the next “useful” edge correctly detected (e.g., the next falling edge DP3, as exemplified in FIG. 3, if the missed edge was a falling one). In other cases, to the contrary, unexpected spikes (e.g., due to disturbances) in the differential signal V.sub.d may generate spurious, unwanted commutations of the reconstructed signal PWM.sub.RX.

[0040] In order to mitigate the above-discussed issue (i.e., the issue of missing “good” pulses and/or detecting “spurious” pulses in the signal V.sub.d at the input of the high voltage die 10b), a conventional approach may rely on using on-off keying (OOK) modulation of the input signal PWM.sub.IN, as exemplified in FIGS. 4, 5 and 6. In this case, the low voltage die 10a of the gate driver device 10 comprises a mixer circuit 40 that receives the input signal PWM.sub.IN(t) and a high frequency carrier signal C(t) (e.g., a sinusoidal signal having a frequency in the range of 100 MHz to 500 MHz) and produces an OOK-modulated signal PWM.sub.TX(t) for transmission to the transmitter circuit 102, according to the known equations of OOK modulation, reproduced in the following:

[00001]${\mathrm{PWM}}_{\mathrm{TX}}\left(t\right)=\{\begin{array}{cc}C\left(t\right),& \mathrm{if}{\mathrm{PWM}}_{\mathrm{IN}}=1\\ 0,& \mathrm{if}{\mathrm{PWM}}_{\mathrm{IN}}=0\end{array}$

or, equivalently:

PWM.sub.TX(t)=PWM.sub.IN(t).Math.C(t)

[0041] Additionally, the low voltage die 10a of the gate driver device 10 may comprise an oscillator circuit for generating the high frequency carrier signal C(t).

[0042] According to this approach, the receiver circuit 104 may be configured to count a number N of pulses (e.g., N=2 as exemplified in FIGS. 5 and 6) to reconstruct the PWM signal PWM.sub.RX. After receiving a number N of pulses, the receiver circuit 104 asserts (e.g., sets to a high logic value) the reconstructed signal PWM.sub.RX. Otherwise, the reconstructed signal PWM.sub.RX remains de-asserted (e.g., set to a low logic value). If the receiver circuit 104 misses a pulse, it may still be able to reconstruct the signal PWM.sub.RX, insofar as it will start counting the pulses from the pulse that immediately follows the missed one: see, for instance, the missed pulse MP6 in FIG. 6, with the output signal PWM.sub.RX(t) being asserted (e.g., set to a high logic value) at the third pulse of signal PWM.sub.TX(t), because the receiver circuit 104 started counting on the second pulse instead of the first one. The higher is the frequency of the carrier signal C(t), the faster is the receiver circuit in correcting the value of the reconstructed signal PWM.sub.RX.

[0043] However, an approach based on OOK modulation introduces a delay in the communication between the low voltage die 10a and the high voltage die 10b, insofar as the receiver circuit 104 needs a time interval T.sub.decoding before assigning the right value to the reconstructed signal PWM.sub.RX at each commutation thereof, as exemplified in FIGS. 5 and 6. The time interval T.sub.decoding is substantially equal to N times the period of the carrier signal C(t), N being again the number of pulses detected (e.g., counted) before assigning a new value (e.g., asserting and/or de-asserting) to the signal PWM.sub.RX(t).

[0044] One or more embodiments may provide an improved transmitter circuit for use in an isolated driver device, based on the recognition that a receiver circuit in the high voltage die of the driver device may be configured to generate a reconstructed PWM signal PWM.sub.RX by setting the signal PWM.sub.RX to a high logic value (‘1’) in response to a positive pulse being detected in the input differential signal V.sub.d, and setting the signal PWM.sub.RX to a low logic value (‘0’) in response to a negative pulse being detected in the input differential signal V.sub.d, as previously discussed with reference to FIGS. 1 to 3.

[0045] Therefore, one or more embodiments may rely on the operating principle exemplified in the time diagrams of FIG. 7 and discussed in the following. In one or more embodiments, a transmitter circuit may comprise circuitry configured to convert the received single ended signal PWM.sub.IN into a pair of differential pulse-width modulated signals OUT.sub.P, OUT.sub.N that comprise continuous trains of pulses (e.g., a respective train of pulses for each commutation of the input signal PWM.sub.IN). The pulses are generated continuously by resorting to a clock signal CLK having a frequency higher than the frequency of signal PWM.sub.IN, so that even if a pulse is lost, the signal PWM.sub.RX (reconstructed at the receiver side) can switch correctly at the next pulse. Therefore, in one or more embodiments a transmitter circuit may be configured to generate a pair of signals OUT.sub.P and OUT.sub.N that, once filtered by the capacitances 103P and 103N, produce a differential signal V.sub.d having pulses both at the edges of the input signal PWM.sub.IN and at the edges of the clock signal CLK. The pulses in the differential signal V.sub.d have a sign (positive or negative) that depends on the level (e.g., logic value) of the input signal PWM.sub.IN. For instance, as exemplified in FIG. 7, the differential signal V.sub.d may include a positive pulse at each edge (rising or falling) of signals PWM.sub.IN and CLK when PWM.sub.IN has a high logic value, and a negative pulse at each edge (rising or falling) of signals PWM.sub.IN and CLK when PWM.sub.IN has a low logic value. According to this operating principle, the receiver circuit 104 in the high voltage die 10b of the isolated driver device may be able to “correct” the value of the reconstructed signal PWM.sub.RX, in the case of a missed pulse and/or spurious pulse, with a delay (e.g., maximum delay) of half clock period. The time diagrams of FIG. 7 illustrate an exemplary case where a pulse MP7 is missed by the receiver circuit at instant t.sub.M7, and the reconstructed signal PWM.sub.RX is assigned the correct value (high, in the case exemplified herein) at instant t.sub.C7, after a time interval equal to T.sub.CLK/2.

[0046] Therefore, one or more embodiments may relate to a transmitter circuit 802′ (possibly formed in a low voltage die 80a of an otherwise conventional isolated driver device 10) as exemplified in the circuit block diagram of FIG. 8.

[0047] The transmitter circuit 802′ comprises an input pin 801a configured to receive a single ended pulse-width modulated input signal PWM.sub.IN, and an input pin 801b configured to receive a clock signal CLK having a frequency higher than the frequency of the input signal PWM.sub.IN. For instance, the frequency of the input signal PWM.sub.IN may be in the range of 15 kHz to 5 MHz. The frequency of the clock signal CLK may be from 2 times higher to 100 times higher than the frequency of the input signal PWM.sub.IN; optionally, the frequency of the clock signal CLK may be about 50 times higher than the frequency of the input signal PWM.sub.IN. For instance, the frequency of the clock signal CLK may be in the range of 8 MHz to 40 MHz; optionally, the frequency of the clock signal CLK may be about 10 MHz. The signals PWM.sub.IN and CLK may be received from an external circuit, e.g., a microcontroller not visible in the Figures annexed herein.

[0048] The transmitter circuit 802′ comprises a tri-state transmitter 802 coupled to the input pin 801a and configured to convert the received single ended signal PWM.sub.IN into a pair of differential pulse-width modulated signals OUT.sub.P, OUT.sub.N. For instance, signal OUT.sub.P may be generated at the output of a buffer circuit 8021 that receives the input signal PWM.sub.IN at input, and signal OUT.sub.N may be generated at the output of another buffer circuit 8023 that receives an inverted replica (e.g., via inverter 8022) of the input signal PWM.sub.IN at input. The die 80a comprises a first high voltage capacitance 803P (e.g., an isolation capacitance) having a first terminal coupled to the first output of the tri-state transmitter 802 (e.g., coupled to the output node 802P of buffer 8021) to receive signal OUT.sub.P, and a second high voltage capacitance 803N (e.g., an isolation capacitance) having a first terminal coupled to the second output of the tri-state transmitter 802 (e.g., coupled to the output node 802N of buffer 8023) to receive signal OUT.sub.N. The second terminals of the capacitances 803P, 803N provide the output nodes 804P, 804N of the low voltage die 80a, which can be connected (e.g., via bonding wires) to the input nodes of a high voltage die (e.g., including a receiver circuit), in a configuration as exemplified in FIG. 1. The signals OUT.sub.P, OUT.sub.N are filtered by the isolation capacitances 803P, 803N so that a differential signal V.sub.d is produced at the output nodes 804P, 804N.

[0049] The output buffers 8021, 8023 of the tri-state transmitter 802 have three possible output states. In the “high” output state, a pull-up path (e.g., a pull-up transistor) is active (e.g., conductive) and the output node of the buffer is forced to a high value, such as a power supply voltage level V.sub.DD. In the “low” output state, a pull-down path (e.g., a pull-down transistor) is active (e.g., conductive) and the output node of the buffer is forced to a low value, such as a negative or reference voltage level V.sub.SS. In the “high impedance” (HIZ) output state, both the pull-up path and the pull-down path are inactive (e.g., non conductive or off) and the output node of the buffer can be driven externally.

[0050] The transmitter circuit 802′ comprises a logic circuit 805 configured to receive signals PWM.sub.IN and CLK. The logic circuit 805 is configured to produce a control signal TX.sub.DIS that is propagated to the tri-state transmitter 802 to control the operating state of buffers 8021, 8023. The control signal TX.sub.DIS may be generated by the logic circuit 805 as a pulsed signal that normally has a first value (e.g., a high logic value) and switches to a second value (e.g., a low logic value) for a short time T.sub.HIZ each time that an edge (e.g., both rising and falling edges) is detected in the clock signal CLK or in the input signal PWM.sub.IN. For instance, the time interval T.sub.HIZ may be in the range of 0.2*T.sub.CLK to 0.25*T.sub.CLK (T.sub.CLK being the period of the clock signal CLK). For instance, the time interval T.sub.HIZ may be in the range of 8 ns to 12 ns; optionally, the time interval T.sub.HIZ may be about 10 ns. The buffers 8021, 8023 may be forced to the high impedance state when the control signal TX.sub.DIS has the first value (e.g., high).

[0051] The transmitter circuit 802′ comprises an output control circuit 806 configured to receive the control signal TX.sub.DIS and configured to drive the output nodes 802P and 802N of buffers 8021 and 8023 (i.e., signals OUT.sub.P and OUT.sub.N) when the buffers 8021 and 8023 are in the high impedance state. In particular, the output control circuit 806 is configured to force signals OUT.sub.P and OUT.sub.N, during the high impedance state of buffers 8021 and 8023 (e.g., when the control signal TX.sub.DIS has the first value), to a voltage V.sub.X that is intermediate between the minimum and maximum values of signals OUT.sub.P and OUT.sub.N (e.g., at the center of the swing range of signals OUT.sub.P and OUT.sub.N).

[0052] Operation of a transmitter circuit 802′ as exemplified in FIG. 8 can be further understood with reference to FIG. 9, which illustrates exemplary time diagrams of signals PWM.sub.IN, CLK, TX.sub.DIS, OUT.sub.P, OUT.sub.N and V.sub.d as possibly received and produced in the transmitter circuit 802′ and low voltage die 80a.

[0053] For instance, the control signal TX.sub.DIS may be normally set to a high logic value (‘1’). As a result of the control signal TX.sub.DIS being high, the tri-state transmitter 802 is in the high impedance state (i.e., both buffers 8021 and 8023 are in the high impedance state) and the signals OUT.sub.P and OUT.sub.N are forced to value V.sub.X by the output control circuit 806. Each time that an edge (both rising edges and falling edges) occurs in signal CLK or signal PWM.sub.IN, the control signal TX.sub.DIS is set by the logic circuit 805 to a low logic value (‘0’) for a short period of time T.sub.HIZ. As a result of the control signal TX.sub.DIS being low, the tri-state transmitter 802 operates normally, i.e., signals OUT.sub.P and OUT.sub.N are driven by buffers 8021 and 8023 as a function of the value of the input signal PWM.sub.IN (e.g., with signal OUT.sub.P having the same polarity as signal PWM.sub.IN, and signal OUT.sub.N having the opposite polarity of signal PWM.sub.IN). The transition from the high impedance state to the active states (high or low) of the buffers 8021 and 8023 is fast. Therefore, the transitions of signals OUT.sub.P and OUT.sub.N from the intermediate value V.sub.X to the extreme values (minimum or maximum) are sharp (e.g., may have a duration in the range of 10 ps to 100 ps). Since signals OUT.sub.P and OUT.sub.N are filtered by the capacitances 803P and 803N, corresponding pulses are produced in the differential signal V.sub.d, as exemplified in FIG. 9.

[0054] After a time interval T.sub.HIZ (determined by the logic circuit 805), the control signal TX.sub.DIS returns to its normal value (e.g., high in the example considered herein), so that the hi-state transmitter 802 returns in the high impedance state and signals OUT.sub.P and OUT.sub.N are again forced to value V.sub.X by the output control circuit 806. The transitions of signals OUT.sub.P and OUT.sub.N from the extreme values (minimum or maximum) to the intermediate value V.sub.X are slow (e.g., may have a duration in the range of 30 ns to 40 ns, or generally some orders of magnitude higher than the duration of the transitions from the intermediate value V.sub.X to the extreme values). Since signals OUT.sub.P and OUT.sub.N are filtered by the capacitances 803P and 803N, no pulses (or negligible pulses) are produced in the differential signal V.sub.d, as exemplified in FIG. 9.

[0055] FIG. 10 is a circuit diagram exemplary of a possible implementation of a transmitter circuit 802′ according to one or more embodiments. In particular, FIG. 10 is exemplary of possible implementation details of the logic circuit 805, the tri-state transmitter 802 and the output control circuit 806.

[0056] As exemplified in FIG. 10, the logic circuit 805 may comprise a first XOR gate 8051 configured to receive the input signal PWM.sub.IN and a delayed replica of the input signal PWM.sub.IN (e.g., delayed by means of an interposed buffer stage 8052). The logic circuit 805 may comprise a second XOR gate 8053 configured to receive the clock signal CLK and a delayed replica of the clock signal CLK (e.g., delayed by means of an interposed buffer stage 8054). Therefore, the signal produced by the XOR gate 8051 is set to a high logic value at each commutation (edge) of signal PWM.sub.IN, and maintains the high logic value (only) for a (short) time period T.sub.HIZ equal to the delay of the buffer stage 8052. Similarly, the signal produced by the XOR gate 8053 is set to a high logic value at each commutation (edge) of signal CLK, and maintains the high logic value (only) for a (short) time period T.sub.HIZ equal to the delay of the buffer stage 8054. The delays of the buffer stages 8052 and 8054 may be equal. The logic circuit 805 may comprise a NOR gate 8055 configured to receive the signals produced by the XOR gates 8051 and 8053, thereby producing the control signal TX.sub.DIS that is normally high and goes too low for a (short) time period T.sub.HIZ at each commutation (edge) of signal PWM.sub.IN or signal CLK, as discussed with reference to FIG. 9.

[0057] As exemplified in FIG. 10, the tri-state transmitter circuit 802 may comprise a first buffer stage 8021 and a second buffer stage 8023.

[0058] The first buffer stage 8021 may comprise a half-bridge circuit connected between a positive supply voltage node V.sub.DD and a negative or reference supply voltage node V.sub.SS. The half-bridge circuit may comprise a high-side transistor (e.g., p-channel MOS transistor) and a low-side transistor (e.g., n-channel MOS transistor). A node 802P intermediate the high-side transistor and the low-side transistor may be configured to produce the signal OUT.sub.P. The high-side transistor may be controlled by a respective control signal produced by an OR gate that receives signal TX.sub.DIS and an inverted replica of signal PWM.sub.IN as input signals. A buffer or delay stage may be coupled between the output of the OR gate and the control terminal of the high-side transistor. Therefore, the high-side transistor may be active (and signal OUT.sub.P may be forced to the high value V.sub.DD) when TX.sub.DIS=0 and PWM.sub.IN=1. The low-side transistor may be controlled by a respective control signal produced by an AND gate that receives an inverted replica of signal TX.sub.DIS and an inverted replica of signal PWM.sub.IN as input signals. A buffer or delay stage may be coupled between the output of the AND gate and the control terminal of the low-side transistor. Therefore, the low-side transistor may be active (and signal OUT.sub.P may be forced to the low value V.sub.SS) when TX.sub.DIS=0 and PWM.sub.IN=0. Both the high-side transistor and the low-side transistor may be inactive (and signal OUT.sub.P may be forced to the intermediate value V.sub.X under the operation of the output control circuit 806) when TX.sub.DIS=1, irrespective of the value of signal PWM.sub.IN.

[0059] Similarly, the second buffer stage 8023 may comprise a half-bridge circuit connected between the positive supply voltage node V.sub.DD and the negative or reference supply voltage node V.sub.SS. The half-bridge circuit may comprise a high-side transistor (e.g., p-channel MOS transistor) and a low-side transistor (e.g., n-channel MOS transistor). A node 802N intermediate the high-side transistor and the low-side transistor may be configured to produce the signal OUT.sub.N. The high-side transistor may be controlled by a respective control signal produced by an OR gate that receives signal TX.sub.DIS and signal PWM.sub.IN as input signals. A buffer or delay stage may be coupled between the output of the OR gate and the control terminal of the high-side transistor. Therefore, the high-side transistor may be active (and signal OUT.sub.N may be forced to the high value V.sub.DD) when TX.sub.DIS=0 and PWM.sub.IN=0. The low-side transistor may be controlled by a respective control signal produced by an AND gate that receives an inverted replica of signal TX.sub.DIS and signal PWM.sub.IN as input signals. A buffer or delay stage may be coupled between the output of the AND gate and the control terminal of the low-side transistor. Therefore, the low-side transistor may be active (and signal OUT.sub.N may be forced to the low value V.sub.SS) when TX.sub.DIS=0 and PWM.sub.IN=1. Both the high-side transistor and the low-side transistor may be inactive (and signal OUT.sub.N may be forced to the intermediate value V.sub.X under the operation of the output control circuit 806) when TX.sub.DIS=1, irrespective of the value of signal PWM.sub.IN.

[0060] As exemplified in FIG. 10, signal PWM.sub.IN may be slightly delayed (e.g., by a buffer stage 8011) before being propagated to the logic gates which drive the buffers 8021 and 8023.

[0061] As exemplified in FIG. 10, the output control circuit 806 may comprise a (e.g., resistive) voltage divider arranged between the positive supply voltage node V.sub.DD and the negative or reference supply voltage node V.sub.SS. For instance, the voltage divider may comprise a series arrangement of two resistors R1 and R2; a node intermediate resistors R1 and R2 may produce the intermediate voltage level V.sub.X. Optionally, resistors R1 and R2 may have the same resistance value, so that V.sub.X is centered with respect to the supply rail V.sub.DD to V.sub.SS. The node intermediate resistors R1 and R2 may be selectively connected to the output nodes 802P and 802N of the buffer stages 8021 and 8023 by means of respective switches controlled by the control signal TX.sub.DIS. The switches are set to a conductive state when the tri-state transmitter 802 is in the high impedance state (e.g., when TX.sub.DIS=1). Optionally, a capacitance may be coupled in parallel to the resistor R2 between the intermediate node of the voltage divider and the negative or reference supply voltage node V.sub.SS.

[0062] It is noted that, when operating in the high impedance state, the transmitter circuit 802′ may be vulnerable to common mode transient pulses. Therefore, one or more embodiments as exemplified in FIG. 11 may additionally comprise a protection circuit 807. The protection circuit 807 may comprise a first capacitance C.sub.P and a second capacitance C.sub.N that are selectively couplable (e.g., by means of respective switches controlled by signal TX.sub.DIS) to the nodes 802P and 802N, respectively. When TX.sub.DIS=0 (active transmission of the tri-state transmitter 802), the capacitances C.sub.P, C.sub.N are decoupled from the nodes 802P, 802N and are charged to V.sub.DD or V.sub.SS according to the value of the input signal PWM.sub.IN. In particular, the capacitance C.sub.P may be charged to V.sub.DD when PWM.sub.IN=1 and charged to V.sub.SS when PWM.sub.IN=0; the capacitance C.sub.N may be charged to V.sub.DD when PWM.sub.IN=0 and charged to V.sub.SS when PWM.sub.IN=1. When TX.sub.DIS=1 (high impedance state of the tri-state transmitter 802), the capacitances C.sub.P and C.sub.N are coupled to nodes 802P and 802N, respectively. Therefore, if a common mode pulse occurs in the signals OUT.sub.P, OUT.sub.N, the capacitances C.sub.P, C.sub.N can absorb the current avoiding the generation of a spurious transition.

[0063] FIG. 11 is a circuit diagram exemplary of a possible implementation of a transmitter circuit 802′ according to one or more embodiments. In particular, FIG. 11 is exemplary of possible implementation details of the protection circuit 807.

[0064] As exemplified in FIG. 11, the protection circuit 807 may comprise a first capacitance C.sub.P coupled to the output node of a respective half-bridge circuit connected between the positive supply voltage node V.sub.DD and the negative or reference supply voltage node V.sub.SS. The half-bridge circuit may comprise a high-side transistor (e.g., p-channel MOS transistor) and a low-side transistor (e.g., n-channel MOS transistor). A node intermediate the high-side transistor and the low-side transistor may be coupled to the capacitance C.sub.P, and may be selectively coupled to node 802P via a switch controlled by signal TX.sub.DIS (e.g., set to a conductive state when TX.sub.DIS=1). The high-side transistor may be controlled by a respective control signal produced by an OR gate that receives signal TX.sub.DIS and an inverted replica of signal PWM.sub.IN as input signals. Therefore, the high-side transistor may be active (and the capacitance C.sub.P may be charged to V.sub.DD) when TX.sub.DIS=0 and PWM.sub.IN=1. The low-side transistor may be controlled by a respective control signal produced by an AND gate that receives an inverted replica of signal TX.sub.DIS and an inverted replica of signal PWM.sub.IN as input signals. Therefore, the low-side transistor may be active (and the capacitance C.sub.P may be charged to V.sub.SS) when TX.sub.DIS=0 and PWM.sub.IN=0. Both the high-side transistor and the low-side transistor may be inactive (and the capacitance C.sub.P may be coupled to node 802P) when TX.sub.DIS=1, irrespective of the value of signal PWM.sub.IN.

[0065] Similarly, the protection circuit 807 may comprise a second capacitance C.sub.N coupled to the output node of a respective half-bridge circuit connected between the positive supply voltage node V.sub.DD and the negative or reference supply voltage node V.sub.SS. The half-bridge circuit may comprise a high-side transistor (e.g., p-channel MOS transistor) and a low-side transistor (e.g., n-channel MOS transistor). A node intermediate the high-side transistor and the low-side transistor may be coupled to the capacitance C.sub.N, and may be selectively coupled to node 802N via a switch controlled by signal TX.sub.DIS (e.g., set to a conductive state when TX.sub.DIS=1). The high-side transistor may be controlled by a respective control signal produced by an OR gate that receives signal TX.sub.DIS and signal PWM.sub.IN as input signals. Therefore, the high-side transistor may be active (and the capacitance C.sub.N may be charged to V.sub.DD) when TX.sub.DIS=0 and PWM.sub.IN=0. The low-side transistor may be controlled by a respective control signal produced by an AND gate that receives an inverted replica of signal TX.sub.DIS and signal PWM.sub.IN as input signals. Therefore, the low-side transistor may be active (and the capacitance C.sub.N may be charged to V.sub.SS) when TX.sub.DIS=0 and PWM.sub.IN=1. Both the high-side transistor and the low-side transistor may be inactive (and the capacitance C.sub.N may be coupled to node 802N) when TX.sub.DIS=1, irrespective of the value of signal PWM.sub.IN. Therefore, one or more embodiments as exemplified in FIG. 11 may provide improved common mode transient immunity (CMTI).

[0066] FIG. 12 is exemplary of a comparison between signals in an isolated driver device according to one or more embodiments (signals in portion A of FIG. 12), and signals in an isolated driver device based on OOK modulation (portion B of FIG. 12). As exemplified in FIG. 12, the reaction times (e.g., the time needed for “correcting” a missed pulse MP12 in the receiver high voltage die 10b) T.sub.react_OOK and T.sub.react_retry are comparable. Advantageously, in one or more embodiments (portion A) signal PWM.sub.RX does not suffer from a decoding delay T.sub.decoding.

[0067] One or more embodiments have been disclosed herein, where the control signal TX.sub.DIS is generated as a function of the edges detected in both signals PWM.sub.IN and CLK. However, due to the frequency of signal CLK being higher than the frequency of signal PWM.sub.IN, and considering that the edges of signal PWM.sub.IN may be coincident with certain edges of signal CLK (as exemplified in FIG. 9), one or more embodiments may generate the control signal TX.sub.DIS as a function of the edges detected in signal CLK only, without affecting the operating principle of the embodiments. For instance, in one or more embodiments the logic circuit 805 may include (only) the XOR gate 8053 and the delay stage 8054, and may include an inverter coupled to the output of the XOR gate 8053 to generate signal TX.sub.DIS, in the place of the NOR gate 8055. On one hand, such simpler embodiments may be effective in applications where the frequency of the input PWM signal PWM.sub.IN is much lower than the frequency of the clock signal CLK. On the other hand, detecting edges in both signals PWM.sub.IN and CLK may improve the robustness of the transmission.

[0068] One or more embodiments may thus provide one or more of the following advantages:

[0069] possibility of decoding the PWM input signal without delay;

[0070] no need for an oscillator circuit for generating a high frequency carrier signal for modulation; and

[0071] a simple implementation of the receiver circuit.

[0072] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the extent of protection.

[0073] A circuit (802′), may be summarized as including a first input node (801a) configured to receive a pulse-width modulated input signal (PWM.sub.IN); a second input node (801b) configured to receive a clock signal (CLK) having a frequency higher than the frequency of said pulse-width modulated input signal (PWM.sub.IN); a logic circuit (805) sensitive to said clock signal (CLK) and configured to generate a control signal (TX.sub.DIS) as a function of said clock signal (CLK), wherein said control signal (TX.sub.DIS) is normally set to a first logic value, and is periodically set to a second logic value for a transmission time interval (T.sub.HIZ) in response to an edge being detected in said clock signal (CLK), said transmission time interval (T.sub.HIZ) being shorter than half clock period of said clock signal (CLK); a tri-state transmitter (802) coupled to the first input node (801a) to receive said pulse-width modulated input signal (PWM.sub.IN) and sensitive to said control signal (TX.sub.DIS), the tri-state transmitter (802) being configured to produce a first output signal (OUT.sub.P) at a first transmitter output node (802P) and a second output signal (OUT.sub.N) at a second transmitter output node (802N), the first output signal (OUT.sub.P) and the second output signal (OUT.sub.N) having a voltage swing between a positive supply voltage (V.sub.DD) and a reference supply voltage (V.sub.SS); an output control circuit (806) sensitive to said control signal (TX.sub.DIS) and coupled to said first transmitter output node (802P) and said second transmitter output node (802N); wherein in response to said control signal (TX.sub.DIS) having said first logic value, said tri-state transmitter (802) sets said first transmitter output node (802P) and said second transmitter output node (802N) to a high impedance state, and said output control circuit (806) drives said first transmitter output node (802P) and said second transmitter output node (802N) to an intermediate voltage level (V.sub.X) between said positive supply voltage (V.sub.DD) and said reference supply voltage (V.sub.SS); and in response to said control signal (TX.sub.DIS) having said second logic value, said tri-state transmitter (802) drives said first transmitter output node (802P) to said positive supply voltage (V.sub.DD) or to said reference supply voltage (V.sub.SS) according to the logic value of said pulse-width modulated input signal (PWM.sub.IN), and drives said second transmitter output node (802P) to said positive supply voltage (V.sub.DD) or to said reference supply voltage (V.sub.SS) according to the inverted logic value of said pulse-width modulated input signal (PWM .sub.IN), wherein said tri-state transmitter (802) is faster than said output control circuit (806) in driving said first transmitter output node (802P) and said second transmitter output node (802N).

[0074] Said tri-state transmitter (802) may drive said first transmitter output node (802P) and said second transmitter output node (802N) to said positive supply voltage (V.sub.DD) and to said reference supply voltage (V.sub.SS) with a respective transition time that may be at least 100 times shorter than the transition time with which said output control circuit (806) may drive said first transmitter output node (802P) and said second transmitter output node (802N) to said intermediate voltage level (V.sub.X).

[0075] Said tri-state transmitter (802) may drive said first transmitter output node (802P) and said second transmitter output node (802N) to said positive supply voltage (V.sub.DD) and to said reference supply voltage (V.sub.SS) with a respective transition time in the range of 10 ps to 100 ps, and said output control circuit (806) may drive said first transmitter output node (802P) and said second transmitter output node (802N) to said intermediate voltage level (V.sub.X) with a respective transition time in the range of 30 ns to 40 ns.

[0076] Said logic circuit (805) may include a first delay circuit element (8054) configured to produce a delayed replica of said clock signal (CLK); a first XOR gate (8053) configured to receive said clock signal (CLK) and said delayed replica of said clock signal (CLK) as input; and an inverter circuit configured to invert the output signal from said first XOR gate (8053) to produce said control signal (TX.sub.DIS).

[0077] Said logic circuit (805) may be further sensitive to said pulse-width modulated input signal (PWM.sub.IN) and may be configured to generate said control signal (TX.sub.DIS) further as a function of said pulse-width modulated input signal (PWM.sub.IN), wherein said control signal (TX.sub.DIS) may be set to said second logic value for said transmission time interval (T.sub.HIZ) may be in response to an edge being detected in said pulse-width modulated input signal (PWM.sub.IN).

[0078] Said logic circuit (805) may include a first delay circuit element (8054) configured to produce a delayed replica of said clock signal (CLK); a first XOR gate (8053) configured to receive said clock signal (CLK) and said delayed replica of said clock signal (CLK) as input; a second delay circuit element (8052) configured to produce a delayed replica of said pulse-width modulated input signal (PWM.sub.IN); a second XOR gate (8051) configured to receive said pulse-width modulated input signal (PWM.sub.IN) and said delayed replica of said pulse-width modulated input signal (PWM.sub.IN) as input; and a NOR gate (8055) configured to receive the output signals from said first XOR gate (8053) and said second XOR gate (8051) to produce said control signal (TX.sub.DIS).

[0079] Said tri-state transmitter (802) may include a first half-bridge circuit (8021) arranged between said positive supply voltage (V.sub.DD) and said reference supply voltage (V.sub.SS) and having an intermediate node coupled to said first transmitter output node (802P); and a second half-bridge circuit (8023) arranged between said positive supply voltage (V.sub.DD) and said reference supply voltage (V.sub.SS) and having an intermediate node coupled to said second transmitter output node (802N); wherein a high-side switch of said first half-bridge circuit (8021) may be conductive in response to said control signal (TX.sub.DIS) having said second logic value and said pulse-width modulated input signal (PWM.sub.IN) having a high logic value; a low-side switch of said first half-bridge circuit (8021) may be conductive in response to said control signal (TX.sub.DIS) having said second logic value and said pulse-width modulated input signal (PWM.sub.IN) having a low logic value; a high-side switch of said second half-bridge circuit (8023) may be conductive in response to said control signal (TX.sub.DIS) having said second logic value and said pulse-width modulated input signal (PWM.sub.IN) having a low logic value; a low-side switch of said second half-bridge circuit (8023) may be conductive in response to said control signal (TX.sub.DIS) having said second logic value and said pulse-width modulated input signal (PWM.sub.IN) having a high logic value; and said high-side switch and said low-side switch of said first half-bridge circuit (8021), as well as said high-side switch and said low-side switch of said second half-bridge circuit (8023), may be non-conductive in response to said control signal (TX.sub.DIS) having said first logic value.

[0080] Said output control circuit (806) may include a voltage divider (R1, R2) arranged between said positive supply voltage (V.sub.DD) and said reference supply voltage (V.sub.SS), and respective switches configured to selectively couple an intermediate node of said voltage divider (R1, R2) to said first transmitter output node (802P) and said second transmitter output node (802N) in response to said control signal (TX.sub.DIS) having said first logic value.

[0081] The circuit (802′) may include a protection circuit (807), wherein the protection circuit (807) may include a first protection capacitance (C.sub.P), a second protection capacitance (C.sub.N), and protection circuitry configured to charge said first protection capacitance (C.sub.P) to said positive supply voltage (V.sub.DD) in response to said control signal (TX.sub.DIS) having said second logic value and said pulse-width modulated input signal (PWM.sub.IN) having a high logic value; charge said first protection capacitance (C.sub.P) to said reference supply voltage (V.sub.SS) in response to said control signal (TX.sub.DIS) having said second logic value and said pulse-width modulated input signal (PWM.sub.IN) having a low logic value; charge said second protection capacitance (C.sub.N) to said positive supply voltage (V.sub.DD) in response to said control signal (TX.sub.DIS) having said second logic value and said pulse-width modulated input signal (PWM.sub.IN) having a low logic value; charge said second protection capacitance (C.sub.N) to said reference supply voltage (V.sub.SS) in response to said control signal (TX.sub.DIS) having said second logic value and said pulse-width modulated input signal (PWM.sub.IN) having a high logic value; and couple said first protection capacitance (C.sub.P) to said first transmitter output node (802P) and couple said second protection capacitance (C.sub.N) to said second transmitter output node (802N) in response to said control signal (TX.sub.DIS) having said first logic value.

[0082] The circuit (80a) may include a first differential output node (804P) and a second differential output node (804N); a first isolation capacitance (803P) coupled between said first transmitter output node (802P) and said first differential output node (804P); and a second isolation capacitance (803N) coupled between said second transmitter output node (802N) and said second differential output node (804N); wherein a differential output signal (V.sub.d) indicative of said pulse-width modulated input signal (PWM.sub.IN) may be produced between said first differential output node (804P) and said second differential output node (804N).

[0083] An isolated driver device, may be summarized as including a first semiconductor die having a transmitter circuit (80a) implemented thereon; a second semiconductor die having a first receiver input node and a second receiver input node, the first receiver input node being electrically coupled to the first differential output node (804P) of the transmitter circuit (80a) and the second receiver input node being electrically coupled to the second differential output node (804N) of the transmitter circuit (80a) to receive said differential output signal (V.sub.d); wherein the second semiconductor die has a receiver circuit implemented thereon, the receiver circuit being configured to receive said differential output signal (V.sub.d), and to set a driving signal (PWM.sub.RX) to a first logic value in response to a positive pulse being detected in said differential output signal (V.sub.d) and to a second logic value in response to a negative pulse being detected in said differential output signal (V.sub.d).

[0084] The second semiconductor die may have a driver circuit implemented thereon, the driver circuit including a half-bridge circuit arranged between a positive supply voltage pin (VH) and a reference supply voltage pin (VL) and driven by said driving signal (PWM.sub.RX) to produce an output switching signal (OUT).

[0085] An electronic system, may be summarized as including a processing unit configured to generate said pulse-width modulated input signal (PWM.sub.IN) and said clock signal (CLK), and an isolated driver device coupled to the processing unit to receive said pulse-width modulated input signal (PWM.sub.IN) and said clock signal (CLK).

[0086] A method of encoding a pulse-width modulated signal (PWM.sub.IN) into a differential pulsed signal (V.sub.d), the method may be summarized as including receiving said pulse-width modulated signal (PWM.sub.IN); providing a clock signal (CLK) having a frequency higher than the frequency of said pulse-width modulated signal (PWM.sub.IN); generating a control signal (TX.sub.DIS) as a function of said clock signal (CLK), wherein said control signal (TX.sub.DIS) is normally set to a first logic value, and is periodically set to a second logic value for a transmission time interval (T.sub.HIZ) in response to an edge being detected in said clock signal (CLK), said transmission time interval (T.sub.HIZ) being shorter than half clock period of said clock signal (CLK); producing a first output signal (OUT.sub.P) and a second output signal (OUT.sub.N), the first output signal (OUT.sub.P) and the second output signal (OUT.sub.N) having a voltage swing between a positive supply voltage (V.sub.DD) and a reference supply voltage (V.sub.SS); and applying capacitive filtering to said first output signal (OUT.sub.P) and said second output signal (OUT.sub.N) to produce respective first and second filtered output signals, wherein said differential pulsed signal (V.sub.d) is produced as a difference between said first filtered output signal and said second filtered output signal; wherein producing said first output signal (OUT.sub.P) and said second output signal (OUT.sub.N) includes in response to said control signal (TX.sub.DIS) having said first logic value, setting said first output signal (OUT.sub.P) and said second output signal (OUT.sub.N) to an intermediate voltage level (V.sub.X) between said positive supply voltage (V.sub.DD) and said reference supply voltage (V.sub.SS); and in response to said control signal (TX.sub.DIS) having said second logic value, setting said first output signal (OUT.sub.P) to said positive supply voltage (V.sub.DD) or to said reference supply voltage (V.sub.SS) according to the logic value of said pulse-width modulated input signal (PWM.sub.IN), and setting said second output signal (OUT.sub.N) to said positive supply voltage (V.sub.DD) or to said reference supply voltage (V.sub.SS) according to the inverted logic value of said pulse-width modulated input signal (PWM.sub.IN), wherein a time interval for setting said first output signal (OUT.sub.P) and said second output signal (OUT.sub.N) to said positive supply voltage (V.sub.DD) or to said reference supply voltage (V.sub.SS) is shorter than a time interval for setting said first output signal (OUT.sub.P) and said second output signal (OUT.sub.N) to said intermediate voltage level (V.sub.X).

[0087] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.