BICMOS-based transceiver for millimeter wave frequency applications

Abstract

An e-band transceiver includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a surface mounted technology (SMT) module on which is mounted a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifier. The receiver circuit of the e-band transceiver includes a receiver-side SMT module on which is mounted a receiver-side SiGe BiCMOS converter, a GaAs pHEMT low noise amplifier coupled to the receiver-side SiGe BiCMOS converter, and a receiver-side microstrip/waveguide interface coupled to the receiver-side GaAs pHEMT low noise amplifier.

Claims

1. An apparatus comprising: a package having an interface; an up-converter (i) implemented in a bipolar-plus-CMOS technology, (ii) disposed in said package, (iii) having a channel filter controlled by a channel parameter and (iv) configured to generate a transmit signal, wherein said transmit signal has a frequency in a millimeter wave frequency range; a power amplifier (i) implemented in a pseudomorphic high-electron-mobility transistor technology, (ii) disposed in said package, and (iii) configured to amplify said transmit signal; a transmit waveguide configured to carry said transmit signal from said power amplifier to said interface; and a memory configured to store calibration data that allows a chip-by-chip calibration, wherein said calibration data includes said channel parameter of said channel filter.

2. The apparatus according to claim 1, wherein said frequency of said transmit signal is between approximately 40 gigahertz and approximately 86 gigahertz.

3. The apparatus according to claim 1, wherein said frequency of said transmit signal is in an E-band.

4. The apparatus according to claim 1, wherein said calibration data avoids a calibration rejection procedure.

5. The apparatus according to claim 1, wherein (i) said a bipolar-plus-CMOS technology comprises a Silicon-Germanium bipolar-plus-CMOS technology and (ii) said pseudomorphic high-electron-mobility transistor technology comprises a Gallium-Arsenide pseudomorphic high-electron-mobility transistor technology.

6. The apparatus according to claim 1, further comprising a digital interface configured to control one or more of (i) a bias, (ii) a type of said channel filter, (iii) an output power level of said transmit signal or (iv) any combination thereof.

7. The apparatus according to claim 6, wherein the digital interface is configured as one of (i) an integrated circuit communications interface or (ii) a serial-peripheral interface.

8. The apparatus according to claim 1, wherein said calibration data compensates for process variations in said power amplifier.

9. The apparatus according to claim 1, wherein said package, said up-converter, said power amplifier and said transmit waveguide form part of a system-in-package assembly.

10. The apparatus according to claim 1, further comprising: an additional package having an additional interface; a low-noise amplifier (i) implemented in said pseudomorphic high-electron-mobility transistor technology, (ii) disposed in said additional package, and (iii) configured to amplify a receive signal, wherein said receive signal has an additional frequency in said millimeter wave frequency range; an additional waveguide configured to carry said receive signal from said additional interface to said low-noise amplifier; a down-converter (i) implemented in said bipolar-plus-CMOS technology, (ii) disposed in said additional package, (iii) having an additional channel filter controlled by an additional channel parameter and (iv) configured to down-convert said receive signal; and an additional memory configured to store said calibration data, wherein said calibration data includes said additional channel parameter of said additional channel filter.

11. The apparatus according to claim 1, wherein said calibration data includes a mixer bias that rejects leakage in said up-converter from a local oscillator.

12. An apparatus comprising: a package having an interface; a low-noise amplifier (i) implemented in a pseudomorphic high-electron-mobility transistor technology, (ii) disposed in said package, and (iii) configured to amplify a receive signal, wherein said receive signal has a frequency in a millimeter wave frequency range; a waveguide configured to carry said receive signal from said interface to said low-noise amplifier; a down-converter (i) implemented in a bipolar-plus-CMOS technology, (ii) disposed in said package, (iii) having a channel filter controlled by a channel parameter and (iv) configured to down-convert said receive signal; and a memory configured to store calibration data that allows a chip-by-chip calibration, wherein said calibration data includes said channel parameter of said channel filter.

13. The apparatus according to claim 12, wherein said frequency of said receive signal is between approximately 40 gigahertz and approximately 86 gigahertz.

14. The apparatus according to claim 12, wherein said frequency of said receive signal is in an E-band.

15. The apparatus according to claim 12, wherein said calibration data avoids a calibration rejection procedure.

16. The apparatus according to claim 12, wherein (i) said a bipolar-plus-CMOS technology comprises a Silicon-Germanium bipolar-plus-CMOS technology and (ii) said pseudomorphic high-electron-mobility transistor technology comprises a Gallium-Arsenide pseudomorphic high-electron-mobility transistor technology.

17. The apparatus according to claim 12, further comprising a digital interface configured to control one or more of (i) a bias, (ii) a type of said channel filter, (iii) an output power level of a baseband signal or (iv) any combination thereof.

18. The apparatus according to claim 12, wherein said calibration data includes a mixer bias that rejects leakage in said down-converter from a local oscillator.

19. The apparatus according to claim 12, wherein said package, said down-converter, said low-noise amplifier and said receive waveguide form part of a system-in-package assembly.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates one embodiment of a transmitter topology comprising a SMT SiP package configured in accordance with principles of the invention;

(2) FIG. 2 illustrates one embodiment of a receiver topology comprising a SMT SiP package configured in accordance with principles of the invention; and

(3) FIG. 3 illustrates one embodiment of a printed circuit board arrangement usable to implement the topologies of FIGS. 1 and 2.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

(4) The present disclosure relates to a novel transceiver design for millimeter-wave applications. To that end, one aspect of the invention is to harness the benefits of silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) technology which has been found to allow, at millimeter-wave frequencies, a high level of integration of various functions and functionalities, and integration of a complementary metal-oxide semiconductor (CMOS) digital control interface, such as the I.sup.2C (Inter Integrated Circuit Communications) or SPI (or Serial-Peripheral interface) protocols, with the addition of non-volatile memory to store calibration data.

(5) At the same time, however, at millimeter wave frequencies SiGe BiCMOS technology is known to suffer from poor voltage breakdown and output power capability, poor linearity for both up- and down-converters, as well as poor noise figure.

(6) However, the inventors have realized that the drawbacks of SiGe BiCMOS technology can be addressed by incorporating gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) technology into the novel transceiver design. Specifically, GaAs pHEMT provides good output power capabilities, high linearity for up- and down-converters and good receiver noise figure, even up to millimeter-wave frequencies.

(7) Still further, GaAs pHEMT technology is known not to have a high-level of integration due to size constraints and couplings in the substrate. Thus, still another aspect of the invention is to incorporate Surface Mounted Technology (SMT) with a waveguide interface in order to provide a low cost System-in-Package (SiP) assembly on a Printed Circuit Board (PCB) while beneficially avoiding high frequency interfaces. With both SiGe BICMOS and GaAs pHEMT technologies being integrated on a one single SiP using SMT, the limitations and drawbacks of the SiGe BICMOS and GaAs pHEMT technologies, respectively, can be addressed in a complementary fashion, while at the same time achieving a very compact form factor for e-band application transceivers.

(8) Accordingly, the present invention is directed to the integration of a two-chip solution in a low cost SiP that utilizes an SMT package design for e-band applications on both the transmitter side and the receiver side, whereby both SiGe BICMOS and GaAs pHEMT technologies are integrated onto the SMT package in a complementary manner to unexpectedly achieve superior performance at millimeter-wave frequencies.

(9) With reference now to FIG. 1, depicted is one embodiment of a transmitter topology 100 comprising a SMT SiP package 110 configured in accordance with principles of the invention.

(10) The SMT package 110 of FIG. 1 corresponds to the transmitter side of a millimeter-wave e-band transceiver. The SMT interfaces of the package 110 are at low frequency, including the I and Q baseband inputs 120 and the local oscillator input 130. In addition, the millimeter-wave output of the transmitter is provided by a microstrip/waveguide interface 140 which may be configured to couple the output signal to an external waveguide (not shown).

(11) The SMT package 110 is primarily comprised of a SiGe BICMOS converter chip 150 and a GaAs output amplifier 160. The SiGe BICMOS converter chip 150 may be preferably configured to provide the baseband amplification and channel filtering, IF and RF amplification and filtering, up- and down-conversion, gain controls and local oscillator multiplication circuits, in accordance with the topology for chip 150 shown in FIG. 1. It should further be appreciated that the topology of the SiGe BICMOS converter chip 150 may be either direct conversion (one single up- and down-conversion from BB to RF) or superetherodyne conversion (two up- and down-conversions, from Baseband to IF and from IF to RF)

(12) Continuing to refer to FIG. 1, a digital interface 170 may be provided by the SiGe BICMOS converter chip 150, whereby digital control of bias, easy change of functionalities, such as type of channel filters and output power levels, may be readily provided to the SMT package 110. The digital interface 170 may be configured as an I.sup.2C or SPI interface.

(13) Finally, the SMT package 110 of FIG. 1 may comprise a non-volatile memory 180, controlled by the digital interface 170, to provide storage capabilities for calibration data during the SiP production test, for example, thereby advantageously removing the burden of production calibration and tedious setting procedures from the customer. In particular, the calibration of the mixer bias for full rejection of local oscillator leakage, which can change from chip-to-chip, can be stored in the memory 180 inside the SMT package 110 itself during the package production test phase. As such, the end user will not need to employ a calibration rejection procedure. Furthermore, all baseband filters can be tuned, on a chip-by-chip basis, using parameters stored in the memory 180 in order to compensate process variations. Additional calibration parameters can also be stored in the memory 180 during production test to compensate for process variations of the GaAs output amplifier chip 160.

(14) Finally, the GaAs output amplifier 160 of FIG. 1, which is preferably based on GaAs pHEMT technology, is configured to provide higher power levels and higher linearity on the transmitter side.

(15) While FIG. 1 depicted one embodiment of a transmitter topology 100 comprising a SMT SiP package 110 configured in accordance with principles of the invention, FIG. 2 depicts a receiver topology 200 which is configured in accordance with the principles of the invention. Specifically, the SMT package 210 of FIG. 2 corresponds to the receiver side of a millimeter-wave e-band transceiver.

(16) The SMT interfaces of the package 210 of FIG. 2 are configured at a correspondingly low frequency, including the I and Q baseband outputs 220 and the local oscillator input 230. In addition, the millimeter-wave input of the receiver is provided by a microstrip/waveguide interface 240.

(17) As with the transmitter SMT package 110, the receiver SMT package 210 is primarily comprised of a SiGe BICMOS converter chip 250, while the corresponding GaAs chip in the receiver is a GaAs low noise amplifier 260. The SiGe BICMOS converter chip 250 may be preferably configured to provide the baseband amplification and channel filtering, IF and RF amplification and filtering, up- and down-conversion, gain controls and local oscillator multiplication circuits, in accordance with the topology shown in FIG. 1. And, as with the transmitter side of the disclosed transceiver, it should equally be appreciated that the topology of the SiGe BICMOS converter chip 250 may be either direct conversion or superetherodyne conversion.

(18) The SiGe BICMOS converter chip 250 of FIG. 2 may also include a digital interface 270 to provide for digital control of bias, easy change of functionalities, such as type of channel filters and output power levels.

(19) Finally, the SMT package 210 of FIG. 2 may also comprise a non-volatile memory 280, controlled by the digital interface 270, to provide similar storage capabilities, functionalities and benefits as described above with reference to the memory 280 of the transmitter topology of FIG. 1.

(20) The GaAs low noise amplifier 260 of FIG. 2, which is preferably based on GaAs pHEMT technology, is configured to provide low noise and higher linearity on the receiver side.

(21) With reference now to FIG. 3, depicted is one example of a PCB 300 on which the above SMT packages 110 and 210 may be implemented. In certain embodiments, PCB 300 may be a multilayer PCB using, for example, FR-4 for the bottom layer to provide robustness to the package, while a high frequency dielectric may be used as the top layer to allow low loss routing of RF signals and low loss at the microstrip/waveguide interface 310. The PCB on which the SMT packages 110 and 120 are implemented may be compatible with the standard board reflow process with standard low frequency feedthrough for direct current, baseband and local oscillator inputs using any number of the depicted pins 1-58. In order to allow proper alignment of the waveguide interface 310 on the bottom of the package, two dowel pins 320a and 320b may be used at the edges of the waveguide interface 320, as shown in FIG. 3. Of course, it should be appreciated that other known PCB configurations could be used in accordance with the principles of the invention.

(22) Thus, in accordance with the above disclosure, the present invention provides a novel two-chip solution in a single low cost SiP that utilizes an SMT package design for e-band applications on both the transmitter side and the receiver side, whereby both SiGe BICMOS and GaAs pHEMT technologies are integrated onto the SMT package in a complementary manner to unexpectedly achieve superior performance at millimeter-wave frequencies.

(23) The foregoing disclosure has been set forth merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof. Although the disclosure use terminology and acronyms that may not be familiar to the layperson, those skilled in the art will be familiar with the terminology and acronyms used herein.