Circuit for controlling slew rate of a high-side switching element

Abstract

A circuit (11) for controlling slew rate of a high-side switching element (6) in a load switch (5) is described. The circuit includes a variable current source (20) for setting a slew rate. The circuit also includes an amplifier (15) comprising a first input coupled to a fixed voltage source (19), a second input coupled to the variable current source and an output (18) for a drive signal. A feedback path (26) from an input terminal (13), connected or connectable to an output (14) of the switching element, to the second input of the amplifier, includes a series voltage-differentiating element, such as a capacitor (27).

Claims

1. A integrated circuit comprising: at least one slew-rate controlling circuit, each slew-rate controlling circuit comprising: a variable current source for providing a control current for setting a slew rate of a high-side switching element in a load switch, the variable current sourse comprising first and second current sources; a differential amplifier comprising: a first input coupled to a reference voltage source; a second input coupled to the variable current source; and a differential output for a signal for driving the switching element; and a feedback path from a circuit input, connected or connectable to an output of the switching element, to the second input of the amplifier, the feedback path including a series voltage-differentiating element, wherein the first and second current sources are viable current sources and the variable current source is a programmable current source controllable by control logic to allow the slew rate of the high-side switching element to be varied according to application and adjusted according to load conditions; and the control logic configured to set the control current for the variable current source.

2. An integrated circuit according to claim 1, wherein the voltage-differentiating element is a capacitor.

3. An integrated circuit according to claim 1, wherein the switching element is an MOS transistor.

4. An integrated circuit according to claim 1, wherein the switching element is an nMOS transistor.

5. An integrated circuit according to claim 1, further comprising: a non-inverting buffer between the output of the differential amplifier and a circuit output connected or connectable to a control electrode of the switching element.

6. An integrated circuit according to claim 1, further comprising: a pre-scaler disposed between the circuit input and the voltage-differentiating element.

7. A system comprising: an integrated circuit according to claim 1; and at least one high-side switching element having a control electrode and an output, wherein each circuit is configured to control a respective switching element whereby the output of the differential amplifier is coupled to the control electrode and the output of the switching element is coupled to the circuit input.

8. A system according to claim 7, further comprising: at least one load, each load connected to a respective switching element.

9. A system according to claim 8, wherein the load is stator coil of a motor.

10. A system according to claim 7, wherein the system comprises three each slew-rate controlling circuits.

11. A method of controlling slew rate of a high-side switching element in a load switch using an integrated circuit according to claim 1, the method comprising: setting the control current using the variable current source.

12. A computer program product comprising a non-transitory computer-readable medium carrying or storing a computer program which, when executed by a controller, causes the controller to perform the method of claim 11.

13. An integrated circuit according to claim 1, which is an application-specific integrated circuit.

14. A circuit for controlling slew rate of a high-side switching element in a load switch, the circuit comprising: a variable current source for setting a slew rate; a differential amplifier comprising; a first input coupled to a deference voltage source; a second input coupled to a reference voltage source; and an output for a signal for driving the switching element, and a feedback path from a circuit input, connected or connectable to an output of the switching element, to the second input of the amplifier, the feedback path including a series voltage-differentiating element, and a circuit for selectively locking the driving signal in a given state, the circuit comprising differential amplifiers for determining the state of the signal and gates and switches for setting a signal level at the second input to ensure that the state is locked in the given state.

15. A circuit according to claim 14, further comprising: a non-inverting buffer between the output of the differential amplifier and a circuit output connected or connectable to a control electrode of the switching element.

16. A circuit according to claim 14, further comprising: a pre-scaler disposed between the circuit input and the voltage-differentiating element.

17. A circuit according to claim 14, which is an application-specific integrated circuit.

18. A system comprising: at least one circuit according to claim 14, and at least one high-side switching element having a control electrode and an output, wherein each circuit is configured to control a respective switching element whereby the output of the differential amplifier is coupled to the control electrode and the output of the switching element is coupled to the circuit input.

19. A system according to claim 18, further comprising: at least one load, each load connected to a respective switching element.

20. A system according to claim 18, wherein the system comprises three each slew-rate controlling circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Certain embodiments of the present invention will now be described, by way of example, with reference to FIGS. 3 to 5b of the accompanying drawings, in which:

(2) FIG. 1 is a schematic diagram of a first driver circuit and a switching element;

(3) FIG. 2 is a schematic diagram of a second driver circuit and a switching element;

(4) FIG. 3 is a block diagram of a system for controlling and driving one or more loads;

(5) FIG. 4 is a schematic diagram of a load, a load switch and a high-side gate driver circuit; and

(6) FIGS. 5a and 5b are timing charts schematically illustrating variation in output voltage across a load with time using the high-side gate driver circuit shown in FIG. 4.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

(7) Referring to FIG. 3, a system 1 for controlling and driving one or more loads 2 is shown. A load 2 may be, for example, a coil in motor, a coil in a solenoid or relay, a heater element or other form of a load having a complex impedance Z. The system 1 can be used for controlling a three-phase motor, that is, a motor having three loads 2, or other type of multi-phase device.

(8) The system 1 includes a controller 3, such as a microcontroller, a pre-driver integrated circuit (IC) 4 and a load switch 5 for the, or each, load 2.

(9) A load switch 5 includes a high-side switching element 6 in the form of an n-channel, power metal-oxide-semiconductor field-effect transistor (MOSFET) (herein also referred to as an nMOSFET or simply nMOS transistor).

(10) The nMOS transistor 6 may be a discrete component or may be integrated into a load switch IC or into the pre-driver IC 4. The nMOS transistor 6 is configured as a source follower. The drain D of the nMOS transistor 6 is tied to a positive voltage supply, V.sub.BAT, from a battery (not shown) and the source S is connected to a first, supply-side terminal 7 of the load 2. A second terminal 8 of the load 2 is connected to ground, GND, via a low-side switching element 9. The positive voltage supply need not be provided by a battery, but can be provided from a mains supply or other type of supply.

(11) The pre-driver IC 4 includes control logic 10 and a high-side gate driver circuit 11. The high-side driver circuit 11 has a driver output 12 which is connected to the gate G of the nMOS transistor 6 and a feedback input 13 which is connected to a tap 14 at or between the source S of the nMOS transistor 6 and the supply-side terminal 7. The tap 14 measures the output of the nMOS transistor 6, i.e. a driver output voltage, V.sub.OUT, which appears across the load 2.

(12) Referring to FIG. 4, a load 2, a load switch 5 and a high-side gate driver circuit 11 are shown in more detail.

(13) As explained earlier, the drain D of the nMOS transistor 6 is tied to the positive voltage supply, V.sub.BAT, and the source S is connected to a first terminal 7 of the load 2. A second terminal 8 of the load 2 is connected to ground, GND, via a low-side switching element 6.

(14) The nMOS transistor 6 is driven by a differential amplifier 15 (herein referred to as the driving differential amplifier) having non-inverting and inverting inputs and an output 18.

(15) A voltage source 19 is connected between ground and the non-inverting input of the amplifier 15 and provides a fixed reference voltage, V.sub.ref, to the driving differential amplifier 15.

(16) The high-side gate driver circuit 11 includes a programmable current source 20 which is controlled by control logic 10 (FIG. 3). The programmable current source 20 comprises a first current source 21, a first switch 22, a second switch 23 and a second current source 24 arranged between supply line, V.sub.DD, and ground, GND. The programmable current source 20 is capable of providing variable currents having positive and negative slopes. The programmable current source 20 provides a control current, i.sub.CTRL, to the inverting input of the driving differential amplifier 15 via node 25.

(17) The high-side gate driver circuit 11 includes a feedback path 26 between the feedback input 13 and the inverting input of the driving differential amplifier 15 via node 25. The path 26 includes a series voltage-differentiating element 27. The voltage differentiating element 27 takes the form of a capacitor 27. However, other forms of voltage-differentiating element 27 can be used, such as a signal processor (not shown). Using a signal processor (not shown) as a voltage-differentiating element 27 can allow the properties of the voltage-differentiating element 27 to be varied.

(18) The high-side gate driver circuit 11 may include an optional circuit 28 for selectively locking the drive signal at the output 18 to HIGH, i.e. ON, or LOW, i.e. OFF. The level locking circuit 28 includes first and second differential amplifiers 29, 30 having respective non-inverting and inverting inputs and respective outputs 36, 37. Each non-inverting input is connected to the output 18 of the differential amplifier 15 and each inverting input is connected to a respective voltage source 38, 39. The voltage source 38, 39 provide damping thresholds for ON and OFF states respectively. The clamping threshold of the first voltage source 38 is just below, e.g. of the order of 100 mV, below the ON voltage level and the clamping threshold of the second voltage threshold 39 is just above, e.g. of the order of 100 mV, above the OFF voltage level. The first and second differential amplifiers 29, 30 are used to determine whether the drive signal is ON or OFF respectively.

(19) The lock circuit 28 includes first and second two input AND gates 40, 41. The outputs 36, 37 of the first and second differential amplifiers 29, 30 are connected to respective first inputs of the AND gates 40, 41. The control logic 10 (FIG. 3) provides control signals OFF, ON to respective second inputs of the AND gates 40, 41. The AND gates 40, 41 have respective outputs 42, 43 control first and second switches 44, 45 arranged in totem pole configuration between a positive supply rail, 2V.sub.ref, and ground, GND and having a tap 46 connected to the feedback path 26 between the capacitor 27 and the node 25. V.sub.ref can be, for example, the band gap voltage, around 1.2 V. However, V.sub.ref can take other values.

(20) The high-side gate driver circuit 11 may include an optional non-inverting buffer 47 between the output 18 of the driving differential amplifier 15 and the drive output 15. The non-inverting buffer 47 may comprise an nMOS transistor 48 and a pMOS transistor 49 arranged in a push-pull configuration between positive supply rail, V.sub.CP, and ground, GND. The non-inverting buffer 47 includes a resistive bypass 50 to help finally establish the correct gate voltage. The resistive bypass 50 takes the form of a resistor.

(21) The high-side gate driver circuit 11 may include an optional pre-scaler 51 connected between the feedback input 13 and capacitor 27. The pre-scaler 51 can be used to step down the driver output voltage, V.sub.OUT. The pre-scaler 51 can take the form of a voltage divider.

(22) The high-side gate driver circuit 11 may also include a switch 52 between the driver output 12 and feedback input 13. The switch can be used to help ensure a low-value ohmic gate short for improved EMC immunity. The switch 52 can take the form of a nMOS gate-source. The switch can be controlled by gate output 42.

(23) Operation

(24) Referring to FIGS. 3, 4, 5a and 5b, slew rate control will now be described in more detail.

(25) The controller 3, via the pre-driver control logic 10, is used to set a desired slew rate. The desired slew rate depends on use and type of load (e.g. motor coil, heater element etc.) and involves considering electromagnetic emission levels and power consumption.

(26) During turn on, the driver output voltage, V.sub.OUT, is given by equation (1) below, namely
V.sub.OUT(1/C.sub.FB)i.sub.CTRLdt(1)

(27) While a control current, i.sub.CTRL, is supplied, a drive signal is applied to the gate of the nMOS transistor 6 and gate charge Q.sub.G increases. The rate of change of driver output voltage, i.e. slew rate, can be approximated by equation (2) below, namely:
dV.sub.OUT/dt(1/C.sub.FB)i.sub.CTRL(2)

(28) Even though the value of the capacitor 27 is fixed, the slew rate can be set using programmable current source 20. If a signal processor or other form of variable and/or programmable voltage-differentiating element 27 is used, then the value of capacitance C.sub.FB need not be fixed and so slew rate can be variably set using the voltage-differentiating element 27.

(29) FIGS. 5a and 5b schematically illustrate behaviour of the driver output voltage, V.sub.OUT, on control signals OFF and ON from control logic 10.

(30) Referring to FIGS. 3, 4 and 5a, the control logic 10 switches the control signal ON from LOW to HIGH. This causes the programmable current source 20 to provide a positive control current, i.sub.CTRL, to the inverting input of the driving differential amplifier 15. There is a propagation delay, t.sub.start, before the driver output voltage, V.sub.OUT, starts to rise to 10% of the positive supply rail voltage, V.sub.BAT. Thereafter, the rate of increase in output voltage, V.sub.OUT, is defined by (1/C.sub.FB) i.sub.CTRL. The output voltage reaches 90% of the positive supply rail voltage, V.sub.BAT, after an elapsed time, t.sub.slope.

(31) If a locking circuit 28 is used, then once the differential amplifier output 18 exceeds the upper clamping threshold voltage level, then the circuit 28 locks the output 18 and, thus, the driver output voltage, V.sub.OUT.

(32) The control logic 10 can then switch the control signal ON from HIGH to LOW.

(33) A similar process is used to switch the load switch 5 off.

(34) Referring to FIGS. 3, 4 and 5b, the control logic 10 switches the control signal OFF from LOW to HIGH. This causes the programmable current source 20 to provide a negative control current, i.sub.CTRL, to the inverting input of the driving differential amplifier 15. There is a propagation delay, t.sub.start, before the driver output voltage, V.sub.OUT, starts to fall by 10%. Thereafter, the rate of decrease in output voltage, V.sub.OUT, is defined by (1/C.sub.FB) i.sub.CTRL. The output voltage reaches 10% of the positive supply rail voltage, V.sub.BAT, after an elapsed time, t.sub.slope.

(35) If a locking circuit 28 is used, then once the differential amplifier output 18 falls below the upper clamping threshold voltage level, then the circuit 28 locks the output 18 and, thus, the driver output voltage, V.sub.OUT.

(36) The control logic 10 can then switch the control signal OFF from HIGH to LOW.

(37) If the system 1 includes a multi-phase device having multiple loads 2, then a high-side gate driver circuit 11 is provided for each switching element 5. Thus, for a three-phase motor, three high-side gate driver circuits 11 are provided. Multiple gate drivers 11 may be provided in the same pre-driver IC 4. Each gate drivers 11 may be provided with respective control logic Do or may share the same control logic 10.

(38) The high-side gate-driver 11 can have one or more advantages.

(39) The high-side gate-driver 11 is less susceptible to variations in nMOS transistor parameters and ratings and so can be used with a wider variety of nMOS transistors. It can also be used with wider variety of switched loads. Through the variable current source 20, the slew rate can be programmed according to a particular application and can be adjusted according to load conditions taking into account, for example, as load impedance, battery voltage and driver transistor parameters. The high-side gate-driver 11 can be easily implemented in a pre-driver IC. Compared to known standard gate current controlled driver solutions the invention optimizes the non-overlapping timing in a bridge configuration and hence the power efficiency.

(40) It will be appreciated that many modifications may be made to the embodiments hereinbefore described.

(41) Other switching elements 6 capable of follower-type behaviour can be used, i.e. where an output node of the switching element 6 follows an input node of the switching element 6. For example, an IGBT may be used.

(42) A switch load may include a low-side, n-MOS transistor and the pre-driver IC 4 may include a low-side gate driver for the low-side n-MOS transistor.