ELECTRICAL CURRENT BASED TEMPERATURE SENSOR AND TEMPERATURE INFORMATION DIGITIZER

Abstract

The described technology is generally directed towards an electrical current based temperature sensor and temperature information digitizer, referred to herein as a “temperature digitizer”. The temperature digitizer can include a sensor core, a digital to analog converter, a current comparator, and a processor. The processor can be configured to perform multiple current comparisons using the sensor core, digital to analog converter, and current comparator, and the processor can generate a digital code that reflects the results of the multiple current comparisons. The digital code represents the temperature.

Claims

1. A temperature digitizer, comprising: a sensor core, wherein the sensor core is configured to generate a temperature dependent electrical current and at least one reference electrical current; a digital to analog converter, wherein the digital to analog converter is configured to generate a controlled electrical current which is combined with the at least one reference current to generate a modified reference current; a current comparator, wherein the current comparator is configured to perform a comparison of the modified reference current and the temperature dependent electrical current; and a processor, wherein the processor is configured to: record a binary result of the comparison performed by the current comparator; generate a current control output based on the binary result, wherein the current control output modifies the controlled electrical current generated by the digital to analog converter; repetitively record subsequent binary results and generate subsequent current control outputs to generate a digital code comprising a series of binary results; and output the digital code.

2. The temperature digitizer of claim 1, wherein the sensor core comprises a bipolar junction transistor.

3. The temperature digitizer of claim 1, wherein the sensor core is configured to generate two reference electrical currents, and wherein the two reference electrical currents comprise first-order temperature independent electrical current signals.

4. The temperature digitizer of claim 3, wherein the controlled electrical current is adjusted based on a first of the two reference electrical currents, and wherein the controlled electrical current is combined with a second of the two reference electrical currents to generate the modified reference current.

5. The temperature digitizer of claim 1, wherein the digital code comprises an at least eight bit digital code.

6. The temperature digitizer of claim 5, wherein the processor is further configured to repetitively generate subsequent digital codes and average the digital code and the subsequent digital codes to identify an at least eleven bit digital code, and wherein the digital code output by the processor comprises the eleven bit digital code.

7. The temperature digitizer of claim 1, wherein the current control output based on the binary result is calculated based on the binary result and a successive approximation algorithm.

8. The temperature digitizer of claim 1, wherein the processor comprises a successive approximation register logic unit.

9. The temperature digitizer of claim 1, wherein the digital to analog converter comprises an eight bit current steering digital to analog converter.

10. A method to generate digitized temperature data, comprising: generating a temperature dependent electrical current and at least one reference electrical current; generating a controlled electrical current which is combined with the at least one reference current to generate a modified reference current; performing a comparison of the modified reference current and the temperature dependent electrical current; recording a binary result of the comparison; generating a current control output based on the binary result, wherein the current control output modifies the controlled electrical current; repetitively recording subsequent binary results and generating subsequent current control outputs to generate a digital code comprising a series of binary results; and outputting the digital code.

11. The method to generate digitized temperature data of claim 10, wherein a bipolar junction transistor is used to generate the temperature dependent electrical current and the at least one reference electrical current.

12. The method to generate digitized temperature data of claim 10, wherein an eight bit current steering digital to analog converter is used to generate the controlled electrical current.

13. The method to generate digitized temperature data of claim 10, wherein a current comparator is used to perform the comparison of the modified reference current and the temperature dependent electrical current.

14. The method to generate digitized temperature data of claim 10, wherein a successive approximation register logic unit is used to record the binary result of the comparison, generate the current control output based on the binary result, repetitively record the subsequent binary results and generate the subsequent current control outputs, and output the digital code.

15. The method to generate digitized temperature data of claim 10, wherein the at least one reference electrical current comprises two reference electrical currents, wherein the controlled electrical current is combined with a second of the two reference electrical currents to generate the modified reference current.

16. The method to generate digitized temperature data of claim 15, wherein the two reference electrical currents comprise first-order temperature independent electrical current signals.

17. The method to generate digitized temperature data of claim 10, wherein the digital code comprises an at least eight bit digital code.

18. The method to generate digitized temperature data of claim 10, further comprising repetitively generating subsequent digital codes and averaging the digital code and the subsequent digital codes to identify an at least eleven bit digital code, and wherein the digital code output comprises the eleven bit digital code.

19. The method to generate digitized temperature data of claim 10, wherein generating the current control output based on the binary result comprises calculating the current control output based on the binary result and a successive approximation algorithm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Non-limiting embodiments of the subject disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified:

[0006] FIG. 1 illustrates an example temperature digitizer, in accordance with various embodiments of this disclosure;

[0007] FIG. 2 illustrates an example temperature digitizer method, in accordance with various embodiments of this disclosure;

[0008] FIG. 3 illustrates an example temperature dependent electrical current, in accordance with various embodiments of this disclosure;

[0009] FIG. 4 illustrates an example reference electrical current, in accordance with various embodiments of this disclosure;

[0010] FIG. 5 illustrates an example controlled electrical current, in accordance with various embodiments of this disclosure;

[0011] FIG. 6 illustrates an example temperature dependent electrical current and an example modified reference current, in accordance with various embodiments of this disclosure;

[0012] FIG. 7 illustrates multiple sequential modifications of a modified reference current and corresponding comparisons of a temperature dependent electrical current with the modified reference current, yielding multiple sequential binary results, in accordance with various embodiments of this disclosure;

[0013] FIG. 8 illustrates an example method performed by a logic component of a temperature digitizer, in accordance with various embodiments of this disclosure; and

[0014] FIG. 9 illustrates processing multiple digital codes to produce an output code, in accordance with various embodiments of this disclosure.

DETAILED DESCRIPTION

[0015] Aspects of the subject disclosure will now be described more fully hereinafter with reference to the accompanying drawings in which example embodiments are shown. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. However, the subject disclosure may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein.

[0016] One or more aspects of the technology described herein are generally directed towards an electrical current based temperature sensor and temperature information digitizer, referred to herein as a “temperature digitizer”, as well as methods of making and using the temperature digitizer. In some examples, temperature digitizers according to this disclosure can include a sensor core, a digital to analog converter, a current comparator, and a processor. The processor can be configured to perform multiple current comparisons using the sensor core, digital to analog converter, and current comparator, and the processor can generate a digital code that reflects the results of the multiple current comparisons. The digital code represents the temperature. Further aspects and embodiments are described in detail below.

[0017] FIG. 1 illustrates an example temperature digitizer 100, in accordance with various embodiments of this disclosure. The temperature digitizer 100 includes a sensor core 110, a current comparator 160, a digital to analog converter (DAC) 140, and a processor 150. Furthermore, the illustrated temperature digitizer 100 includes a current comparator interface 130 and a DAC interface 120. In some embodiments, the current comparator interface 130 and the DAC interface 120 can be included within the current comparator 160 and the DAC 140, respectively. A vertical dashed line down the middle of FIG. 1 generally divides an analog front-end portion of the temperature digitizer 100 from an analog to digital converter (ADC) portion of the temperature digitizer 100.

[0018] In an example embodiment, the sensor core 110 can comprise a bipolar core including a transistor, such as a bipolar junction transistor (BJT) or a metal-oxide-silicon (MOS) transistor. The DAC 140 can comprise an 8-bit current steering DAC. The processor 150 can comprise a successive approximation register (SAR) logic unit with an 8-bit connection to the DAC 140, as shown, and an 11-bit output by which processor 150 can output an output code 154, as shown. The processor 150 can be configured to conduct oversampling, e.g., 64x oversampling as will be described further herein.

[0019] The sensor core 110 can generate multiple output electrical currents, for example, the sensor core 110 can generate a temperature dependent current I.sub.PTAT 112, and one or more reference currents, such as I.sub.REF 114 and I.sub.REF_DAC_PRE PRE 116. In some embodiments, the two reference electrical currents I.sub.REF 114 and I.sub.REF_DAC_PRE 116 can comprise first-order temperature independent electrical current signals.

[0020] The temperature digitizer 100 can comprise wires or other electrical connectors which carry the illustrated electrical currents from their respective sources to their respective destinations. I.sub.PTAT 112 can originate at sensor core 110 and terminate at current comparator interface 130. I.sub.REF_DAC_PRE 116 can originate at sensor core 110 and terminate at DAC interface 120. I.sub.REF 114 can originate at sensor core 110 and terminate at a connection point which combines I.sub.REF 114 and I.sub.DAC 144, resulting in a modified reference current I.sub.MOD 146.

[0021] The DAC 140 can also generate electrical currents, for example, a current I.sub.REF_DAC 142 and a controlled electrical current I.sub.DAC 144. I.sub.REF_DAC 142 can originate at DAC 140 and terminate at DAC interface 120. Because the DAC interface 120 can be a part of the DAC 140, I.sub.REF_DAC 142 can optionally comprise an internally measurable current within the DAC 140. I.sub.REF_DAC 142 can be equal to, or otherwise proportional to, I.sub.REF_DAC_PRE 116.

[0022] The DAC 140 can be configured to generate the controlled electrical current I.sub.DAC 144 based on I.sub.REF_DAC 142 as well as based on a current control output 152 received from the processor 150. Thus the controlled electrical current I.sub.DAC 144 can be adjusted based on a first of the two reference electrical currents (I.sub.REF_DAC_PRE 116), and the controlled electrical current I.sub.DAC 144 can be combined with a second of the two reference electrical currents (I.sub.REF 114) to generate the modified reference current (I.sub.MOD 146).

[0023] The temperature digitizer 100 can comprise wires or other electrical connectors which carry the illustrated electrical currents from their respective sources to their respective destinations. I.sub.DAC 144 can originate at DAC 140 and terminate at the connection point which combines the reference current I.sub.REF 114 and the controlled current I.sub.DAC 144, and the combined I.sub.REF 114 and I.sub.DAC 144 is illustrated as the modified reference current I.sub.MOD 146. The modified reference current I.sub.MOD 146 can originate at the connection point for I.sub.REF 114 and I.sub.DAC 144, and I.sub.MOD 146 can terminate at the current comparator interface 130.

[0024] Currents I.sub.A 162 and I.sub.B 164 are generated inside the current comparator interface 130 and spilled at the current comparator 160 inputs. I.sub.A 162 and I.sub.B 164, respectively, can be equal to, or otherwise proportional to, temperature dependent current I.sub.PTAT 112 and modified reference current I.sub.MOD 146, respectively. The current comparator 160 can compare I.sub.A 162 and I.sub.B 164 in order to perform a comparison of the temperature dependent current I.sub.PTAT 112 and the modified reference current I.sub.MOD 146.

[0025] The current comparator 160 can generate a binary result 166 based on the comparison of the temperature dependent current I.sub.PTAT 112 and modified reference current I.sub.MOD 146. For example, if the temperature dependent current I.sub.PTAT 112 is larger than the modified reference current I.sub.MOD 146, the current comparator 160 can generate a 1 as the binary result 166. If the temperature dependent current I.sub.PTAT 112 is smaller than the modified reference current I.sub.MOD 146, the current comparator 160 can generate a 0 as the binary result 166. The binary result 166 can be provided to the processor 150.

[0026] The processor 150 can initially provide a current control output 152 to the DAC 140, wherein the current control output 152 controls or influences I.sub.DAC 144. After the initial current control output 152, the processor 150 can record a corresponding binary result 166. The processor 150 can then use the binary result 166 to determine a next current control output 152, e.g., the processor 150 can calculate the next current control output 152 based on the binary result 166 and a successive approximation algorithm. The processor 150 can provide the next current control output 152 to the DAC 140, to once again control or influence I.sub.DAC 144. The modified I.sub.DAC 144 leads to a different I.sub.MOD 146, which is compared to I.sub.PTAT 112 by the current comparator 160, leading to a next binary result 166. The processor 150 can record the next binary result 166 and repeat the process by calculating a subsequent current control output 152.

[0027] The processor 150 can repeat the process of recording a binary result 166 of the comparison performed by the current comparator 160, generating a current control output 152 based on the binary result 166, wherein the current control output 152 modifies the controlled electrical current I.sub.DAC 144 generated by the DAC 140, and repetitively recording subsequent binary results 166 and generating subsequent current control outputs 152, as many times as needed to generate a digital code comprising a series of binary results 166, e.g., the processor 150 can be configured to repeat the process eight times to record an 8 bit digital code comprising 8 sequential binary results 166.

[0028] In some embodiments, the processor 150 can be configured to output the digital code, e.g., the 8-bit digital code, as output code 154. In other embodiments, the processor 150 can be configured to repetitively generate subsequent digital codes, and average the digital code and the subsequent digital codes to identify a higher resolution digital code, e.g., an at least 11 bit digital code. The processor 150 can then output the higher resolution digital output code, as output code 154.

[0029] For example, the processor 150 can be configured to record 64 digital codes (e.g., 64 8-bit digital codes) as inputs, and the processor 150 can be configured to then use the 64 digital codes to calculate each output code 154. The processor 150 can process the multiple recorded digital codes, e.g., by performing an averaging operation, in order to calculate the output code 154, e.g., the 11 bit output code 154.

[0030] With regard to FIG. 1 in general, embodiments of the illustrated temperature digitizer 100 can be widely applied in various measurement, instrumentation, and control systems. Fabricating a temperature sensor in integrated circuit (IC) technology, according to FIG. 1, is well suited for the volume production of low-cost products. Temperature sensors fabricated in IC technology can be combined with interface electronics on a single chip. Such ‘smart’ sensors have distinct advantages compared to conventional sensors: they can directly communicate with a microcomputer in a standardized digital format, thus reducing the complexity and increasing the modularity of the system in which they are applied.

[0031] Smart temperature sensors are typically limited in accuracy because of two main reasons. To keep production costs low, smart temperature sensors are often produced in standard complementary metal-oxide-semiconductor (CMOS) technology, which has been developed for mainstream digital products, not precision analog products. In addition, to keep production costs low, their temperature error is typically measured (calibrated) and corrected at not more than one temperature. Embodiments according to FIG. 1 can address these limitations.

[0032] In an aspect, circuits according to FIG. 1 can be designed to operate substantially in current mode. This promotes simplicity in summing and scaling signals in the current domain, giving rise to an advantage in terms of occupied silicon area; in fact, this approach allows to spare several adding and amplifying circuits inherently required in a voltage domain alternative. In addition, the signals of interest are processed by a lower number of blocks, and so the sources of error that contribute to the outputs are reduced. With a lower amount of contamination of the signals of interest, it is simpler to achieve a higher level of accuracy.

[0033] In embodiments wherein sensor core 110 is a BJT, the sensor core 110 can generate the currents needed to properly feed the ADC (on the right side of FIG. 1). This includes a proportional to absolute temperature (PTAT) current 112, which can be an input of the ADC, and two replicas of a first-order temperature independent current 114, 116 which can be used as references to perform the conversion. A single point current-mode trimming circuit can be used to generate the currents 114, 116, to improve the system accuracy level with the goal to achieve minimum nonlinearity of the sensor output characteristic and to keep the global current consumption as low as possible.

[0034] The ADC (on the right side of FIG. 1) can be based on a SAR architecture and can comprise a current steering DAC 140, a current comparator 160, and processor 150, such as a SAR logic block, as described above. The current steering DAC 140, whose reference signal can be a properly scaled version of the reference current via the DAC interface 120, drives the current comparator interface 130 by means of a current signal I.sub.DAC 144 which is controlled by the processor 150. The current comparator 160 can periodically provide a decision (binary result 166) that rules the behavior of the processor 150 which executes the successive-approximation algorithm. The three blocks included in the ADC can handle 8 bits and thus a single conversion cycle can provide as output an 8 bit digital word, also referred to herein as a digital code. To refine the resolution, oversampling can be used in order to achieve an 11 bit code, by averaging the 8 bit codes of 64 conversions.

[0035] FIG. 2 illustrates an example temperature digitizer method, in accordance with various embodiments of this disclosure. For simplicity of explanation, the illustrated method is depicted and described as a series of acts. It is to be understood and appreciated that various embodiments disclosed herein need not be limited by the acts illustrated and/or by the order of acts. For example, acts can occur in various orders and/or concurrently, and with other acts not presented or described herein. Furthermore, not all illustrated acts may be required to implement methodologies in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the methods illustrated herein could alternatively be represented as a series of interrelated states via a state diagram or events.

[0036] Operations 202 and 204 can be performed by the sensor core 110 illustrated in FIG. 1. At 202, the sensor core 110 can generate a temperature dependent electrical current, e.g., I.sub.PTAT 112. At 204, the sensor core 110 can generate at least one reference electrical current, such as I.sub.REF 114 and I.sub.REF_DAC_PRE 116.

[0037] The remaining operations 206-216 can be performed by the processor 150, DAC 140, and current comparator 160 and their respective interfaces illustrated in FIG. 1. In general, multiple digital codes can be generated by multiple repetitions of operations 206-214, and after the multiple digital codes are generated, the multiple digital codes can be used to calculate and provide an output code at operation 216.

[0038] At 206, the DAC 140 can generate a controlled electrical current I.sub.DAC 144. At 208, the controlled electrical current I.sub.DAC 144 can be combined with the at least one reference current I.sub.REF 114 to generate a modified reference current I.sub.MOD 146.

[0039] At 210, the current comparator 160 can perform a comparison of the modified reference current I.sub.MOD 146 and the temperature dependent electrical current I.sub.PTAT 112. The current comparator 160 can output a binary result 166 to the processor 150.

[0040] At 212, the processor 150 can record a binary result 166 of the comparison performed at operation 210. At 214, the processor 150 can generate a current control output 152 based on the binary result 166 and a successive approximation algorithm, discussed further in connection with FIG. 7. The current control output 152 can modify the controlled electrical current 144. Operations 206-214 can be repeated in a loop, as indicated by the arrow from box 214 back to box 206, in order to repetitively record subsequent binary results 166 and generate subsequent current control outputs 152 to generate a digital code comprising a series of binary results 166.

[0041] After the digital code is generated, at 216, the processor 150 can optionally provide the digital code as the output code 154, wherein the output code 154 can be provided to any component that is coupled with the temperature digitizer 100 via the interface illustrated in FIG. 1 (illustrated as an 11 bit output code interface). Alternatively, the processor 150 can cause operations 206-214 to be repeated still further in order to repetitively generate subsequent digital codes, and, at 216, the processor 150 can average the digital code and the subsequent digital codes (or otherwise process the digital codes) to identify an enhanced digital code, e.g., an at least eleven bit digital code. The processor 150 can output the enhanced digital code as the output code 154.

[0042] With regard to FIG. 2 in general, in some embodiments, methods according to this disclosure can include generating a temperature dependent current-domain signal and two replicas of a first-order temperature independent current signal (references) by means of a BJT-based circuit.

[0043] Methods can furthermore include, during a single conversion repetition: in response to a digital output, comparing the temperature dependent current-varying signal with one of the two references plus the other reference scaled by a factor depending on a successive-approximation algorithm. This step can be iterated multiple times, e.g., 8 times to get an 8 bit digital word.

[0044] Furthermore, methods can repeat the conversion repetition, e.g., 64 times, storing the resulting 64 8 bit digital words which differ from each other due to the presence of noise. Finally, methods can include computing the average of the 64 samples, thereby resolving 3 additional bits. The resulting 11 bit digital code is proportional to the temperature dependent current-domain signal.

[0045] FIG. 3 illustrates an example temperature dependent electrical current, in accordance with various embodiments of this disclosure. FIG. 3 is a graph showing the temperature dependent electrical current I.sub.PTAT, in micro amps (μA) at different temperatures ranging from −60° Celsius (C) to 150° C. As can be seen, a sensor core 110 can output different temperature dependent electrical currents at different temperatures.

[0046] FIG. 4 illustrates an example reference electrical current, in accordance with various embodiments of this disclosure. FIG. 4 is a graph showing a reference electrical current I.sub.REF, in μA at different temperatures ranging from −60° C. to 150° C. The illustrated I.sub.REF can represent currents I.sub.REF 114 and/or I.sub.REF_DAC_PRE 116 introduced in FIG. 1. I.sub.REF can be considered as a first-order temperature independent electrical current signal, which can display a small positive linear temperature dependence, which results in a non-linearity that can be turned to compensate for the second-order non-linearity originated from the curvature of the voltage that falls between the base and emitter (VBE) of a transistor within the sensor core 110.

[0047] FIG. 5 illustrates an example controlled electrical current, in accordance with various embodiments of this disclosure. FIG. 5 is a graph showing the controlled electrical current I.sub.DAC, in μA at different temperatures ranging from −60° C. to 150° C. FIG. 5 shows a controlled electrical current I.sub.DAC which can be generated based on one current control output 152, understanding that different current control outputs 152 can be used to change I.sub.DAC, however, the slope and linearity of I.sub.DAC will be similar at different current magnitudes.

[0048] FIG. 6 illustrates an example temperature dependent electrical current and an example modified reference current, in accordance with various embodiments of this disclosure. FIG. 6 is a graph showing the temperature dependent electrical current I.sub.PTAT, in μA at different temperatures ranging from −60° C. to 150° C., as introduced in FIG. 3, along with a modified reference current I.sub.MOD also in μA at temperatures ranging from −60° C. to 150° C. I.sub.MOD can comprise a combination of I.sub.DAC (FIG. 5) and I.sub.REF (FIG. 4), as described herein. As such, I.sub.MOD, like I.sub.DAC, can have different values (effectively moving I.sub.MOD up or down on the vertical axis) at a given temperature depending on the current control output 152. As can be observed in FIG. 6, I.sub.PTAT can be compared with I.sub.MOD at a given temperature, e.g., by current comparator 160. Current comparator 160 can generate a first binary result 166 if I.sub.PTAT is larger than I.sub.MOD, or a second (opposite) binary result 166 if I.sub.PTAT is smaller than I.sub.MOD.

[0049] FIG. 7 illustrates multiple sequential modifications of a modified reference current and corresponding comparisons of a temperature dependent electrical current with the modified reference current, yielding multiple sequential binary results, in accordance with various embodiments of this disclosure. FIG. 7 is a graph showing an example modified reference current (I.sub.MOD) and an example temperature dependent electrical current (I.sub.PTAT) over time, where time is represented on the horizontal axis. FIG. 7 presumes a constant temperature throughout multiple operations that modify I.sub.MOD, therefore, I.sub.PTAT is illustrated as a straight horizontal line, while I.sub.MOD changes over time in response to different control inputs.

[0050] As can be understood by reference to FIG. 7, processor 150 can use a successive approximation algorithm to set a first current control output 152, resulting in a first I.sub.MOD current (at the left side of FIG. 7). The illustrated first I.sub.MOD current is represented as ½. The current comparator 160 can then compare the first I.sub.MOD current with I.sub.PTAT. In this example, the I.sub.PTAT is less than the first I.sub.MOD, and so a first binary result 166 of the comparison can be a 0, as illustrated in FIG. 7 underneath the graphed currents. If I.sub.PTAT had been more than first I.sub.MOD, the first binary result 166 of the comparison could instead be a 1. In this example, the processor 150 can store the binary result (0) in the first bit position (Bit 0).

[0051] Next, the processor 150 can use the successive approximation algorithm to set a second current control output 152, resulting in a second I.sub.MOD current. The successive approximation algorithm can cause the processor 150 to adjust I.sub.MOD one half step down when the previous binary result indicated that I.sub.PTAT was less than the first I.sub.MOD (as in this example). In an opposite example, the successive approximation algorithm can cause the processor 150 to adjust I.sub.MOD one half step up when a previous binary result (1) indicated that I.sub.PTAT was more than first I.sub.MOD. Returning to the illustrated example, the successive approximation algorithm can cause the processor 150 to adjust I.sub.MOD one half step down, namely, to ¼. Second I.sub.MOD current is therefore represented in FIG. 7 as ¼, which is one half step down from the previous I.sub.MOD value of ½. The current comparator 160 can then compare the second I.sub.MOD current with I.sub.PTAT. In this example, the I.sub.PTAT is more than the second I.sub.MOD, and so a second binary result 166 of the comparison can be a 1. Again, other values can be arrived at in other examples. In this example, the processor 150 can store the second binary result in the second bit position (Bit 1).

[0052] Next, the processor 150 can use the successive approximation algorithm to set a third current control output 152, resulting in a third I.sub.MOD current. The successive approximation algorithm can cause the processor 150 to adjust I.sub.MOD one half step up this time, because when the previous binary result indicated that I.sub.PTAT was more than second I.sub.MOD. The successive approximation algorithm can cause the processor 150 to adjust I.sub.MOD one half step up, namely, to ⅜. The third I.sub.MOD current is therefore represented in FIG. 7 as ⅜, which is which is one half step up from the previous I.sub.MOD value of ¼. Note that the half step is half of the previous step, so successive half steps are smaller with each repetition. The current comparator 160 can then compare the third I.sub.MOD current with I.sub.PTAT. In this example, the I.sub.PTAT is more than third I.sub.MOD, and so a third binary result 166 of the comparison can be a 1. Again, other values can be arrived at in other examples. In this example, the processor 150 can store the third binary result in the third bit position (Bit 2).

[0053] The above procedure can be repeated until all 8 bits are determined. In general, the successive approximation algorithm can effect an adjustment of the modified reference current I.sub.MOD, wherein the adjustment moves I.sub.MOD in the direction of I.sub.PTAT, and wherein the magnitude of the adjustment is a fraction (such as one half, or any other fraction) of a previous adjustment. In this manner, I.sub.MOD becomes successively closer to I.sub.PTAT with each adjustment. As a result, the digital code (in this example, 01101011) is representative of I.sub.PTAT, which is representative of the temperature.

[0054] FIG. 8 illustrates an example method performed by a logic component of a temperature digitizer, in accordance with various embodiments of this disclosure. For simplicity of explanation, the illustrated method is depicted and described as a series of acts. It is to be understood and appreciated that various embodiments disclosed herein need not be limited by the acts illustrated and/or by the order of acts. For example, acts can occur in various orders and/or concurrently, and with other acts not presented or described herein. Furthermore, not all illustrated acts may be required to implement methodologies in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the methods illustrated herein could alternatively be represented as a series of interrelated states via a state diagram or events.

[0055] The operations illustrated in FIG. 8 can be performed, e.g., by the processor 150 illustrated in FIG. 1. AT 800, the processor 150 can initiate a temperature measurement operation. At 802, the processor 150 can use a successive approximation algorithm, such as described in connection with FIG. 7, to generate a current control output 152. The first current control output 152 results in a first I.sub.MOD, which is compared with I.sub.PTAT, resulting in a binary result 166. At 804, the processor 150 can record the binary result 166. At 806, the processor 150 can determine if recording of binary results is done, e.g., if all 8 bits of a digital code have been recorded, or in some embodiments, if all of the bits for multiple digital codes (e.g., 64 digital codes) have been recorded.

[0056] If not done at 806, then the processor 150 returns to operation 802 and uses the successive approximation algorithm to generate a next current control output 152 based on the previous binary result 166. The processor 150 can then repeat operation 804 to record the next binary result 166, followed by operation 806. The processor 150 can repeat operations 802-806 as needed until the processor 150 determines that it is done (all bits are recorded) at operation 806.

[0057] If done at 806, then at 808 the processor 150 can calculate/provide an output code 154. In embodiments wherein the processor 150 generates a single digital code, the processor 150 can output the single digital code as the output code 154 without further processing. In embodiments wherein the processor 150 generates multiple digital codes, the processor 150 can combine the multiple digital codes to determine an enhanced accuracy digital code (e.g., an eleven bit digital code can be calculated from 64 eight bit digital codes), and the processor 150 can output the enhanced accuracy digital code as the output code 154. The processor 150 can end at 810, the temperature digitization is complete. Further temperature digitization operations can be performed by re-starting operations at 800.

[0058] FIG. 9 illustrates processing multiple digital codes to produce an output code, in accordance with various embodiments of this disclosure. Digital codes 910 including code 1, code 2, code 3, code 4 . . . code 64 can be recorded by the processor 150. Each of the digital codes 910 can comprise, e.g., an 8 bit code generate by 8 current comparison operations, as described herein. The digital codes 910 can be processed by a calculate/provide output code block 808, introduced in FIG. 8. A variety of different processing approaches can be used at 808. Some embodiments can use averaging operations to determine an enhanced accuracy average of the digital codes 910. The resulting enhanced accuracy average can comprise a digital code having more bits than the input digital codes 910, e.g., 11 bits. The enhanced accuracy digital code can be output as output code 920.

[0059] As employed in the subject specification, the term “component” refers to substantially any analog and/or digital based device(s), circuit(s), etc. comprising, e.g., a resistor, a capacitor, a transistor, a diode, an inductor, a memory, a programmable device, e.g., fuse, field programmable gate array (FPGA), complex programmable logic device (CPLD), etc. relevant to performing operations and/or functions of circuit(s), device(s), system(s), etc. disclosed herein. Further, the terms “processing component”, “control unit component”, “control unit”, and “arithmetic logic unit (ALU)” can refer to substantially any computing processing unit or device (e.g., MAC, etc.), comprising, but not limited to comprising, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an ASIC, a digital signal processor (DSP), an FPGA, a programmable logic controller (PLC), a CPLD, a discrete gate or transistor logic, discrete hardware components, an analog circuit, or any combination thereof designed to perform the functions and/or processes described herein. Further, a processor can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, e.g., in order to optimize space usage or enhance performance of mobile devices. A processor can also be implemented as a combination of computing processing units, devices, etc.

[0060] In the subject specification, the term “memory”, “memory component”, “lookup table (LUT)” and substantially any other information storage component relevant to operation and functionality of the devices disclosed herein refer to “memory components,” or entities embodied in a “memory,” or components comprising the memory. It will be appreciated that the memory can include volatile memory and/or nonvolatile memory. By way of illustration, and not limitation, volatile memory, can include random access memory (RAM), which can act as external cache memory. By way of illustration and not limitation, RAM can include synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct Rambus dynamic RAM (DRDRAM), and/or Rambus dynamic RAM (RDRAM). In other embodiment(s) nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Additionally, the components and/or devices disclosed herein can comprise, without being limited to comprising, these and any other suitable types of memory.

[0061] Reference throughout this specification to “one embodiment,” or “an embodiment,” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment,” or “in an embodiment,” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0062] Furthermore, to the extent that the terms “includes,” “has,” “contains,” and other similar words are used in either the detailed description or the appended claims, such terms are intended to be inclusive—in a manner similar to the term “comprising” as an open transition word—without precluding any additional or other elements. Moreover, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form.

[0063] Aspects of systems, apparatus, devices, processes, and process blocks explained herein can be embodied within hardware, such as an ASIC or the like. Moreover, the order in which some or all of the process blocks appear in each process should not be deemed limiting. Rather, it should be understood by a person of ordinary skill in the art having the benefit of the instant disclosure that some of the process blocks can be executed in a variety of orders not illustrated.

[0064] Furthermore, the word “exemplary” and/or “demonstrative” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art having the benefit of the instant disclosure.

[0065] The above description of illustrated embodiments of the subject disclosure is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as those skilled in the relevant art can recognize.

[0066] In this regard, while the disclosed subject matter has been described in connection with various embodiments and corresponding Figures, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.