Method for electrically interconnecting at least two substrates and multichip module

Abstract

A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

Claims

1. A method for electrically interconnecting at least two substrates, each having corresponding sets of electrical contacts, at least one of the substrates having a set of electrical contacts formed of a deformable metal, comprising: aligning respective sets of electrical contacts of the first and a second substrates immersed in a curable liquid adhesive; and compressing the corresponding sets of electrical contacts while curing the curable liquid adhesive to form a solid matrix, to: exclude the curable liquid adhesive from an intercontact zone; deform the set of electrical contacts formed of the deformable metal; and generate a prestress to maintain a compressive force between the respective sets of electrical contacts of the at least two substrates; the formed solid matrix maintaining adhesion and mechanical integrity over at least an entire range of temperatures between about +50 C to 175 C, wherein the at least two of the substrates each having the set of electrical contacts are connected or bonded together without heating to a reflow temperature of the deformable metal.

2. The method according to claim 1, further comprising maintaining the curable liquid adhesive below a temperature of about 100 C during curing to form the solid matrix.

3. The method according to claim 1, wherein the curable liquid adhesive comprises an epoxy adhesive that shrinks during curing, and has a positive coefficient of thermal expansion when cured to form the solid matrix, the at least two substrates have substantially matched coefficients of thermal expansion, and the solid matrix has a substantially mismatched coefficient of thermal expansion with respect to the at least two substrates.

4. The method according to claim 1, wherein said compressing comprises imposing a pressure of between about 5-100 gm per contact pair.

5. The method according to claim 1, wherein the solid matrix maintains mutual compression and electrical conductivity between the corresponding sets of electrical contacts at a temperature of less than about 10K.

6. A method of forming a multichip module, comprising a first substrate having a first set of contacts in a first contact pattern, the first set of contacts being formed of a metal which is deformable under a contact pressure, and a second substrate having a second set of contacts in a second contact pattern, the second contact pattern corresponding to the first contact pattern, the method comprising: compressing the first set of contacts against the second set of contacts, under the contact pressure, to deform the first set of contacts substantially without fusion of the first set of contacts and the second set of contacts, and forming interconnected electrical circuits between the first substrate and the second substrate; and curing of a liquid adhesive, subject to shrinkage during curing to generate a tensile prestress, around the first set of contacts compressed against the second set of contacts, to form a cryogenically stable solid matrix surrounding the first set of contacts and the second set of contacts, which maintains a compressive force between the first set of contacts and the second set of contacts bonded together substantially without heating to the reflow temperature of the metal which is deformable.

7. The method according to claim 6, wherein said cryogenically stable solid matrix maintains adhesion and mechanical integrity over at least a range of temperatures between about +50 C to 175 C.

8. The method according to claim 6, wherein the liquid adhesive comprises an epoxy adhesive which shrinks during curing, and has a positive coefficient of thermal expansion when cured, the first and second substrates have matched coefficients of thermal expansion, and the cured adhesive has a substantially mismatched coefficient of thermal expansion with respect to the first and second substrates.

9. The method according to claim 6, wherein the contact pressure comprises a pressure of between about 5-100 gm per contact pair.

10. The method module according to claim 6, wherein at least one of the first substrate and the second substrate comprises at least one Josephson junction.

11. The method according to claim 10, wherein the at least one Josephson junction operates as an element within at least one rapid single flux quantum gate.

12. The method according to claim 6, wherein the cryogenically stable solid matrix has a positive coefficient of thermal expansion, and the liquid adhesive has a viscosity at 20 C of less than about 1000 cp.

13. A method of forming a multichip module, comprising: providing a first substrate having a first set of metal contacts, and a second substrate having a second set of metal contacts; deforming the second set of metal contacts under compression with the first set of metal contacts, to form an unfused electrical interconnection between the first set of metal contacts and the second set of metal contacts; and curing a liquid to form a polymer matrix which is mechanically stable at 9 K, surrounding the first and second set of contacts, having a tensile prestress generated during curing to maintain a compressive force between the first set of contacts and the second set of contacts over a temperature range comprising at least +50 C to 175 C, substantially without heating to a reflow temperature the first set of metal contacts and the second set of metal contacts bonded together.

14. The method according to claim 13, wherein the liquid comprises a curable epoxy adhesive which shrinks during curing, and has a positive coefficient of thermal expansion when cured, wherein the first and second substrates have matched coefficients of thermal expansion, and the cured adhesive has a substantially mismatched coefficient of thermal expansion with respect to the first and second substrates.

15. The method according to claim 13, wherein the second set of metal contacts are deformed under a contact pressure of between about 5-100 gm per contact pair.

16. The method according to claim 13, wherein at least one of the first substrate and the second substrate comprises at least one Josephson junction which operates as a switching element of at least one rapid single flux quantum gate.

17. The method according to claim 13, wherein the polymer matrix has a positive coefficient of thermal expansion, and the liquid has, prior to curing, a viscosity at 20 C of less than about 1000 cp.

18. The method according to claim 14, wherein the polymer matrix is substantially unfilled.

19. The method according to claim 14, wherein the second set of metal contacts are plastically deformed.

20. The method according to claim 14, wherein the polymer matrix maintains mutual compression and electrical conductivity between the first set of metal contacts and the second set of metal contacts at a temperature of less than about 10K.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A shows an exemplary substrate wafer in accordance with the present invention, showing the pads for connection to the chip inside the bonding pads for external connection;

(2) FIG. 1B shows an exemplary chip to be bonded to the wafer of FIG. 1A, showing the pads for connection to the substrate wafer;

(3) FIGS. 2A, 2B and 2C show, a top view of an exemplary contact pattern of a wafer chip, a side view of the wafer chip and a carrier in position for attachment, and a side view of the bonded wafer chip and carrier, respectively;

(4) FIG. 2D shows the carrier contacts immersed in liquid adhesive before bonding to the wafer;

(5) FIG. 2E shows the bonded result, in which the wafer and carrier contacts are compressed to achieve electrical continuity, surrounded by solidified adhesive; and

(6) FIG. 3 shows an exemplary multichip module which may be implemented according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Comparative Example

(7) Single-chip modules (SCMs) consisting of 5-mm5-mm chips bonded to 1-cm1-cm silicon carriers with SnIn eutectic solder, using a well-practiced solder-reflow die-attach method. K. E. Yokoyama, G. Akerling, A. D. Smith, and M. Wire, Robust superconducting die attach process, IEEE Trans. Appl. Supercond., vol. 7, pp. 2631-2634 (June 1997) (Yokoyama). Very impressive high-speed data were obtained with these samples. After several thermal cycles, the contact pads were cleaned of an SCM carrier by immersing it in acetone and placing it in an ultrasonic bath. The chip immediately detached from its carrier. Solder was still attached on both the chip and carrier pads. Likewise, using an ultrasonic probe to excite sound waves in another carrier lead to similar results: the chip detached. Therefore, while reflow soldering techniques for fabricating MCM's generally yield acceptable electrical performance, their mechanical performance is inferior.

(8) The 5 mm.sup.2 test chip fabricated with HYPRES' (Elmsford, N.Y.) 1-kA/cm.sup.2 process (D. Yohannes, S. Sarwana, S. K. Tolpygo, A. Sahu, Y. A. Polyakov, and V. K. Semenov, Characterization of HYPRES' 4.5 kA/cm.sup.2 & 8 kA/cm.sup.2Nb/AlOx/Nb fabrication processes, IEEE Trans. Appl. Supercond., vol. 15, pp. 90-93, June 2005.) and having InSn bumps formed by dipping the chip in a molten solder bath, was placed over, and aligned with corresponding contacts on a 1 cm.sup.2 carrier, and the aligned structure heated to a reflow temperature. Each transmitter launches a pulse train onto a 1.6- PTL (passive transmission line), off chip through a bump, back on chip through another bump.

Example

(9) Experimental results for chip-to-chip data communications on a superconducting Multi-Chip-Module (MCM) using a novel fabrication technique are provided. The MCM was produced using a non-conductive adhesive to bond a 5-mm5-mm test chip to a 1-cm1-cm carrier. The module demonstrated superior mechanical stability and protection from its environment during thermal cycling. The MCM also retained its electrical properties after multiple thermal cycling from room temperature to 4 K. The superconducting circuitry successfully passed single-flux quanta at rates exceeding 50 Gbps, with error rates lower than 510.sup.14 at 36 Gbps using 100-micrometer diameter InSn solder bumps, and lower than 610.sup.14 at 57 Gbps using 30-micrometer-diameter solder bumps. Although this was demonstrated with a single chip, passing the signal off the chip to the carrier and back again is equivalent to communication between two chips on a larger carrier. The extension to more than two chips is also evident.

(10) One embodiment of the invention is intended to improve system assembly time and yield by culling known good die and permanently bonding them to the carrier. Accordingly, chips must first be tested on a test carrier, chips must be demounted from the test carrier and remounted on the MCM system carrier, and the adhesive used for initial chip testing must provide a strong bond while enabling rework.

(11) The solder bumps were produced by dunking a carrier into a bath of liquid solder, as shown in FIGS. 2B and 2D. K. E. Yokoyama, G. Akerling, A. D. Smith, and M. Wire, Robust superconducting die attach process, IEEE Trans. Appl. Supercond., vol. 7, pp. 2631-2634, June 1997. Other techniques may be used, and thus it is not necessary to raise the chip to reflow temperatures in all embodiments. The chips were then aligned and bonded to the substrate using a Karl Suss model 150 chip bonder. A drop of adhesive was applied to the substrate just before assembly, and thus the drop remained uncured during compression of the contacts. The bumps easily pushed through the adhesive to make excellent electrical contact. After curing, epoxy shrinkage resulted in reliable electrical connection and mechanical stability. Many kinds of bumps can be used with this technique, including solder, gold studs, and polymers.

(12) Solder bump heights were measured with a Veeco model NT1100 profilometer. Several fluxes were tried, but the technique frequently yielded bump height variations of as much as 50% for 5 m high bumps, thereby reducing yield. Modules produced with gold stud bumps provided by Palomar Technologies produced superior bump uniformity (1 m 1), and excellent electrical contact.

(13) The adhesive, shown in FIGS. 2B, 2C, 2D, and 2E, may be a temporary or permanent type. Permanent type adhesives could not be disassembled even after weeks of soaking in solvents and hours of immersion in an ultrasonic bath, while temporary adhesive bonds were readily severed using an ultrasonic bath or probe.

(14) Thermal cycling experiments were conducted for these modules in which the SCM was cycled between 4K and room temperature more than 10 times without any mechanical or electrical failure. These experiments were deliberately carried out on under harsh conditions, in which the SCM was subject to moisture condensation and quick changes in temperature.

(15) The re-workable adhesive method does not result in perfect yields subsequent to the first bonding, due to difficulty in removing adhesive residues. Some chips could, however, be rebonded.

(16) A preferred permanent non-conductive adhesive is Tra-Bond 2115, which has a relatively low viscosity of 250 cp. Tra-Bond 2151, with a viscosity of 40,000 cp, on the other hand, was too viscous, and it was difficult to squeeze out the adhesive sufficiently to get good electrical contact. The 2115 lacks filler, whereas the 2151 has added alumina and silica filler, which increases the viscosity and also the thermal conductivity. The process requires that a pressure be applied between the wafer and substrate to displace liquid adhesive from the contact region, to provide metal-to-metal contact, and further that the contacts be deformed to provide a large contact area per contact as shown in FIGS. 2D and 2E, and to ensure that statistical variations in contact height do not result in open circuits. However, the amount of pressure that may be applied is limited by the fragility of the wafer and substrate, with too high a pressure potentially leading to fracture. Too little pressure would lead to open circuits. It is noted that the adhesive itself redistributes forces, in a manner somewhat related to the viscosity of the uncured adhesive. A higher viscosity or highly filled liquid will tend to have a greater force redistribution, and therefore a highly viscous liquid may prevent reliable electrical connections from being formed. Likewise, higher viscosity adhesives may persist in the region between the respective contact pairs, leading to formation of an insulating film between them and an open circuit or high impedance path. Depending on the filler composition and characteristics, filler particles may also present a barrier to prevent good contact. Therefore, according to one embodiment of the invention, the adhesive has a relatively low filler concentration and is substantially formed of polymeric substances.

(17) As the preferred adhesives cure, small amount of shrinkage occurs. If the adhesive has a larger positive coefficient of thermal expansion than the wafer and substrate materials, then if the structures are heated during curing, and/or operated at reduced temperatures, a prestress will be imparted to the adhesive. Each of these advantageously increases the force placed between the respective pairs of electrical contacts, and therefore tend to maintain good electrical contact.

(18) In order to accelerate curing of the epoxy, it may be heated. Without heating, curing takes about 24 hours at room temperature. Heating to 60 C in the alignment fixture permits effective curing to be achieved in about 2 hours. This heating also decreases the viscosity of the epoxy even further, enabling more effectively elimination of epoxy from between the electrical contacts, assuring absence of an insulating layer.

(19) The top passivating layer for both the chip and the substrate carrier is generally amorphous SiO.sub.2. The epoxy needs to wet this layer effectively, and thus the epoxy may be specially selected for this characteristic. Likewise, since it is not intended to maintain a layer between the metallic contacts, the epoxy may be selected to have a low wettability for the metal contacts, especially when compressed during curing.

(20) In the case of a removable adhesive, for example to permit rework or to test wafers before final assembly, various materials may be used to weaken or degrade the epoxy. The preferred method for removing a frangible epoxy is ACF-X remover (Anisotropic Conductive Film), available from Ito America Inc., www.itousa.com, which is also used for flip chip applications. It is also based on epoxy-like polymers. ACF-X causes epoxy to crack so that it can be removed mechanically. This chemical worked on some other epoxies but not on Tra-Bond 2115, which provides a permanent bond.

(21) When using the Tra-Bond 2115 epoxy, a 2 kg force was used for chips with InSn bumps. There are 200 bumps, thus a pressure of about 10 grams per bump was applied. With gold studs, a force of 60 grams per contact was employed.

(22) The process for forming the MCM is shown in FIGS. 2A-2C. An array of metallic bumps are first created on the chip contacts. (These bumps can be prepared by prior art methods including InSn solder dipping and gold stud bonding.) Then, the chip carrier, shown in FIG. 1A, is coated with a nonconductive adhesive (with relatively low viscosity), the chip, shown in FIG. 1B, is carefully aligned with the carrier, and the two are carefully pressed together in a way that squeezes the glue out of the contact regions and compresses the bumps, without stressing or breaking the chip. The assembly may be heated slightly to cure the adhesive, but there is no need to melt the solder. The result is a package that is strongly bonded in the non-contacting regions, and held by compression in the contacts.

(23) The adhesive is specially chosen for these purposes. The final connections must be clean metallic contacts, with very low contact resistance. Any significant insulating residue on the contacts would degrade the signal propagation. Further, the adhesive must be compatible with repeated cycling down between room temperature and cryogenic temperatures without cracking or affecting the contact resistance.

(24) An SFQ racetrack similar to that described in Y. Hashimoto, S. Yorozu, and T. Miyazaki, Transmission of single flux quantum between superconductor chips, Appl. Phys. Lett., vol. 86, pp. 072502-1-072502-3 (February 2005), was employed to test the performance of the adhesive bonded multichip module. With this technique, one monitors the average voltage while a definite number of flux quanta circumnavigates a loop. This is an excellent method of determining the maximum sustainable data rate in circuits with PTLs and chip-to-chip (C2C) bump connections. A test chip was designed using a target critical current density of 4.5 kA/cm.sup.2, and increased the DFQ matching resistor and PTL impedance to 3. The SCMs were assembled with adhesive mechanical bonds.

(25) The racetrack experiment enables a specific number of flux quanta to enter the loop, and to remain circulating while the switch is on. The racetrack speed can be varied by changing the bias of a variable delay line (VDL), which contains a 70-junction Josephson transmission line (JTL). The average voltage is n.sub.0/t, where t is the sum of the circuit delay (mostly in the VDL), and the time to pass through the PTL and bump transitions.

(26) The circuit was simulated, and estimated as approximately 340 ps, or 6.1 V/.sub.0 at nominal bias. While the switch is off, there is no observed change in the average voltage. When the switch is turned on, a ramped input voltage is applied to a DC/SFQ converter. As each flux quantum is popped into the loop, the average voltage increases by approximately 6 V, as expected. (The voltage to be measured is amplified by an Ithaco Model 1201 low noise preamplifier, Ithaco, Inc. PO Box 6437, Ithaca N.Y. 14851-6437.)

(27) Further increases in the number of flux quanta eventually results in a marked decrease in the step height, indicating a significant increase in the bit error rate (BER). For the adhesive bonded multichip module, the linearity holds up to 90 V, corresponding to a data rate of approximately 43 Gbps.

(28) A quantitative estimate of the bit error rate can be obtained by observing how long the average voltage stays on the same voltage step. A voltage of 72 V could be sustained for more than 10 minutes, indicating that the BER is less than 510.sup.14 at a data rate of 36 Gbps.

(29) Initial results for an experiment using 30 m solder bumps with signal bumps spaced 80 m apart and five nearest-neighbor ground bumps show for n=20.sub.0 the maximum sustainable voltage was 119 V, corresponding to a maximum data rate of 57.5 Gbps. The measured BER was less than 610.sup.14 at this data rate.

(30) To increase data rates, bump geometries with more closely spaced 30 m bumps may be used, for example. The chip-immersion bump-deposition technique often results in unacceptable bump-height variations. Therefore, other bumping methods, such as vacuum-deposited solder bumps, electrographic techniques, and gold stud bumps may be employed, that will assure better uniformity.

(31) The adhesive bonding method for multichip modules may be used, for example, to form a multichip implementation of a digital autocorrelation circuit for a received radio frequency analog signal as shown in FIG. 3. For example, four identical chips, each with a 32-channel digital autocorrelation circuit, together with the front-end ADC chip, are mounted on a substrate for form a multichip module. Each of the devices are provided on a silicon wafer, which, for example, is patterned to provided Josephson junction circuits which are adapted to operate at <10K. All five chips would need to send weak SFQ pulses (1 mV, 2 ps) between them at a rate of 20 Gbits/s or greater. This embodiment represents a 128-channel digital spectrometer, but since the components are each simpler than an integrated RF-input 128-bit autocorrelator, and the multichip module fabrication technique provides high yield, and in some implementations, a capability for rework, the yield would be much higher than if the entire circuit needed to be on the same chip.

(32) The present invention therefore provides a method for fabricating an MCM by providing a substrate having preformed electrical contacts, placing a liquid curable adhesive over the contacts, placing a chip having corresponding electrical contacts in alignment with the electrical contacts of the substrate to form a liquid curable adhesive-filled gap there-between, compressing the chip and substrate to displace the liquid curable adhesive between the contacts and form electrical pathways, and curing the liquid curable adhesive to form a solid which maintains the electrical pathways.

(33) The present invention further provides an MCM which has a substrate and at least one chip in electrical communication therewith through corresponding sets of predefined electrical contacts, wherein the corresponding sets of predefined electrical contacts are not thermally welded together, and are maintained in relative compression by a cured adhesive surrounding the sets of predefined electrical contacts, which preferably maintains its substantive mechanical characteristics at cryogenic temperatures.

REFERENCES

(34) [1] K. Likharev and V. Semenov, RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems, IEEE Trans. Appl. Supercond., vol. 1, pp. 3-28, March 1991. [2] D. Gupta, W. Li, S. B. Kaplan, and I. V. Vernik, High-speed interchip data transmission technology for superconducting multi-chip modules, IEEE Trans. Appl. Supercond., vol. 11, pp. 731-734, June 2001. [3] J. H. Kang, D. Gupta, and S. B. Kaplan, Design of RSFQ Digitizer on a Multichip Module, IEEE Trans. Appl. Supercond., vol. vol 12, pp. 1848-1851, September 2002. [4] Y. Hashimoto, S. Yorozu, and T. Miyazaki, Transmission of single flux quantum between superconductor chips, Appl. Phys. Lett., vol. 86, pp. 072502-1-072502-3, February 2005. [5] K. E. Yokoyama, G. Akerling, A. D. Smith, and M. Wire, Robust superconducting die attach process, IEEE Trans. Appl. Supercond., vol. 7, pp. 2631-2634, June 1997. [6] D. Yohannes, S. Sarwana, S. K. Tolpygo, A. Sahu, Y. A. Polyakov, and V. K. Semenov, Characterization of HYPRES' 4.5 kA/cm.sup.2 & 8 kA/cm.sup.2 Nb/AlOx/Nb fabrication processes, IEEE Trans. Appl. Supercond., vol. 15, pp. 90-93, June 2005. [7] S. B. Kaplan, V. Dotsenko, D. Tolpygo, High-Speed Experimental Results for an Adhesive-Bonded Superconducting Multi-Chip Module, IEEE Transactions on Applied Superconductivity, vol. 17, pp. 971-974, June 2007.