COMPONENT WITH A THIN-LAYER COVERING AND METHOD FOR ITS PRODUCTION

Abstract

A component (B) is specified which comprises a functional structure (FS) on a carrier (TR) that is spanned by a thin-layer covering (DSA) resting on said carrier. A first wiring layer (VE1) is applied onto or in the thin-layer covering and comprises structured conductor traces that are connected with the functional structure.

Claims

1. A component (B) comprising a carrier (TR), a functional structure (FS) on the carrier (TR), a thin-layer covering (DSA) spanning across the functional structure (FS) and resting on the carrier, a first wiring layer (VE1) that is applied onto the planarization layer and comprises structured conductor traces, wherein the first wiring layer (VE1) is interconnected with the functional structure (FS) via the conductor traces,

2. The component according to claim 1, in which the first wiring layer (VE1) comprises solderable connecting pads (AP).

3. The component according to any of the preceding claims, the partial layers comprise a mechanically stable layer (MSS) and a sealing layer (VS) in which the mechanically stable layer encloses above the carrier (TR) a cavity in which is enclosed at least a portion of the functional structure (FS) in which the wiring layer (VE) is arranged between two of the partial layers.

4. The component according to the preceding claim, wherein the functional structure (FS) is selected from: a MEMS structure (MEMSS), a micro-acoustic structure, an SAW structure (SAWS), a BAW structure (BAWS), a GBAW structure (GBAWS).

5. The component according to any of the preceding claims, also comprising a connection face (AF) on the carrier (TR) which is interconnected with both the functional structure (FS) and, via one of the conductor traces through the planarization layer, with the first wiring layer (VE1).

6. The component according to the preceding claim, in which the connection faces (AF) and the solderable connecting pads (AP) are permuted in terms of the number in which they are contained in the component, or in the horizontal distribution on the component, and/or in the respective horizontal position.

7. The component according to any of the preceding claims, also comprising one or more circuit components connected with the functional structure (FS) on the thin-layer covering above the first functional structure (FS).

8. Component (B) according to any of the preceding claims, in which a second wiring layer (VE2) is arranged between two partial layers of the thin-layer covering (DSA) in which at least one electrically insulating partial layer is arranged between the two wiring layers (VE1, VE2) in which structured conductor traces from both wiring layers are electrically connected with one another, in which electrical connections are provided only in the upper of the two wiring layers (VE2).

9. The component according to any of the preceding claims, in which a plurality of functional structures (FS) operating with acoustic waves are respectively covered by a separate thin-layer covering (DSA) and connected to form an HF filter in which the connection of the functional structures (FS) to form an HF filter is realized at least partially in the first and/or second wiring layer.

10. A method for producing a component (B), comprising the steps: Providing a carrier (TR), arrangement of a functional structure (FS) on the carrier (TR), covering of the first functional structure (FS) with a thin-layer covering (DSA), generation and structuring of a first wiring layer on the thin-layer covering (DSA) so that it is electrically connected with the first functional structure (FS).

11. The method according to the preceding claim, wherein a metal layer is deposited onto the thin-layer covering (DSA) and structured in order to form the first wiring layer, and an electrically insulating layer is produced over the wiring layer and structured so that free areas (FF) remain a solderable metallization is applied onto the free areas (FF) in order to produce solderable connecting pads (AP).

Description

BRIEF DESCRIPTION OF THE DRAWING

[0029] FIG. 1A a simple embodiment of a component according to the invention, in schematic cross section,

[0030] FIG. 1B the same embodiment, in plan view,

[0031] FIG. 2 a second embodiment in schematic cross section,

[0032] FIG. 3 an embodiment having two wiring layers, in schematic cross section,

[0033] FIG. 4 an embodiment having different arrangement of the wiring layer,

[0034] FIG. 5 an embodiment having a special hermetic layer,

[0035] FIGS. 6A to 6E different process steps in the production of a conventional thin-layer covering,

[0036] FIGS. 7B through G various process steps in the production of a component according to the invention,

[0037] FIGS. 8B through F various process steps, according to a variant, in the production of a component according to the invention,

[0038] FIGS. 9B through H various process steps in the production of an additional variant of a component according to the invention,

[0039] FIG. 10B through F various process steps according to a last process variant.

DETAILED DESCRIPTION

[0040] FIG. 1A shows a simple exemplary embodiment using a schematic cross section drawing. Functional structures FS are arranged on a carrier TR which has at least mechanically supportive properties and possibly comprises integrated electrical components that may realize additional component function in conjunction with the functional structures. These realize the component function, or at least a portion of the component function. The functional structures FS are connected with a connection face AF by means of a connecting conductor AL.

[0041] A thin-layer covering DSA spans the functional structure FS, which is embedded in a cavity below this. The connection face AF remains free of the thin-layer covering DSA. Inasmuch, the arrangement coincides with known thin-layer coverings.

[0042] According to the invention, a first wiring layer VE1 is now applied on the surface of the thin-layer covering DSA or in said thin-layer covering, which first wiring layer VE1 comprises structured conductor traces that are advantageously routed to the highest point of the thin-layer covering. A connecting pad AP is then advantageously executed there, which connecting pad AP has a solderable metallization and serves for the connection of the functional structure to an external circuit environment.

[0043] FIG. 1B shows the arrangement in a plan view. In contrast to FIG. 1A, here two connecting conductors AL that lead to two connection faces AF are arranged directly on the substrate, pointing toward the functional structure FS. The thin-layer covering DSA spans the functional structure FS and leaves the connection faces AF free.

[0044] Structured conductor traces that form a first wiring layer VE1 are now directed on the surface of the thin-layer covering DSA. In the shown instance, each of the connection faces AF on the surface of the carrier TR is connected with a separate connecting pad AP on the top side of the thin-layer covering DSA. However, it is also possible to connect multiple connection faces AF with a common connecting pad AP, since a wiring between different connection pads AP is enabled via the first wiring layer VE1.

[0045] While the thin-layer covering DSA is depicted as a uniform material in FIG. 1A, in reality it is for the most part comprised of a plurality of different partial layers to which respective different functions are accorded in the thin-layer covering DSA.

[0046] FIG. 2 shows a mechanically stable layer MSS, which directly faces toward the inside of the cavity, as a lowermost and supporting partial layer of the thin-layer covering DSA. The further processing, especially the application and structuring of additional (partial) layers, is now performed on this mechanically stable layer MSS while maintaining the cavity across the functional structure ES.

[0047] In the exemplary embodiment according to FIG. 2, the metallization for the first wiring layer VE1 is applied directly onto the mechanically stable layer MSS. After the structuring of the wiring layer, a sealing layer VS serves to seal possible openings in the mechanically stable layer MSS (not depicted in the figure). Furthermore, the sealing layer VS is structured so that an area on which the solderable connecting pad AP is generated remains uncovered at the uppermost point of the first wiring layer VE1. The sealing layer VS may thereby serve as a structuring aid.

[0048] Here a hermetic layer HS that covers the entire thin-layer covering (with the exception of the connecting pads AP) is applied as a final layer which, however, is not required in all embodiments.

[0049] FIG. 3 shows an additional embodiment in schematic cross section, in which now the openings OE through which a sacrificial material below the mechanically stable layer MSS has been removed are shown in said mechanically stable layer MSS. The openings OE are sealed with the sealing layer VS, which is applied on the entire surface of the mechanically stable layer MSS.

[0050] In this embodiment, the metallization for the first wiring layer VE1 is still to be applied and structured before the application of the sealing layer VS.

[0051] After the application and structuring of the sealing layer VS, a second wiring layer VE2 is applied and structured in the form of a metallization. This contacts the metallization of the first wiring layer VE1 in a structural gap of the sealing layer VS in which a metallization of said first metallization layer VE1 is uncovered. There, a structured conductor trace of the first wiring layer VE1 may be extended to a pad. The second wiring layer is subsequently routed to the surface of the sealing layer VS and there is provided with a solderable connecting pad AP, advantageously at the highest point. This structure is depicted in the left part of the figure.

[0052] As depicted in FIG. 3, additional structure variants made up of first and second wiring layer VE1, VE2 may be realized as an alternative or in parallel to this. These differ from the embodiment depicted in the left figure part merely in that the connection of first and second wiring layer VE1, VE2 takes place on the surface of the carrier in the region of the connection faces AF. In the first variant, the connection of first and second wiring layer VE1, VE2 takes place at the highest point of the first wiring layer VE1.

[0053] FIG. 4 shows an embodiment in schematic cross section, in which the first wiring layer VE1 is applied onto the sealing layer VS that in turn, as before, also covers the mechanically stable layer MSS. The first wiring layer VE1 in turn contacts a connection face AF on the surface of the carrier TR which is connected with the functional structure FS via a connection conductor AL. A hermetic layer HS covers the component, with the exception of the solderable connecting pad AP.

[0054] An additional possibility to integrate a wiring layer VE into the design of a thin-layer covering is depicted in FIG. 5. There, the sealing layer VS is covered with a hermetic layer HS that leaves uncovered only the connection face AF on the surface of the carrier TR, at least in part. In this way, the first wiring layer VE1 may now be generated over the hermetic layer HS and be electrically connected with the connection face AF.

[0055] After generation of a solderable connecting pad AP, an additional hermetic layer HS2 is generated, especially a passivation of the metallization of the first wiring layer VE1.

[0056] Using various schematic cross sections, FIG. 6 shows various process stages of the method known per se for the production of a known component with conventional thin-layer covering. For this purpose, a functional structure FS, including supply lines and connecting faces AF, is initially produced on a carrier TR. The functional structures FS, for example, constitute transducer structures for an acoustic component, especially an SAW or BAW component.

[0057] Above the functional structures FS, a sacrificial layer OS is now applied and structured such that it defines the areas for the subsequent cavities underneath the thin-layer covering DSA. The sacrificial layer OS preferably comprises an easily structurable material, especially a lacquer layer.

[0058] A mechanically stable layer MSS is now applied onto the entire surface of the structured sacrificial layer OS; for example, an SiO.sub.2 layer is applied by means of sputtering or CVD. FIG. 1A shows the component at this method stage.

[0059] Subsequently, openings OE are produced in the mechanically stable layer MSS; through these openings, the sacrificial layer underneath the mechanically stable layer MSS can now be dissolved away. One or more openings OE can be provided for each provided cavity or for each thin-layer covering DSA. FIG. 6B shows the arrangement at this method stage.

[0060] In the next step, the openings OE are sealed using a sealing layer VS. The sealing layer VS is preferably applied onto the entire surface and subsequently structured, exposing the connecting faces AF as shown in FIG. 6C. The cavity is thus sealed in an air-tight manner.

[0061] The sealing layer VS is preferably an organic lacquer or a polymer.

[0062] FIG. 6D shows the arrangement after the production of a hermetic layer HS above the sealing layer VS as well as after the production of solderable connecting pads AP directly above the connecting faces AF on the surface of the carrier TR. The sequence for the production of the connecting pads AP and the hermetic layer HS can also be switched.

[0063] The hermetic layer HS is preferably a thick and electrically insulating layer, especially a silicon nitride layer.

[0064] FIG. 6E shows the connection of such a component provided with a thin-layer covering DSA by means of bumps BU, which are produced above and in contact with the solderable connecting pads AP. The bumps U can be stud bumps or solder bumps.

[0065] Using schematic cross sections, FIG. 7 shows various process stages according to a first method variant for the manufacturing of components according to the invention. The starting point is an arrangement as depicted in FIG. 6A after the production of the mechanically stable layer MSS. Therefore, the presentation of this first stage is omitted in FIG. 7.

[0066] FIG. 7B shows the arrangement after the structuring of the mechanically stable layer MSS. In particular, the connection faces AF that are electrically connected with the functional structure FS are thereby uncovered on the surface of the carrier TR.

[0067] The mechanically stable layer may be a sufficiently thick SiO.sub.2 layer. However, the mechanically stable layer may also be multi-layer and comprise a silicon nitride layer in addition to the SiO.sub.2 layer or as an alternative to this. However, other multi-layer embodiments are also possible insofar as they may produce a sufficient mechanical stability.

[0068] FIG. 7C shows the arrangement after production and structuring of the first wiring layer VE1. This is applied as a whole-surface metallization and structured into conductor traces and the later connecting pads AP.

[0069] The metallization of the first wiring layer VE1 may be executed from a suitable metal and comprise aluminum, copper, nickel or silver. The metallization may also be multi-layer.

[0070] In the next process step, openings OE are now generated in an uncovered region of the mechanically stable layer MSS, for example via dry etching. The sacrificial layer OS is subsequently extracted through these openings OE, preferably wet-chemically with solvent or, depending on the material of the sacrificial layer OS, with an etchant.

[0071] FIG. 7D shows the arrangement having an opening OE in the region of the section plane (right part of the figure), [sic] an additional opening in a region above or below the section plane, as is shown in the left half of the figure. The openings OE are preferably of small (but sufficient for extraction) cross section so that sufficient surface remains, in addition to the openings OE, to place or to structure conductor trace structures of the first wiring layer VE1 so that they are routed across the entire surface of the mechanically stable layer MSS.

[0072] In the next step, according to FIG. 7E a sealing layer VS is structured over the entire surface so that at least the regions for the later connecting pads AP are uncovered within the first wiring layer VE1.

[0073] The sealing layer VS is preferably applied in a liquid state, or even better a viscous state, [so] that it cannot penetrate into the openings OE. The sealing layer VS may comprise a coating in which a polymer is dissolved in a solvent. However, a liquid polymer may also be used. The polymer may be arbitrarily selected and, for example, may consist of epoxide, acrylate, polyimide or other suitable polymers or coatings, or comprise such materials.

[0074] FIG. 7F shows the arrangement after the application of a hermetic layer HS that is applied over the entire surface and structured so that the region of the connecting pads AP above the first wiring layer VE1 remains free. The hermetic layer HS is preferably a silicon nitride layer, but may also comprise a different insulating material. It is also possible to generate an insulating layer from an organic or inorganic material, and to ultimately further cover this with a metallization insofar as this does not impermissibly electromagnetically interact with the functional structures.

[0075] In the next step, the solderable connecting pads AP are generated at the points at which metallizations of the first wiring layer VE1 or of the connection faces AF are free of sealing layer VS and hermetic layer HS. A solderable connecting pad AP may comprise various metals that may make the metallization of the first wiring layer VE solderable. The solderable connecting pad AP may comprise a gold layer that is advantageously applied over a nickel layer. Copper is also suitable for the generation of a solderable connecting pad AP.

[0076] Depending on the required layer thickness, various process possibilities are suitable for the application of the solderable connecting pad AP. A base metallization or a thin metal layer may be sputtered on. A thicker layer may also be generated via sputtering, or also via vapor deposition. However, it is also possible to reinforce (for example galvanically) an applied primary thin layer or an uncovered metal layer by means of metal deposition from solution. The final layer, preferably comprising gold, may be vapor-deposited.

[0077] FIG. 7G shows the arrangement after the placement of bumps BU on the connecting pads AP. In any event, the first wiring layer VE1 is contacted via the bumps BU and the underlying connecting pads AP, as is depicted in the right part of the figure. Additional connecting pads AP may also be directly provided over connection faces AF in the region, as is depicted in the left part of the figure.

[0078] Using the process stages B through F (See FIG. 6 for method stage A), FIG. 8 shows an additional process variant for the production of a component according to the invention with thin-layer covering and wiring layer.

[0079] FIG. 8B shows the arrangement after the production of openings OE in the mechanically stable layer MSS after the extraction of the sacrificial layer, which was enclosed below said mechanically stable layer MSS. Materials for this arrangement, as well as the process steps required for this, are selected corresponding to a known thin-layer covering or the first process variant according to FIG. 7.

[0080] FIG. 8C shows the arrangement after the application and structuring of a sealing layer VS, which may in turn take place analogously to the depiction in FIG. 6 or 7.

[0081] FIG. 8D shows the arrangement after the application of a first wiring layer VE1 that rests on the sealing layer VS, or whose conductor traces are routed on the surface of the sealing layer VS, and therefore on the surface of the thin-layer covering DSA. The first wiring layer VE1 is connected with the connection faces AF on the surface of the carrier TR.

[0082] In the next step according to FIG. 8E, a hermetic layer HS is applied and structured across the entire surface of the arrangement so that only the regions of the metallization that are provided for the connecting pads AP remain clear in the first wiring layer VE1; alternatively, additional regions over the connection faces AF remain clear. These are depicted as free areas FF in the figure.

[0083] Finally, a solderable connecting pad AP is generated in the region of the free areas FF and provided with bumps BU. FIG. 8F shows the arrangement at this method stage.

[0084] Using various process stages b through h, FIG. 9 shows an additional production variant of a component according to the invention having thin-layer covering. Assuming a structure according to that depicted in FIG. 6A, in the next step the mechanically stable layer MSS is initially structured in order to uncover the connection faces AF on the surface of the carrier TR.

[0085] In the next step, according to FIG. 9C a metallization for the first wiring layer VE1 is applied and structured. The structuring takes place so that a desired wiring of connection faces AF to the connecting pads is generated in the form of structured conductor traces.

[0086] A desired number of openings OE is subsequently generated in the mechanically stable layers MSS of each thin-layer covering, and the sacrificial layer is removed through these openings OE. The openings may be generated via dry etching.

[0087] If an organic coating is used as a sacrificial layer, the extraction of the sacrificial layer preferably takes place with an organic solvent. FIG. 9D shows the arrangement at this method stage.

[0088] According to FIG. 9E, the openings OE are covered by means of a sealing layer VS that is applied over the entire surface and subsequently is structured so that free areas FF are created in which the metallization of the first wiring layer VE1 is uncovered.

[0089] As FIG. 9F shows, a second wiring layer VE2 in the form of a metallization is applied over the sealing layer VS and is structured to produce a desired wiring or interconnection. In the areas of the first wiring layer VE1 that are free of the sealing layer VS, the second wiring layer VE2 is engaged in electrical contact with the first.

[0090] A hermetic layer HS is subsequently deposited over the entire arrangement and structured, wherein free areas FF for the layer connecting pads remain free. FIG. 9H shows the arrangement after the generation of the connecting pads AP, and the bumps that are generated on said connecting pads.

[0091] FIG. 10 shows an additional process variant using process stages b through f. Starting from FIG. 6A, the structure depicted in FIG. 10B is obtained by uncovering the connection faces AF, etching of the mechanically stable layer MSS to produce openings OE, and removal of the sacrificial layer OS.

[0092] FIG. 10C shows the structure after the whole-area application of a sealing layer VS and structuring via uncovering of the connection faces AF.

[0093] FIG. 10D shows the arrangement after a hermetic layer HS has been applied and structured over the sealing layer VS, in that the connection faces AF have been free of the hermetic layer HS again.

[0094] A metallization is now applied and structured over the hermetic layer HS to produce the first wiring layer VE1. It thereby contacts the previously uncovered connection faces AF.

[0095] Since the sealing layer VS is already covered under the hermetic layer HS, now only the upper regions of the first wiring layer VE1 are still uncovered or unprotected. For their protection, a solderable connecting pad is initially generated on the first wiring layer. If the solderable connecting pad AP comprises a gold layer, for example, this may serve to mask the connecting pads AP from the remaining wiring layer or the remaining structures of the wiring layer if these receive an oxide passivation with the aid of an oxidation process. The gold layer, or that connecting pad AP provided with a gold layer, remains untouched by this. FIG. 10F shows the arrangement after the generation of bumps BU on the solderable connecting pads AP.

[0096] The invention could be explained in reference to just a few exemplary embodiments and is, therefore, not limited to these. For the invention, it is essentially insignificant what type of structures may be encapsulated under the thin-layer covering DSA. MEMS components are preferably covered that, for interference-free operation, may not come into direct contact with a covering, and therefore require a cavity for encapsulation.

[0097] SAW and BAW modules are preferably encapsulated, as well as MEMS components. Any thin-layer covering may cover individual functional structures or entire groups of functional structures. The complete interconnection of the functional structures may take place within one of the wiring layers. The external contact of the component or components may be provided at the wiring layer VE1, at the wiring layer VE2, and additionally via the connection faces AF at the layer of the carrier. The connection pads AP are preferably arranged at the highest point or points of the thin-layer covering, since there the smallest stand-off is possible, thus the smallest clearance from a circuit environment into which the component is introduced via soldering.

LIST OF TERMS AND REFERENCES

[0098]

TABLE-US-00001 Structured conductor paths AF solderable connection face (on carrier) AL connecting conductor AP connecting pad (on DSA) B Component BU bump DSA Thin-layer covering FF free area FIL HF filter FS Functional structure HR Cavity HS Hermetic layer MS Metal layer MSS Mechanically stable layer OS Sacrificial layer PL Electrically insulating layer SK Circuit components TR Carrier TS partial layer UBM Solderable metallization for solderable connecting face VE1 First wiring level VE2 Second wiring level VS Sealing layer