Low Loss Impedance Matching Circuit Network Having An Inductor With A Low Coupling Coefficient

Abstract

A wireless transceiver circuit with an impedance matching network within an integrated circuit is disclosed. In some embodiments, the impedance matching network utilizes an inductor, having two portions, disposed on two different metal layers of the integrated circuit. The first end of the first portion of the inductor is in communication with an antenna. The second end of the second portion is in communication with a low noise amplifier for receiving signals and a power amplifier for transmitting RF signals. The second end of the first portion is connected to the first end of the second portion using a via. In another embodiment, the two portions are disposed on the same metal layer, wherein one portion is disposed within the other with a gap separating the two portions. These configurations require less space than using two separate inductors and also have a low coupling coefficient.

Claims

1. An impedance matching network implemented using an integrated circuit, comprising: an inductor comprising a first portion disposed on a first metal layer of the integrated circuit and a second portion disposed on a second metal layer, different from the first metal layer, wherein a first end of the first portion is in communication with an antenna, a second end of the first portion is connected to a first end of the second portion using a via, and a second end of the second portion is in communication with a shared node; a first tunable capacitor connected to the via; and a second tunable capacitor connected to the shared node.

2. The impedance matching network of claim 1, wherein a coupling coefficient between the first portion and the second portion is less than 0.4.

3. The impedance matching network of claim 1, wherein a coupling coefficient between the first portion and the second portion is less than 0.35.

4. The impedance matching network of claim 1, wherein real estate used on the first metal layer for the first portion overlaps real estate used on the second metal layer for the second portion.

5. The impedance matching network of claim 1, wherein the first portion and the second portion comprise a plurality of connected octagonal coils.

6. The impedance matching network of claim 5, wherein an offset between a center of the first portion and a center of the second portion is at least 40 μm.

7. The impedance matching network of claim 5, wherein an innermost octagonal coil of the first portion is vertically aligned with an outermost octagonal coil of the second portion.

8. The impedance matching network of claim 1, wherein the first metal layer is below the second metal layer.

9. The impedance matching network of claim 1, wherein trace widths for the second portion are narrower than trace widths for the first portion.

10. A wireless transceiver comprising: the impedance matching network of claim 1; a low noise amplifier to receive signals from an antenna during a receive mode; and a power amplifier to transmit signals to the antenna during a transmit mode, wherein the low noise amplifier and the power amplifier connect to the shared node.

11. An impedance matching network implemented using an integrated circuit, comprising: an inductor comprising a first portion disposed on a first metal layer of the integrated circuit and a second portion disposed on the first metal layer and contained within the first portion and separated from the first portion by a separation distance, wherein a second end of the first portion is connected to a first end of the second portion, wherein a first end of the first portion or a second end of the second portion is connected to a shared node; a first tunable capacitor connected to the second end of the first portion; and a second tunable capacitor connected to the shared node.

12. The impedance matching network of claim 11, wherein a coupling coefficient between the first portion and the second portion is less than 0.4.

13. The impedance matching network of claim 11, wherein a coupling coefficient between the first portion and the second portion is less than 0.35.

14. The impedance matching network of claim 11, wherein the first portion and the second portion comprise a plurality of connected octagonal coils.

15. The impedance matching network of claim 11, wherein the separation distance is at least 10 μm.

16. The impedance matching network of claim 11, wherein the first end of the first portion is connected to an antenna and the second end of the second portion is connected to the shared node.

17. The impedance matching network of claim 11, wherein the first end of the first portion is connected to the shared node and the second end of the second portion is connected to an antenna.

18. A wireless transceiver comprising: the impedance matching network of claim 16; a low noise amplifier to receive signals from the antenna during a receive mode; and a power amplifier to transmit signals to the antenna during a transmit mode, wherein the low noise amplifier and the power amplifier connect to the shared node.

19. A wireless transceiver comprising: the impedance matching network of claim 17; a low noise amplifier to receive signals from the antenna during a receive mode; and a power amplifier to transmit signals to the antenna during a transmit mode, wherein the low noise amplifier and the power amplifier connect to the shared node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] For a better understanding of the present disclosure, reference is made to the accompanying drawings, in which like elements are referenced with like numerals, and in which:

[0040] FIG. 1 is a block diagram of a prior art wireless device with of-chip impedance matching networks;

[0041] FIG. 2 is a block diagram of a prior art wireless device with a single on-chip impedance matching network that utilizes two inductors;

[0042] FIG. 3 is a representative schematic diagram showing the layout of the impedance matching network of FIG. 2;

[0043] FIG. 4 is a block diagram of a prior art wireless device with a single on-chip impedance matching network that utilizes a single inductor;

[0044] FIG. 5 is a representative schematic diagram showing the layout of the impedance matching network of FIG. 4;

[0045] FIG. 6A-6C are equivalent circuits for the impedance matching network of FIG. 4;

[0046] FIG. 7 is a representative schematic diagram showing the new layout of the impedance matching network according to a first embodiment;

[0047] FIG. 8 is a representative schematic diagram showing the new layout of the impedance matching network according to a second embodiment; and

[0048] FIG. 9 is a representative schematic diagram showing the new layout of the impedance matching network according to a third embodiment.

DETAILED DESCRIPTION

[0049] As described above, the impedance matching network shown in FIGS. 4-5 consumes less space within the integrated circuit than the impedance matching network of FIG. 2. However, as noted above, the quality factor of the impedance matching network of FIGS. 4-5 is degraded as compared to the impedance matching network of FIG. 2. Specifically, due to the use of an inductor with a center tap capacitor in FIG. 5, there is a large coupling coefficient between the two portions of the inductor L.sub.5.

[0050] Coupling coefficient refers to the interaction between two inductors, and is in the range from 0 to 1. The closer two inductors are located to one another, the larger the coupling coefficient, assuming all other factors remain constant. Coupling coefficient is defined as:

[00011]$k=\frac{M}{\sqrt{L_1*L_2}}$

[0051] where k is coupling coefficient, M is mutual inductance and L.sub.1 and L.sub.2 are the two inductance values.

[0052] For example, the coupling coefficient between the inductors L.sub.2, L.sub.4 in FIG. 3 may be about 0.1 or less. In contrast, the coupling coefficient between the two portions of L.sub.5 in FIG. 5 may be about 0.5 to 0.6.

[0053] As shown in the above equation, the larger the coupling coefficient is, the greater the mutual inductance (M).

[0054] Thus, reduction of the coupling coefficient for the two portions of the inductor L.sub.5 would reduce the range of values required for C.sub.3, which in turn, improves the quality factor. One approach to reduce coupling coefficient is to dispose the two portions of the inductor L.sub.5 on two different metal layers of the integrated circuit. Specifically, FIG. 5 shows that the entirety of the inductor L.sub.5 is disposed on the higher metal layer. By separating the inductor into two portions and disposing these two portions on different metal layers, the coupling coefficient may be reduced. For example, the first portion of the inductor L.sub.5, referred to L.sub.5a, may be disposed on a lower metal layer within the integrated circuit. The first portion L.sub.5a is in communication with the antenna. The second portion of the inductor L.sub.5, referred to as L.sub.5b, may be disposed on an upper metal layer within the integrated circuit. The second portion L.sub.5b is in communication with the LNA and the power amplifier.

[0055] It may be beneficial to dispose the first portion L.sub.5a on the lower metal layer, as this metal layer may have higher coupling to the substrate. Since the first portion L.sub.5a is part of the first L-network which has lower impedance (i.e. Z.sub.ANT), it is less affected by any resistive or capacitive coupling to the substrate. Additionally, to minimize the series resistance of the inductor L.sub.5, it may be beneficial to use wider trace widths for the first portion L.sub.5a.

[0056] Conversely, the second portion L.sub.5b is part of a second L-network that has a higher impedance due to its connection to the LNA and power amplifier. Therefore, the second portion L.sub.5b may be more affected by substrate coupling. Thus, the second portion L.sub.5b may be disposed on a higher metal layer than the first portion L.sub.5a.

[0057] Additionally, the trace widths for the second portion L.sub.5b may be narrower than the trace widths of the first portion L.sub.5a since the impedance of the second portion L.sub.5b is more sensitive to substrate coupling.

[0058] Further, center tap capacitor C.sub.3 may be connected to the via that connects the first portion L.sub.5a to the second portion L.sub.5b.

[0059] In each of the embodiments described, the wireless device is implemented as an integrated circuit, wherein the LNA and power amplifier are connected to a shared node. An antenna is in communication with a pad of the integrated circuit. The impedance matching network is disposed between the pad and the shared node.

[0060] In FIG. 7, the transceiver circuit 700 is disposed within an integrated circuit. The transceiver circuit 700 is in communication with an antenna 710 through a pad 705. Low noise amplifier 702 and power amplifier 701 are within the transceiver circuit 700 and both connect to a shared node 703. The outermost coil of the first portion L.sub.5a is in electrical contact with the pad 705.

[0061] In this embodiment, the first portion L.sub.5a and the second portion L.sub.5b are offset from one another in one direction. In one particular embodiment, the offset between the centers of the first portion L.sub.5a and the second portion L.sub.5b is about 40 μm. Of course, in certain embodiments, the offset may be greater than this value. In other embodiments, the offset may be less than this value. In one embodiment, L.sub.5a may have an inner diameter of 90 μm and an outer diameter of 135 μm, while L.sub.5b may have an inner diameter of 90 μm and an outer diameter of 145 μm.

[0062] Assume the direction upward from the center of first portion L.sub.5a is defined as 0°, and the direction to the right of the center of first portion L.sub.5a is defined as 90°. Thus, in this embodiment, the center of the second portion L.sub.5b is offset from the center of the first portion L.sub.5a at an angle of 0°.

[0063] In this embodiment, both portions are created using a plurality of connected octagonal coils. The center of each portion may be defined as follows. A normal line may be drawn from the midpoint of each segment of each octagonal coil. The point at which all of these normal lines intersect is the center of the portion. The locations at which the octagonal coils are closest to the center may be referred to as the inner diameter. The locations at which the octagonal coils are furthest from the center may be referred to as the outer diameter.

[0064] In this embodiment, a via 730 connects the first portion L.sub.5a to the second portion L.sub.5b. Note that the innermost coil of the first portion L.sub.5a is aligned in the height direction with the outermost coil in the second portion L.sub.5b. In this way, the connection between the first portion L.sub.5a and the second portion L.sub.5b is a vertical via. C.sub.3 is connected to via 730 using metal trace 740, which may be disposed on the higher metal layer.

[0065] For the innermost coil of the first portion L.sub.5a to vertically connect to the outermost coil of the second portion L.sub.5b, the centers of the two portions L.sub.5a, L.sub.5b may be offset by a distance equal to the difference between the outer radius of the second portion and the inner radius of the first portion. If the offset is equal to this difference, the two portions may be connected using only a vertical via. If the offset is greater or less than this difference, the two portions may be connected by a vertical via and a metal trace.

[0066] The innermost coil of the second portion L.sub.5b is connected to the shared node 703 using second metal trace 750, which is disposed on the lower metal layer. In certain embodiments, this is the same metal layer that the first portion L.sub.5a is disposed on. A second via 745 is used to connect the innermost coil of the second portion L.sub.5b, which may be disposed on an upper metal layer, to the second metal trace 750. Capacitor C.sub.2 is also connected to second metal trace 750.

[0067] A control circuit 770 may be in communication with C.sub.2 and C.sub.3. As described above, these capacitors are tunable. In certain embodiments, the control circuit may be a digitally controlled capacitor array, comprising a plurality of capacitors that are arranged in parallel, wherein the control circuit may enable one or more of these parallel capacitors to achieve the desired capacitance for C.sub.2 and C.sub.3. In certain embodiments, the specific capacitor values may be stored in the control circuit as digital bytes, where each bit denotes whether a specific capacitor should be enabled or remain disabled.

[0068] While FIG. 7 shows the two portions L.sub.5a, L.sub.5b offset in the vertical direction (or 0°), the two portions may also be offset in the horizontal direction. This may be achieved, for example, by rotating the layout shown in FIG. 7 by 90°.

[0069] The values of L.sub.5a and L.sub.5b and the minimum and maximum values for C.sub.2 and C.sub.3 may be determined using the equations recited above, which utilize Z.sub.ANT, R.sub.max, R.sub.PA, M, and ω.sub.0.

[0070] FIG. 8 shows another embodiment of the present disclosure. The transceiver circuit 800 is disposed within an integrated circuit. The transceiver circuit 800 is in communication with an antenna 810 through a pad 805. Low noise amplifier 802 and power amplifier 801 are within the transceiver circuit 800 and both connect to a shared node 803. The outermost coil of the first portion L.sub.5a is in electrical contact with the pad 805.

[0071] In this embodiment, the center of the first portion L.sub.5a and the center of the second portion L.sub.5b are offset in two directions. In FIG. 8, the center of the second portion L.sub.5b is offset from the center of the first portion L.sub.5a at an angle of 45°.

[0072] In this embodiment, a via 830 connects the first portion L.sub.5a to the second portion L.sub.5b. Note that the innermost coil of the first portion L.sub.5a is aligned in the height direction with the outermost coil in the second portion L.sub.5b. In this way, the connection between the first portion L.sub.5a and the second portion L.sub.5b is a vertical via. Of course, the connection may be created using a trace and a via in embodiments where the innermost coil of the first portion L.sub.5a and the outermost coil of second portion L.sub.5b are not vertically aligned. C.sub.3 is connected to via 830 using metal trace 840, which is disposed on the higher metal layer.

[0073] The innermost coil of the second portion L.sub.5b is connected to the shared node 803 using second metal trace 850, which is disposed on the lower metal layer. In certain embodiments, this is the same metal layer that the first portion L.sub.5a is disposed on. A second via 845 is used to connect the innermost coil of the second portion L.sub.5b, which may be disposed on an upper metal layer, to the second metal trace 850. Capacitor C.sub.2 is also connected to second metal trace 850.

[0074] A control circuit 870 may be in communication with C.sub.2 and C.sub.3. This control circuit 870 may be similar to that described with respect to FIG. 7.

[0075] As described above, for the innermost coil of the first portion L.sub.5a to connect to the outermost coil of the second portion L.sub.5b the centers of the two portions L.sub.5a, L.sub.5b may be offset by a distance equal to the difference between the outer radius of the second portion and the inner radius of the first portion. If the offset is equal to this difference, the two portions may be connected using only a vertical via. If the offset is greater or less than this difference, the two portions may be connected by a vertical via and a metal trace. In this embodiment, the centers of the two portions may be offset by 40 μm.

[0076] Thus, in the embodiments shown in FIGS. 7-8, the inductor L.sub.5 comprises two portions, L.sub.5a and L.sub.5b, which are disposed on different metal layers within the integrated circuit. In certain embodiments, the two portions of the inductor at least partially overlap one another. In other words, the real estate used on one metal layer to implement one portion of the inductor at least partially overlaps the real estate used on a different metal layer to implement the second portion of the inductor. In certain embodiments, either the first portion L.sub.5a or the second L.sub.5b may be completely within the real estate used for the other portion. In other embodiments, the first and second portion only partially overlap, as shown in FIGS. 7-8.

[0077] Of course, other configurations may be utilized to reduce the coupling coefficient. One such configuration is shown in FIG. 9.

[0078] The transceiver circuit 900 is in communication with an antenna 910 through a pad 905. Low noise amplifier 902 and power amplifier 901 are within the transceiver circuit 900 and both connect to a shared node 903. The outermost coil of the first portion L.sub.5a is in electrical contact with the pad 905.

[0079] In this embodiment, first portion L.sub.5a and the second portion L.sub.5b are disposed on the same metal layer, which may be an upper metal layer. Further, the center of the first portion L.sub.5a and the center of the second portion L.sub.5b may be coincident.

[0080] In this embodiment, both portions are created using a plurality of connected octagonal coils. The center of each portion may be defined as follows. A normal line may be drawn from the midpoint of each segment of each octagonal coil. The point at which all of these normal lines intersect is the center of the portion. The locations at which the octagonal coils are closest to the center may be referred to as the inner diameter. The locations at which the octagonal coils are furthest from the center may be referred to as the outer diameter.

[0081] In this embodiment, the second portion L.sub.5b is completely contained within the first portion L.sub.5a. The outer diameter of the second portion L.sub.5b is less than the inner diameter of the first portion L.sub.5a, such that the outer diameter of the second portion L.sub.5b is separated from the inner diameter of the first portion L.sub.5a by a separation distance 925. In certain embodiments, the separation distance 925 may be 10 μm or more. For example, in one embodiment, the second portion L.sub.5b has an inner diameter of 65 μm and an outer diameter of 120 μm, while L.sub.5a has an inner diameter of 145 μm and an outer diameter of 160 μm. This creates a separation distance 925 of nearly 12.5 μm. This separation distance 925 may be increased by increasing the inner diameter of the first portion L.sub.5a, or by decreasing the outer diameter of the second portion L.sub.5b. This separation distance 925 aids in decreasing the coupling coefficient. In some embodiments, the configuration shown in FIG. 9 may have a coupling coefficient of less than 0.5. In certain embodiments, the coupling coefficient may be less than 0.4. In certain embodiments, the coupling coefficient may be about 0.33.

[0082] Via 930 is used to connect the innermost coil of the first portion L.sub.5a, which may be disposed on the upper metal layer, to the metal trace 940 disposed on a lower metal layer. C.sub.3 is connected to via 930 using metal trace 940. In this embodiment, C.sub.3 may also be disposed on the lower metal layer.

[0083] The innermost coil of the second portion L.sub.5b is connected to the shared node 903 using second metal trace 950, which is disposed on the lower metal layer. A second via 945 is used to connect the innermost coil of the second portion L.sub.5b, which may be disposed on an upper metal layer, to the second metal trace 950. Capacitor C.sub.2 is also connected to second metal trace 950.

[0084] A control circuit 970 may be in communication with C.sub.2 and C.sub.3. This control circuit 970 may be similar to that described with respect to FIG. 7.

[0085] Furthermore, while FIG. 9 shows the second portion L.sub.5b contained within the first portion L.sub.5a, other embodiments are possible. For example, the first portion L.sub.5a may be contained within the second portion L.sub.5b. To implement this configuration, the outermost coil (which is connected to the pad 905 in FIG. 9) would be connected to the shared node 903. Additionally, the innermost coil (which is connected to the shared node 903 in FIG. 9 using second metal trace 950) would be connected to the pad 905.

[0086] The embodiments shown in FIG. 7-9 may reduce the coupling coefficient from 0.56 (the value realized for the configuration shown in FIG. 5) to less than 0.4. In certain embodiments, the coupling coefficient may be reduced to less than 0.35. In some embodiments, the coupling coefficient may be reduced to less than 0.30. In yet other embodiments, the coupling coefficient may be reduced to less than 0.25.

[0087] The present system and method have many advantages.

[0088] First, as compared to the impedance matching network shown in FIGS. 2-3, the present impedance matching networks reduces the required space by up to 50%. This may be critical within integrated circuits.

[0089] Second, referring back to the relationship between C.sub.3 and C.sub.1, it was determined that for a maximum value of C.sub.1=0.634 pF, a center frequency of 2.45 GHz and a mutual inductance of 1.22 nH (based on a coupling coefficient of 0.56), the maximum value of C.sub.3 would be 0.776 pF, a 22% increase over C.sub.1. However, if the coupling coefficient is reduced to 0.3, the mutual inductance is reduced to 0.8 nH. Thus, the maximum value of C.sub.3 is now 0.720 pF. This is only a 13.5% increase over C.sub.1. Thus, the quality factor is greatly improved for the configurations shown in FIGS. 7 and 8, as compared to that shown in FIG. 5.

[0090] In summary, the configurations shown in FIG. 7-9 represent a compromise between best quality factor (achieved using two physically separate inductors) and smallest space (achieved using a single center tapped inductor). The configuration is 65% of the area used by the configuration shown in FIG. 3 and has a quality factor of the capacitor that is only 13.5% worse than that for the configuration shown in FIGS. 2-3.

[0091] The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Further, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein.