Abstract
A neurostimulator incorporating a novel chip design that uses the principle of redundant signal crossfiring to overcome electronic component mismatch error in general and transistor mismatch error in particular, to yield superior quality neurostimulation signal generation, useful in enhancing the bidirectional human-machine interface in prosthesis operation for the restoration of somatosensation for an amputee.
Claims
1. A neurostimulator system, comprising: at least one digital-to-analog converter configured to receive an analog peripheral nervous system electrical signal from a patient and to convert said analog signal into a corresponding digital signal; at least two current mirror circuits configured to receive digital electrical signals from said digital-to-analog converter and to provide mirrored current to at least two additional circuit components; at least two or more current drivers, at least one being an anodic output current driver, and at least one being a cathodic output current driver, said drivers being configured to scale the current signals received from said mirror circuits by a multiplying factor, and further configured to driving the constant current to at least one output electrode; wherein said outputs of said two or more current drivers are configured so as to create a combined, crossfiring, output of said current drivers that produces a redundant sensing structure that produces accurate current pulses with an effective super-resolution accuracy beyond ordinary limitations imposed by physical constraints of materials in said system.
2. The system as claimed in claim 1, wherein said redundant structure is configured so as to achieve a super-resolution signal accuracy outcome by applying the effects of random mismatch error function to said system, with the proviso that mismatch avoidance and mismatch compensation functions are not applied in achieving said super-resolution signal accuracy outcome.
3. The system as claimed in claim 2, wherein said random mismatch error function is configured so as to select and tune transistor size to achieve a desired mismatch ratio of 10% to 20%.
4. The system as claimed in claim 3, additionally comprising an on-chip timing generator.
5. The system as claimed in claim 4, additionally comprising both on-chip and off-chip components configured so as to retrievably store calculated optimal transistor configurations obtained through foreground calibration, and which configurations can be retrieved and read by said on-chip timing generator so as to produce signal output with super resolution accuracy.
6. The system as claimed in claim 5, wherein said on-chip component is a memory chip component of said system.
7. The system as claimed in claim 5, where said off-chip component is a look-up table component of said system.
8. The system as claimed in claim 1, additionally comprising an external controller configured so as to ensure charge-balancing that is achieved by digital compensation for residual mismatch between said anodic and cathodic currents.
9. The system as claimed in claim 8, wherein said charge balancing is further characterized as being coarse level charge balancing.
10. The system as claimed in claim 8, where said charge balancing is further characterized as being fine level charge balancing.
11. The system as claimed in claim 1, configured so as to modulate the neurostimulation intensity of said crossfiring redundant signal output to create various levels of somatosensorial signal outputs of from light to strong touch in real time in a neuroprosthesis device.
12. The system as claimed in claim 2, wherein said random mismatch error function is configured so as to select and tune diode size to achieve a desired mismatch ratio.
13. The system as claimed in claim 2, wherein said random mismatch error function is configured so as to select and tune resistor size to achieve a desired mismatch ratio.
14. The system as claimed in claim 2, wherein said random mismatch error function is configured so as to select and tune capacitor size to achieve a desired mismatch ratio.
15. The system as claimed in claim 2, whereby application of the effects of random mismatch error function in said system is configured so as to be applied to extremely large mismatches to achieve super-resolution over 10-fold beyond intrinsic resolution of said design imposed by physical constraints of materials in said system.
16. A high-resolution constant-current stimulator neuroprosthesis neurostimulator chip, comprising: at least one digital-to-analog converter configured to receive an analog peripheral nervous system electrical signal from a patient and to convert said analog signal into a corresponding digital signal; at least two current mirror circuits configured to receive digital electrical signals from said digital-to-analog converter and to provide mirrored current to at least two additional circuit components; at least two or more current drivers, at least one being an anodic output current driver, and at least one being a cathodic output current driver, said drivers being configured to scale the current signals received from said mirror circuits by a multiplying factor, and further configured to driving the constant current to at least one output electrode; wherein said outputs of said two or more current drivers are configured so as to create a crossfiring, combined output of said current drivers that produces a redundant structure to produce accurate current pulses with an effective super-resolution beyond limitations of physical constraints of mismatch error in materials in said system.
17. An electrical neuromodulation neurostimulator chip for the generation of neurostimulation signals in a neuroprosthesis, wherein said chip comprises: at least one digital-to-analog converter configured to receive an analog peripheral nervous system electrical signal from a patient and to convert said analog signal into a corresponding digital signal; at least two current mirror circuits configured to receive digital electrical signals from said digital-to-analog converter and to provide mirrored current to at least two additional circuit components; at least two or more current drivers, at least one being an anodic output current driver, and at least one being a cathodic output current driver, said drivers being configured to scale the current signals received from said mirror circuits by a multiplying factor, and further configured to driving the constant current to at least one output electrode; wherein said outputs of said two or more current drivers are configured so as to create a crossfiring, combined output of said current drivers that produces a redundant structure to produce accurate current pulses with an effective super-resolution beyond limitations of physical constraints of materials in said system.
18. A method of rehabilitating an amputee by fitting said amputee with a tactile-sensitive neuroprosthesis comprising the neurostimulator chip of claim 17.
19. The method of claim 18, wherein said neuroprosthesis is a prosthetic forearm and hand.
20. The method of claim 18, wherein said neuroprosthesis is a prosthetic hand.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0033] FIGS. 1A and 1B are circuit diagrams that provide circuit schematics that show the basic reverse crossfire, or RXR, circuit components of the invention.
[0034] FIG. 2 is a four-part circuit diagram that provides circuit schematics of four alternative embodiments that achieve an identical neural signal output.
[0035] FIG. 3 is as distribution chart displaying the number of redundant configurations corresponding to individual output codes of various RXF structures.
[0036] FIGS. 4A, 4B, and 4C are graphical representations of varying degrees of configuration code diffusion.
[0037] FIGS. 5A and 5B are the graphical results of a Monte Carlo simulation of super-resolution created by the invention.
[0038] FIG. 6 is the graphical result of a Monte Carlo simulation of random mismatch ratio to achieve super-resolution.
[0039] FIG. 7 is a circuit diagram that provides a circuit schematic of a fully integrated neurostimulator design.
[0040] FIG. 8 is a tabular chart of typical physical measurements of transistors used in the RXF circuit.
[0041] FIG. 9 is a schematic flow-chart of the process of tuning transistor mismatch.
[0042] FIG. 10 is the graphical results of a Monte Carlo simulation of the effect of tuning on effective mismatch.
[0043] FIG. 11 is a flow chart and schematic illustration of a stimulator chip control strategy.
[0044] FIG. 12 is a micrograph of a neuromodulator chip of the invention.
[0045] FIGS. 13A and 13B are graphical representations of chip performance under varying mismatch management strategies.
[0046] FIG. 14 is a graphical representation of actual computed mismatch error under varying mismatch management strategies.
[0047] FIGS. 15A and 15B are graphical representations of a stimulator channel integral nonlinearity and of differential nonlinearity.
[0048] FIGS. 16A and 16B are graphical representations of the results of output measurements that demonstrate that decreasing current levels yield lowered distortion levels.
[0049] FIG. 17 is a graphical representation of charge mismatch as a function of charge-balancing capacity of a stimulator channel.
[0050] FIG. 18 is a graphical representation of the results of a stimulator's charge-balancing characteristics measured in a buffered saline solution.
[0051] FIG. 19 is a set of photo images of a prosthesis incorporating a neurostimulation module as part of the prosthesis complete system.
[0052] FIG. 20 is a graphic representation readout of current amplitude pulses generated by prosthesis tactile contact with a solid surface.
[0053] FIGS. 21A and 21B are a pair of graphic representations of before-and-after nerve signal quality following stimulation artifact removal.
DETAILED DESCRIPTION OF THE DRAWINGS AND INVENTION
[0054] Turning first to FIGS. 1A and 1B, there is shown a preferred embodiment of the basic RXF circuitry components, so configured as to create a structure of information redundancy, it being understood herein that numerous alternative different internal configurations can produce the same type of desired output. An important consideration is that a circuit architecture as disclosed here will realize its desired output qualities with a significantly reduced requirement of physical components, as compared to the prior art.
[0055] FIG. 1A illustrates a preferred embodiment of a standard, biphasic, current-mode stimulator, which is comprised of a current digital-to-analog converter (IDAC) 101, current mirror circuits 102 and 103, and anodic (positive) 104, and cathodic (negative) 105 output current driver/multipliers. The drivers perform dual functions: firstly, the scaling of the IDAC current by a multiplying factor, and secondly, the driving of a constant current to an electrode. For each channel of a given embodiment, there is one IDAC that is shared among a plurality of discrete drivers. Subsequently, the anodic i.sub.A and cathodic i.sub.C output currents are expressed as follows:
i.sub.A=I.sub.IDAC.Math.x.sub.SA=I.sub.ref.Math.x.sub.D.Math.x.sub.SA
i.sub.C=I.sub.IDAC.Math.x.sub.SC=I.sub.ref.Math.x.sub.D.Math.x.sub.SC
[0056] Where I.sub.ref is a fixed reference current, x.sub.SA and x.sub.SC are the multiplier codes, and x.sub.D is the IDAC code.
[0057] FIG. 1B illustrates how an RXF structure is created by functionally connecting and combining, or as used in this disclosure, “cross firing” the output of two or more drivers 106, 107, and 108. Each driver contributes a small amount of current shown as pulse forms 109 for driver 1, 110 for driver 2, and 111 for driver n, which together constitute the input current i.sub.A 112, which may be independently adjusted to generate a final desired stimulation pulse 113, and that constitutes the output current i.sub.C 114. The timing of the pulses produced by different drivers must be synchronized, meaning that the anodic and cathodic currents are turned on and off at exact moments in time such that they will behave as a single stimulation channel. This synchronization can be easily achieved with an on-chip timing generator means, well known to those of ordinary skill in the art, that turns on, and turns off, the output from two or more drivers simultaneously at desired and calculated time internals so as to achieve synchronization of the outputs.
[0058] FIG. 2 illustrates examples of several alternative circuit configurations that produce the same theoretical output when there is no mismatch error. Here the IDAC's resolution is expressed as N.sub.D=5 and the multiplier's resolution is expressed as N.sub.S=4. These four illustrated configurations of different IDAC and multiplier values will generate the same output code i.sub.C=8. The RXF structure is seen to be redundant because the same output code can be generated by numerous different configurations of the IDAC and multiplier. In practice, there may be up to tens to hundreds of distinct configurations associated with each output code. The varying configurations of the IDAC and multipliers exhibit complex mutual relationships that depend on the resolution capability of the IDAC, of the multipliers, and of the number of crossfire drivers.
[0059] FIG. 3 illustrates a distribution of the number of redundant configurations 301 corresponding to each output code in a single driver, in this non-limiting example given as a 2-way RXF 302, and a 3-way RXF 303 structure across the sample space, compared to an apparatus having a single driver 304. Manufacturing additional crossfire drivers thus can be seen to extend the maximal output, and exponentially increase the level of redundancy, which is essential to achieve super-resolution. The total number of non-zero, distinct configurations in an n-way RXF structure with n crossfire drivers is expressed as follows:
Σ(n)=(2.sup.N.sup.D−1).Math.[(2.sup.N.sup.S).sup.n−1]
[0060] With each additionally added crossfire driver, the number of configurations (i.e., level of redundancy) grows exponentially, but the physical resources required, i.e., for example chip area, will only increase linearly. This is a significant improvement in improving signal output and quality without a parallel increase in apparatus resource, which would otherwise impose physical size constraints and energy consumption constraints on a neuromodulation device.
[0061] FIGS. 4A, 4B, 4C show a unique property of a redundant structure called “code diffusion” that enables super-resolution. The graphs show the distribution of the analog outputs produced by three different configurations of a 2-way RXF structure. The analog outputs are contained in a continuous sample space with values ranging from 0 to a maximum value of approximately 31.Math.(15+15)=930 LSB where 1 LSB=I.sub.ref. A least significant bit (LSB) is the bit position in a binary integer giving the units value, that is, determining whether the number is even or odd. The LSB is sometimes referred to as the low-order bit or right-most bit, due to the convention in positional notation of writing less significant digits further to the right. It is analogous to the least significant digit of a decimal integer, which is the digit in the ones (right-most) position. To model the random mismatch error, it is assumed that each unit-transistor of both the IDAC and the multipliers has a Gaussian distribution, and that the standard deviation is the mismatch ratio. When generating random samples, negative values are set to zero. FIG. 4A shows that, with no mismatch errors, redundant configurations generate the exact same analog outputs 401 that are centered at integral integer codes 402, e.g. [0, 1, 2, 3, . . . ]. Their distributions are represented by Dirac delta impulses with the weight equal to the number of configurations. FIG. 4B shows that, with small random mismatch errors, the actual values of different analog outputs begin to deviate from their original states and “diffuse” into the adjacent sample space 403. FIG. 4C shows that, with large mismatch errors, the actual values of different analog outputs have exponentially increased and completely diffused 404, and are now evenly distributed across the sample space.
[0062] Code diffusion allows for the generation of sub-integer codes, e.g. [0.1, 0.2, 0.3, . . . with a certain probability that is not normally possible. These sub-integer codes correspond to the sample space's finer partitions, so that there is thus an effective super-resolution that is beyond the baseline figure. For example, to achieve a (+1) super-resolution, redundant configurations that generate all the e.g. sub-integer codes of [0, 0.5, 1, 1.5, . . . ] must be found. To achieve (+2) super-resolution, the required sub-integer codes are [0, 0.25, 0.5, 0.75, 1, . . . ]. While identifying the correct configuration for every output code is an NP-hard optimization problem, it is only possible in an information redundant architecture such as RS. In computational complexity theory, a problem is NP-complete when: a brute-force search algorithm can solve it, and the correctness of each solution can be verified quickly, and the problem can be used to simulate any other problem with similar solvability; where RS is Reed-Solomon codes, which operate on a block of data treated as a set of finite field elements called symbols. RS codes are able to detect and correct multiple symbol errors. The probability of accomplishing this task is maximized when the codes distribute evenly across the sample space, as shown in FIG. 4C.
[0063] FIGS. 5A, and 5B illustrate Monte Carlo simulation results to evaluate the theoretical super-resolution that can be achieved with the present invention. Here, the mismatch error is applied to elements of both the IDAC and multiplier equally. In each simulation, the RXF structure is optimized by an automated brute-force approach, i.e., sorting through all the possible redundant configurations and finding the ones that generate the desired output with the least amount of error. We use the terms “effective resolution” and “effective sensitivity” to measure quantitative performance. The effective resolution is defined as the Shannon entropy, which is computed with respect to a targeted resolution (12 bits) is expressed as follows:
[00001]
[0064] where H.sub.N.sub.x is the effective resolution (entropy) with respect to the targeted resolution N.sub.x; M.sub.N.sub.x is the normalized total mean-square-error integrated over each digital code d∈[0, 2.sup.N.sup.x−1]; θ.sub.0, θ.sub.1, . . . are the corresponding analog outputs. The targeted resolution N.sub.x is the reference upper-bound of the device's super-resolution, which is arbitrarily defined over the full-range. No matter how high the targeted resolution is defined, the effective resolution H.sub.N.sub.x would converge to a maximum value. The effective sensitivity is defined as the smallest change in output current that could be accurately produced by the device. It is computed as follows:
[00002]
[0065] where S.sub.N.sub.x is the effective sensitivity; FR is the targeted output full-range. The metrics are evaluated for all values of the full-range from 0 to the maximum value of 930LSB.
[0066] FIG. 5A shows that RXF enables the achievement of an effective super-resolution that is practically always higher than the device's intrinsic resolution. The effective super resolution, at different values of output full-range, is highly correlated with the number of redundant configurations. The effective resolution in the first 0-50 LSB is low because there are not enough redundant configurations. The effective resolution reaches its highest point at approximately 50-80% (450-750 LSB) of the maximum full-range in which most of the redundant configurations are located. At the practical full-range of 80% (750LSB), the RXF structure achieves 2-3 bits super-resolution beyond the intrinsic baseline. The intrinsic baseline is the best resolution that can be attained with the prior art conventional structure and zero mismatches. Beyond this point, the resolution drops rapidly because the redundant configurations become sparsely distributed, thus there is insufficient redundancy. Moreover, the illustrated results clearly demonstrate a novel, unobvious, unique, and fundamental functional capability of the present invention, which is that mismatch error is utilized to actually enhance resolution. Unlike any previous design in the prior art, the proposed system becomes more accurate as and when the mismatch ratio increases from 0 to 10%. This is because a larger mismatch error leads to a more even distribution of redundant values across the sample space, which maximizes the probability of finding a configuration to generate the desired output. The effectiveness also becomes more consistent (i.e., smaller deviation) when the mismatch ratio increases from 0 to 10%. This shows that the super-resolution achieved by the present invention is high-yield, replicable, and does not rely on a specific random configuration.
[0067] FIG. 5B illustrates that similar functions of the invention are produced, in terms of the other parameter being used, namely effective sensitivity, which is proportional to the inverse of the effective resolution.
[0068] FIG. 6 illustrates Monte Carlo simulation results from evaluating the optimal range of random mismatch ratio to achieve super-resolution. The graph shows the effective resolution, computed at 50%, then 80%, then 90% ranges with different mismatch ratios of from 0.1-100%. The present invention demonstrates that in a novel, non-predicted, and surprising manner, contrary to the teachings of the prior art, a mismatch ratio within a range of about 10 to 20% yields the most preferred, optimal, super-resolution at most ranges. Above that range, not only is there is little significant additional boost to the effective resolution, but also, deviation starts to widen. This suggests a lower effective yield, since fewer samples are capable of achieving the desired super-resolution, and the structure may well become unreliable.
[0069] FIG. 7 illustrates the schematic of a fully-integrated neurostimulator design with 2-way RXF architecture n=2, N.sub.D=5, N.sub.S=4. The IDAC is shown at 701, the current mirror is at 702, and current drivers are at 703 and 704. The current mirrors and drivers are based on an op-amp assisted boosted-cascode current driver and current mirror. Here the design trades away or trades off device area in order to to achieve ultra-high-output impedance. The estimated output impedances are >1 GΩ at 1 mA (source) and >50 GΩ at −1 mA (sink). The output voltage range is set by V.sub.DN=V.sub.SS+0.5 (V) and V.sub.DP=V.sub.DD−0.5 (V), which results in compliance of ±4.5V. The reference current is generated by a voltage-to-current converter circuit, and the value is set to. I.sub.ref=1.5 μA by V.sub.DD and by an external resistor.
[0070] FIG. 8 shows, with respect to the circuit in FIG. 7, the width to length dimensions, in μm, of key transistors and transistor arrays illustrated in FIG. 7. Minimum feature-size transistors are used whenever possible (e.g., IDAC) to maximize the available mismatch error. Nevertheless, larger transistors are needed for the driver, the cascode, and the output switches, in order to meet the voltage-drop requirement for maintaining output compliance. The anodic circuits generally use larger transistors than their cathodic counterparts because the current drivability of P-channel metal-oxide-semiconductor (PMOS) is about 50% less than that of N-channel metal-oxide semiconductor (NMOS).
[0071] Proceeding contrary to conventional wisdom, the present invention utilizes a large level of transistor mismatch of approximately 10-20% as a desirable element of a most preferred design embodiment. The present invention's key advantage is its ability to convert mismatch error from a concerning and vexing problem into a desirable and useful means for achieving previously unachievable signal resolution and sensitivity, allowing designers of ordinary skill in the art to utilize smaller-sized components, and to relax physical layout constraints, which were engineering compromises that were required to be made in order to suppress mismatches in past design approaches. While the implication is that the RXF technique would work better in a deep submicron complementary metal-oxide semiconductor (CMOS) process with a large amount of mismatch, the random mismatch existing in the standard CMOS process may not be adequate. In situations where a “naturally” occurring mismatch is thought to be insufficient, it is now possible to increase the amount of error on purpose.
[0072] FIG. 9 illustrates a flow chart of a preferred procedure to tune a transistor mismatch ratio to achieve optimal super-resolution. Monte Carlo simulations can be used during the design process to evaluate the effective mismatch ratio. Random mismatch error (spread) is caused by variations and mismatches, while process (systematic) error (offset) is caused by non-ideal schematic and parasitic elements. If the random error in a design does not reach the most preferable level (i.e, 10-20%), then “artificial” mismatches may be created by arbitrarily tuning the individual unit transistors' size (W/L) by a range of from a few tens to a few hundred nanometers from the nominal value. The tuning values are randomly generated in a computer and manually added to each unit-transistor, (though this may influence the systematic error). The procedure is repeated with each bit of the IDAC and multiplier to the extent necessary. The procedure is ideally carried out with post-layout simulations, because the parasitic elements could result in creating additional systematic errors.
[0073] FIG. 10 illustrates the result of a Monte Carlo simulation, where the effective mismatch includes both the systematic error 1001 and random error 1002 components. The tuning process described above may introduce sought-after additional systematic errors, while not affecting the random error component.
[0074] FIGS. 11A, and 11B show the present invention's stimulator control strategy, which consists of both an on-chip logic/memory process, and an off-chip logic/memory process. To achieve super-resolution, an RXF structure must be optimized. This is done with a one-time chip calibration procedure at the chip factory where all of the driver's output currents are measured. There are 2 (2.sup.5−1).Math.(2.sup.4−1)=930 non-zero values per driver to be measured, both cathodic and anodic. All the crossfire configurations are then computed. There are 2 (2.sup.5−1).Math.(2.sup.4.Math.2.sup.4−1)=15,810 non-zero configurations per channel in a 2-way RXF structure. The optimized configuration associated with each desirable output current can be easily found by sorting through all the available values in a brute-force manner. While it is not an elegant solution, the optimization procedure only needs to be done once with the off-chip computation. The optimized configurations are then stored in an external lookup table. With a 10-bit effective resolution, the table size would be calculated to be 2 2.sup.10 (5 +4 +4)=26,624 bits (3.3 kB) per channel. An external controller maps each desirable output with the lookup table's optimized configuration during normal operation. The configuration is loaded into the stimulator chip via a transmission protocol consisting of a 10 MHz clock line and a data line.
[0075] The on-chip timing generator circuits produce stimulation pulses. This is essential to achieve a near-perfect synchronization of multiple drivers in a crossfire configuration. All of the stimulation parameters, such as pulse-width, IDAC, multiplier, polarity, and the like, are stored in integrated registers. The anodic and cathodic phases of a biphasic pulse can be independently configured to produce both symmetrical and asymmetrical stimulation with any ratio setting. New IDAC and multiplier configurations are loaded during the interphase delay. In a most preferred embodiment of the invention, a 16-bit register at a base clock of 10 MHz to control the pulse-width is used. This allows generating any timing from 0.01 msec to 6.56 msec with 0.1 μsec adjustment step. The adjustment step is also used to digitally compensate for the residual mismatch between the anodic and cathodic currents to ensure charge-balancing. This is achieved by tuning the anodic and cathodic pulse-width such that:
minimize|i.sub.A.Math.(t.sub.A+Δt.sub.A)−i.sub.C.Math.(t.sub.C+Δt.sub.C)|
[0076] The adjustment timings (Δt.sub.A, Δt.sub.C) are computed by an external controller based on the measured currents i.sub.A, i.sub.C and required pulse-width (t.sub.A, t.sub.C).
[0077] FIG. 12 shows a photomicrograph of a prototype chip of the most preferred embodiment of the invention, which was fabricated using the GlobalFoundries 0.18 μmBCDLite process. This embodiment utilizes isolated high-voltage LDMOS transistors, which are capable of supporting up to 30V. The disclosed chip contains 8 RXF channels (utilizing 16 current drivers) and occupies a core area of approximately 0.8 mm×2.3 mm. The chip's overall static power consumption is approximately 2.4 mW for the analog circuits at a 10V (±5V) supply and 1.6 mW for the digital circuits at a 1.8V supply. Most of the static power is generated from the high-voltage op-amps' bias current, which can be shut down during the interval that a channel is not in use.
[0078] Chip measurement results. FIGS. 13A and 13B illustrate the measured results of the effective resolution and effective sensitivity for the above-described chip. The data were acquired from different channels and chips N.sub.Ch=8, N.sub.IC=10. The reference current was set to I.sub.ref=1.5 μA, which translates to a practical output full-range of approximately 1.1 mA. The RXF technique of the present invention results in an effective super-resolution of 2-3 bits beyond the intrinsic baseline, conforming with the theoretical analysis. The effective sensitivity is well below the reference current across most of the output full-range, which was not possible to achieve in any prior art approach.
[0079] FIG. 14 illustrates the actual mismatch error computed from the measured current outputs for each bit of the IDAC and multiplier. The IDAC exhibits desirable random and systematic error, falling within the optimal 10-20% range.
[0080] FIGS. 15A and 15B illustrate the measured integral nonlinearity (INL) and differential nonlinearity (DNL) of a stimulator channel. Here both the x-axis and y-axis are normalized to the targeted resolution of 12 bits over the 1.1 mA full range. The codes were optimized so that the outputs are always monotonic. The measured channel achieves an effective super-resolution of 9.75 bits and effective sensitivity of 1.28 μA. Unlike a conventional ADC/DAC, the INL and DNL of an RXF device are not symmetrical. Lower digital codes are more accurate because they contain more redundant configurations. The large spikes of INL/DNL data in higher digital codes (3500-4000 LSB) and the brief peak in the area of 0-50 LSB are associated with regions where there are not enough redundant configurations and their distribution is accordingly sparse.
[0081] FIG. 16A illustrates examples of measured output current using, for example, a 1 kΩ resistive load. In this test, the chip generated a train of biphasic stimulation pulses at various output current levels of 100, 200, 500, and 1000 μA. Each pulse was accurately modulated to produce a sinusoidal waveform with a 5 μA ac amplitude. FIG. 16B zooms in to show greater detail of the pulse trains. The results indicate that the output at lower current levels is more accurate than the output at higher current levels, i.e., the sinusoidal waveforms of 100 or 200 μA are visibly less distorted than the sinusoidal wave forms of 500 or 1000 μA. Nevertheless, the waveform deviation at 1000 μA level is still within an accuracy of ±1 μA.
[0082] FIG. 17 illustrates a detail of the measured charge-balancing characteristics of a stimulator channel, previously alluded to in FIG. 1B. In this embodiment there were used a 1 msec pulse-width, anodic (positive) leading pulses, cathodic (negative) trailing pulses, and a lumped electrode model expressed as as C=0.5 μF, R.sub.S=1 kΩ, R.sub.P=10 MΩ. There are two levels of charge-balancing, coarse and fine, both of which are digitally calculated by an external controller based on the measured currents and optimized configurations. The coarse calibration involves selecting the optimal IDAC and multiplier configuration of the second phase with a current amplitude matching the first phase. This process is done during the one-time factory optimization based on the measured current of every RXF configuration. Both the IDAC and multiplier values are adjusted during the inter-phase delay and require less than 10 μsec settling time. The fine calibration involves digitally tuning the second phase's pulse-width with 0.1 μsec steps to further compensate for any residual mismatch between the absolute amplitudes of the anodic and cathodic currents. With coarse calibration alone, the current mismatch is less than 0.2% across the entire output full-range. Again, lower current levels have more accurate matching. When combined with fine calibration, the overall charge mismatch is reduced to an insignificant degree ($<0.005%$).
[0083] FIG. 18 illustrates the results of an aqueous environment experiment to verify the stimulator's charge-balancing characteristics in an aqueous saline solution. A pair of stainless-steel needle electrodes were submerged in a phosphate-buffered saline (PBS) preparation. The electrode's impedance was measured at 7.4 kΩ at 1 kHz. The stimulus is a train of cathodic leading, biphasic, symmetric pulses, with 1 msec pulse-width, and a targeted 200 μA current amplitude. The stimulation rate was 100 Hz, which approaches the upper bound of a most preferred embodiment application for the device. The 10 msec pulse-to-pulse spacing was selected since that rate does not allow sufficient time for the electrode to naturally discharge. In the first measurement, RXF with both coarse and fine calibration was used, and after 1000 pulses, the electrode's residual voltage stabilized at about 62 mV. The estimated current amplitudes were estimated and set at [−200.1, 200.0]μA, and 0.5 μsec was added to the second phase. In the second measurement, only one multiplier (but with no RXF) was used, to match the anodic and cathodic current with available configurations, and the residual voltage reached 375 mV and continued to increase. The estimated current amplitudes are [−201.2, 201.6]μA. In the third measurement, neither RXF nor current matching was used, and the residual voltage quickly reached 1813 mV, saturating the electrode interface as water began to undergo electrolysis. Current amplitudes were [−223.2, 230.7]μA.
[0084] FIG. 19 photographically illustrates a neuroprosthesis experimental setup, which demonstrates the need for a high-resolution, fully-integrated neurostimulator, and this need is met by the chip architecture utilized in the present invention. The experiment is designed to restore somatosensation in a transradial amputee using electrical microstimulation while simultaneously acquiring nerve signals and generating new microstimulations that are re-calibrated in response to the processing of acquired nerve signals, in order to control a prosthetic hand's movements. A most preferred embodiment of a neurostimulator chip component is the essential part of the Scorpius neuromodulation system, a proprietary system known to those of ordinary skill in the art, that has both recording, and stimulation functions. The design and specifications of the Scorpius system are reported in Nguyen & Xu et al. A Bioelectric Neural Interface Towards Intuitive Prosthetic Control For Amputees. Journal of Neural Engineering, 17(6), 066001. (2020), the entire disclosure of which is incorporated herein by reference. Three Scorpius devices were used in the setup shown in FIG. 19, which can simultaneously address 24 independent stimulation channels. Four longitudinal intrafascicular electrode (LIFE) arrays were implanted into the patient using the microsurgical fascicular targeting (FAST) technique. The FAST-LIFE microelectrodes target discrete fascicles in the median and ulnar nerves. The design and characteristics of the electrodes are reported by Cynthia K. Overstreet et al Fascicle specific targeting for selective peripheral nerve stimulation. J. Neural Eng. 16 066040 (2019), the entire disclosure of which is incorporated herein by reference. The electrode's wires penetrated through the patients' skin and were connected to the Scorpius devices via standard Omnetics nano-connectors. The prosthesis was a heavily modified i-Limb Access hand (Touch Bionics, Livingston, UK). The prosthetic hand was equipped with touch sensors (Interlink Electronics, CA, USA) at the fingertips. In this most preferred embodiment of the present inventions, the hand's driver was replaced with a customized controller using the ESP32-WROOM-32 module (Espressif Systems, Shanghai, China). The ESP32 sampled force readouts from the sensors at 50 Hz and relayed data to the host server via Bluetooth. The host server used the sensor readouts to modulate the stimulation pulses' current amplitude to create various levels of touch sensation in the patient.
[0085] Turning now to FIG. 20, there is shown the resultant stimulation pattern as a function of elapsed time, as the prosthesis touched and released an object, which stimulation signal was applied to an electrode with clear sensory precepts acquired from previous mapping experiments. The stimulation pattern was a train of cathodic-leading, biphasic, symmetric pulses with a 0.4 msec pulse-width, at a 40 Hz rate. The current amplitude was modulated to be proportional to the applied force. The pulses were only generated when the sensor readout was above a certain threshold. The neurostimulator's super-resolution was essential for modulating the current amplitude with 1 μA accuracy at any given threshold within a 10-1100 μA range. In one particular electrode embodiment shown in FIG. 20, the current amplitude ranged from 220 μA to 280 μA. The lower threshold 220 μA is the smallest current amplitude at which the patient can just barely begin to perceive sensation, while the higher threshold 280 μA is the highest current amplitude at which the patient can comfortably receive and tolerate signals without experiencing pain. Thus, it is essential to produce an accurate current amplitude within this range in order to deliver continuous and desirable sensory feedback from light to strong touch. It also noteworthy that the current thresholds vary widely across electrodes, even for those within the same microelectrode array. The thresholds may be as low as 15 μA and as high as 1000 μA. However, for any specific electrode, the working range (i.e., lower to higher threshold) is most preferably and 50-100 μA.
[0086] FIG. 21A and 21B illustrates neural recordings acquired by the above described Scorpius system while the amputee patient flexed one of the prosthetic “phantom” fingers, and the resultant stimulation signal from the prosthetic finger's tip touchpad was delivered to an adjacent electrode. A charge-balanced neurostimulator also played an important role in motor decoding experiments with simultaneous somatosensory feedback. The data show that the stimulation artifacts overlapped with the nerve signals. Charge-balancing helps reduce the impact of artifacts and prevents long-term charge accumulation, which could hinder the recorder's operation. The results show that the artifacts may be removed to recover most of the nerve data for decoding the amputee's motor intentions. The artifacts are removed offline using the template matching method for demonstration purposes. A brief duration of 2-3 msec at the onset of each stimulation pulse is removed and replaced with a straight line because the recorder's input is fully saturated.
[0087] While the above description contains much specificity, these should not be construed as limitations on the scope of any embodiment, but as exemplifications of the presented embodiments thereof. Many other alternative embodiments and variations are possible within the teachings of the various embodiments. While the invention has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made, and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention will not be limited to the particular embodiment disclosed as the best or only mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims. Also, in the drawings and the description, there have been disclosed exemplary embodiments of the invention and, although specific terms may have been employed, they are, unless otherwise stated, used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention therefore not being so limited. Moreover, the use of the terms first, second, etc. do not denote any order or hierarchy of importance, but rather the terms first, second, etc. are used to distinguish one element from another. Furthermore, the use of the terms a, an, etc. do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items.
[0088] While the invention has been described, exemplified, and illustrated in reference to certain preferred embodiments thereof, those skilled in the art will appreciate that various changes, modifications, and substitutions can be made therein without departing from the spirit and scope of the invention. It is intended, therefore that the invention be limited only by the scope of the claims which follow, and that such claims be interpreted as broadly as is reasonable.
