Class-D amplifier circuit

Abstract

A bridge output stage is coupled to an electroacoustic conversion element via an inductor L. Driving circuits drive the output stage according to pulse signals S.sub.2H and S.sub.2L that correspond to an audio signal S.sub.1. An overcurrent detection circuit asserts an overcurrent detection signal S.sub.3L (i) when a current I.sub.ML that flows through a transistor M.sub.L to be monitored that forms the output stage is continuously larger than a first threshold value for a first period of time or (ii) when the current I.sub.ML that flows through the transistor M.sub.L to be monitored is larger than a second threshold value that is higher than the first threshold value after a predetermined second period of time elapses after the transistor M.sub.L to be monitored turns on.

Claims

1. A Class-D amplifier circuit comprising: a bridge output stage coupled to an electroacoustic conversion element via an inductor; a driving circuit structured to drive the output stage according to a pulse signal that corresponds to an audio signal; and an overcurrent detection circuit structured to assert an overcurrent detection signal (i) when a current that flows through a transistor to be monitored that forms the output stage exceeds a first threshold value for a predetermined first period of time, or (ii) when a current that flows through the transistor to be monitored exceeds a second threshold value that is higher than the first threshold value after a predetermined second period of time elapses after the transistor to be monitored turns on, wherein the overcurrent detection circuit comprises: a first comparator structured to compare a current detection signal that corresponds to a current that flows through the transistor to be monitored with a first threshold voltage that corresponds to the first threshold value, and to generate a first comparison signal indicating a comparison result; a second comparator structured to compare the current detection signal with a second threshold voltage that corresponds to the second threshold value, and to generate a second comparison signal indicating a comparison result; and a judgment circuit structured to generate the overcurrent detection signal based on the first comparison signal and the second comparison signal.

2. The Class-D amplifier circuit according to claim 1, wherein the transistor to be monitored is turned off according to an assertion of the overcurrent detection signal.

3. The Class-D amplifier circuit according to claim 1, wherein, when a predetermined number of cycles of assertions of the overcurrent detection signal consecutively occur, switching of the output stage is suspended.

4. The Class-D amplifier circuit according to claim 1, further comprising a fail output circuit structured to output the overcurrent detection signal to an external circuit.

5. The Class-D amplifier circuit according to claim 1, wherein the current detection signal corresponds to a voltage drop across the transistor to be monitored.

6. The Class-D amplifier circuit according to claim 1, wherein a high-side transistor and a low-side transistor are both set to be the transistor to be monitored.

7. The Class-D amplifier circuit according to claim 1, wherein the output stage is configured as a full-bridge circuit.

8. The Class-D amplifier circuit according to claim 1, monolithically integrated on a single semiconductor substrate.

9. An audio output device comprising: an electroacoustic conversion element; the Class-D amplifier circuit according to claim 1; and a filter circuit comprising an inductor arranged between the Class-D amplifier circuit and the electroacoustic conversion element.

10. An electronic device comprising: an electroacoustic conversion element; the Class-D amplifier circuit according to claim 1; and a filter circuit comprising an inductor arranged between the Class-D amplifier circuit and the electroacoustic conversion element.

11. A control method for a Class-D amplifier circuit coupled to an electroacoustic conversion element via an inductor, the control method comprising: generating a pulse signal that corresponds to an audio signal; driving an output stage of the audio Class-D amplifier according to the pulse signal; and generating an overcurrent detection signal which is asserted (i) when a current that flows through a transistor to be monitored that forms the output stage exceeds a first threshold value for a predetermined first period of time, or (ii) when a current that flows through the transistor to be monitored exceeds a second threshold value that is higher than the first threshold value after a predetermined second period of time elapses after the transistor to be monitored turns on, wherein generating the overcurrent detection signal comprises: comparing a current detection signal that corresponds to a current that flows through the transistor to be monitored with a first threshold voltage that corresponds to the first threshold value so as to generate a first comparison signal indicating a comparison result; comparing the current detection signal with a second threshold voltage that corresponds to the second threshold value so as to generate a second comparison signal indicating a comparison result; and generating the overcurrent detection signal based on the first comparison signal and the second comparison signal.

12. The control method according to claim 11, further comprising suspending switching of the output stage when a predetermined number of cycles of assertions of the overcurrent detection signal consecutively occur.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:

(2) FIG. 1 is a circuit diagram showing an output stage of a Class-D amplifier circuit;

(3) FIGS. 2A and 2B are waveform diagrams each showing an overcurrent protection operation;

(4) FIG. 3 is a diagram for describing DC superimposition characteristics of an inductor;

(5) FIG. 4 is a block diagram showing an audio output device including a Class-D amplifier circuit according to an embodiment;

(6) FIGS. 5A and 5B are waveform diagrams each showing the Class-D amplifier circuit shown in FIG. 4;

(7) FIG. 6 is an operation waveform diagram showing the operation of the Class-D amplifier circuit when magnetic saturation continuously occurs;

(8) FIG. 7 is a circuit diagram showing a specific example configuration of the Class-D amplifier circuit;

(9) FIG. 8 is a block diagram showing a Class-D amplifier employing the BTL method; and

(10) FIGS. 9A through 9C are external views each showing an electronic device.

DETAILED DESCRIPTION OF THE INVENTION

(11) The invention will now be described based on preferred embodiments which do not intend to limit the scope of the present invention but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.

(12) In the present specification, the state represented by the phrase the member A is coupled to the member B also includes a state in which the member A is indirectly coupled to the member B via another member that does not affect the electric connection between them, or that does not damage the functions of the connection between them, in addition to a state in which they are physically and directly coupled.

(13) Similarly, the state represented by the phrase the member C is provided between the member A and the member B also includes a state in which the member A is indirectly coupled to the member C, or the member B is indirectly coupled to the member C via another member that does not affect the electric connection between them, or that does not damage the functions of the connection between them, in addition to a state in which they are directly coupled.

(14) FIG. 4 is a block diagram showing an audio output device 200 including a Class-D amplifier circuit 100 according to an embodiment. As with the circuit configuration shown in FIG. 1, the audio output device 200 includes an electroacoustic conversion element 202, an LC filter 204, an output coupling capacitor 205, and a Class-D amplifier circuit 100.

(15) The Class-D amplifier circuit 100 includes an output stage 102, driving circuits 104H and 104L, a pulse width modulator 106, and overcurrent detection circuits 130H and 130L, which are integrated on a single semiconductor substrate in the form of a function IC.

(16) The half-bridge output stage 102 is coupled to the electroacoustic conversion element 202 via an inductor L of the LC filter 204 and the output coupling capacitor 205. The pulse width modulator 106 receives an audio signal S.sub.1, and generates pulse-width modulated pulse signals S.sub.2H and S.sub.2L. The driving circuits 104H and 104L drive a high-side transistor M.sub.H and a low-side transistor M.sub.L of the output stage 102 according to the pulse signals S.sub.2H and S.sub.2L, respectively. It should be noted that the high-side transistor M.sub.H and the low-side transistor M.sub.L may each be a discrete element external to the Class-D amplifier circuit 100. Description will be made in this embodiment regarding an arrangement in which the high-side transistor M.sub.H is configured as an N-channel MOSFET, and an unshown bootstrap circuit is coupled to the driving circuit 104H.

(17) During a period in which the high-side transistor M.sub.H is turned on and the low-side transistor M.sub.L is turned off, a voltage occurs at the OUT pin which is close to the input voltage V.sub.CC supplied to the power supply pin VCC. On the other hand, during a period in which the high-side transistor M.sub.H is turned off and the low-side transistor M.sub.L is turned on, a voltage occurs at the OUT pin which is close to the ground voltage V.sub.GND supplied to the GND pin. A pulse signal V.sub.OUT is generated at the OUT pin with a duty ratio that changes according to the audio signal S.sub.1. The pulse signal V.sub.OUT is smoothed by the LC filter 204, and the audio signal S.sub.1 is played back by means of the electroacoustic conversion element 202.

(18) The overcurrent detection circuits 130H and 130L are configured to monitor the high-side transistor M.sub.H and the low-side transistor M.sub.L, respectively, and are each configured in the same fashion with respect to function. Here, description will be made regarding the configuration and the operation of the overcurrent detection circuit 130L.

(19) With the overcurrent detection circuit 130L, (i) when a state in which the current I.sub.ML that flows through the transistor M.sub.L to be monitored which forms the output stage 102 is larger than the first threshold I.sub.OCP1 has continued for a predetermined first period of time (which will also be referred to as the judgment time) .sub.1, the overcurrent detection circuit 130L asserts (sets to the high level, for example) an overcurrent detection signal S.sub.3L. This will be referred to as the first condition.

(20) Furthermore, with the overcurrent detection circuit 130L, (ii) when the current I.sub.ML that flows through the transistor M.sub.L to be monitored exceeds a second threshold value I.sub.OCP2 that is higher than the first threshold value I.sub.OCP1 after a predetermined second period of time (which will be referred to as the mask time) .sub.2 after the transistor M.sub.L to be monitored is turned on, the overcurrent detection circuit 130L asserts an overcurrent detection signal S.sub.3L. This will be referred to as the second condition. In the second condition, a detection delay (or judgment time) 3 from the time point at which the current I.sub.ML exceeds the second threshold value I.sub.OCP2 up to the time point at which the overcurrent detection signal S.sub.3L is asserted is sufficiently shorter than the judgment time .sub.1 designed in the first condition. The turn-on event of the transistor M.sub.L to be monitored can be detected based on the gate signal of the transistor M.sub.L. However, the present invention is not restricted to such an arrangement. Also, the turn-on event may be detected based on the pulse signal S.sub.2L or the voltage V.sub.OUT at the OUT pin. Also, the turn-on event may be detected based on an internal signal of the pulse width modulator 106.

(21) For example, the overcurrent detection circuit 130L includes a first comparator 132, a second comparator 134, and a judgment circuit 136. The first comparator 132 compares a current detection signal V.sub.CSL that corresponds to the current I.sub.ML that flows through the transistor M.sub.L to be monitored with a first threshold voltage V.sub.TH1 that corresponds to the first threshold value I.sub.OCP1, and generates a first comparison signal S.sub.4 that indicates a comparison result. For example, when V.sub.CSL>V.sub.TH1, i.e., when I.sub.ML>I.sub.OCP1, the first comparison signal S.sub.4 is set to the high level. Conversely, when V.sub.CSL<V.sub.TH1, i.e., when I.sub.ML<I.sub.OCP1, the first comparison signal S.sub.4 is set to the low level.

(22) The second comparator 134 compares the current detection signal V.sub.CSL that corresponds to the current I.sub.ML that flows through the transistor M.sub.L to be monitored with a second threshold voltage V.sub.TH2 that corresponds to the second threshold value I.sub.OCP2, and generates a second comparison signal S.sub.5 that indicates a comparison result. For example, when V.sub.CSL>V.sub.TH2, i.e., when I.sub.ML>I.sub.OCP2, the second comparison signal S.sub.5 is set to the high level. Conversely, when V.sub.CSL<V.sub.TH2, i.e., when I.sub.ML<I.sub.OCP2, the second comparison signal S.sub.5 is set to the low level.

(23) The judgment circuit 136 generates an overcurrent detection signal S.sub.3L based on the first comparison signal S.sub.4 and the second comparison signal S.sub.5. When the first comparison signal S.sub.4 remains at the high level for the first period of time .sub.1, or when the second comparison signal S.sub.5 transits to the high level after the second period of time .sub.2 elapses after the transistor M.sub.L is turned on, the judgment circuit 136 asserts the overcurrent detection signal S.sub.3L.

(24) The overcurrent detection circuit 130H monitors the current I.sub.MH that flows through the high-side transistor M.sub.H. When an overcurrent state is detected, the overcurrent detection signal S.sub.3H is asserted.

(25) The overcurrent detection signals S.sub.3H and S.sub.3L can be employed for overcurrent protection. For example, when the overcurrent detection signal S.sub.3H is asserted, the pulse width modulator 106 switches the pulse signal S.sub.2H to the off level, thereby forcibly turning off the high-side transistor M.sub.H. Similarly, when the overcurrent detection signal S.sub.3L is asserted, the pulse width modulator 106 switches the pulse signal S.sub.2L to the off level, thereby forcibly turning off the low-side transistor M.sub.L.

(26) Alternatively, the overcurrent detection signals S.sub.3H and S.sub.3L may be input to the driving circuits 104H and 104L, respectively. When the overcurrent detection signal S.sub.3H is asserted, the driving circuit 104H may switch the gate signal of the high-side transistor M.sub.H to the low level, thereby forcibly turning off the high-side transistor. Similarly, when the overcurrent detection signal S.sub.3L is asserted, the driving circuit 104L may switch the gate signal of the low-side transistor M.sub.L to the low level, thereby forcibly turning off the low-side transistor M.sub.L.

(27) More preferably, when a predetermined number of cycles, i.e., N cycles (N represents an integer of 2 or more), of assertions of the overcurrent detection signals S.sub.3H and S.sub.3L consecutively occur, the switching operation of the output stage 102 is suspended.

(28) When the overcurrent detection signals S.sub.3H and S.sub.3L are asserted, a fail output circuit 108 changes the electric state of a fail pin FAIL. The FAIL pin is coupled to a processor 206 such as an external CPU or microcomputer. This allows the processor 206 to judge based on the state of the FAIL pin whether or not an abnormal state has occurred in the Class-D amplifier circuit 100. The fail output circuit 108 may include an output stage having an open-drain or otherwise open-collector configuration.

(29) The above is the configuration of the Class-D amplifier circuit 100. Next, description will be made regarding the operation thereof. FIGS. 5A and 5B are operation waveform diagrams each showing the operation of the Class-D amplifier circuit 100 shown in FIG. 4. Description will be made below directing attention to the operation of the overcurrent detection circuit 130L.

(30) First, description will be made with reference to FIG. 5A regarding the operation when no magnetic saturation occurs in the inductor L. After the low-side transistor M.sub.L is turned on at the time point t.sub.0, the current I.sub.ML that flows through the low-side transistor M.sub.L starts to rise. When no magnetic saturation occurs, the slope of the rising of the current is small. In a case in which the current I.sub.ML reaches the first threshold value I.sub.OCP1 at the time point t.sub.1, the overcurrent detection signal S.sub.3L is asserted after the judgment time .sub.1 elapses in this state, i.e., at the time point t.sub.2. This forcibly turns off the low-side transistor M.sub.L, thereby blocking the current I.sub.ML.

(31) Next, description will be made with reference to FIG. 5B regarding the operation to be performed when magnetic saturation occurs in the inductor L. After the low-side transistor M.sub.L is turned on at the time point t.sub.0, the current I.sub.ML that flows through the low-side transistor M.sub.L starts to rise. During a period up to the time point t.sub.1 after the second period of time .sub.2 elapses from the turn-on of the low-side transistor M.sub.L, the overcurrent detection based on the second condition is disabled.

(32) In a case in which the DC current component that flows through the inductor L exceeds the allowable current I.sub.DC.sub._.sub.MAX at the time point t.sub.2, the inductance falls, which raises the slope of rising of the current I.sub.ML. When the current I.sub.ML exceeds the second threshold value I.sub.OCP2 at the time point t.sub.3, the overcurrent detection signal S.sub.3L is immediately asserted (after a delay that is shorter than the judgment time .sub.1). This forcibly turns off the low-side transistor M.sub.L, which blocks the current I.sub.ML.

(33) It should be noted that the overcurrent detection circuit 130H operates in the same manner as that of the overcurrent detection circuit 130L, which can be understood by those skilled in this art. The above is the operation of the Class-D amplifier circuit 100. Next, description will be made regarding the advantage thereof.

(34) With the Class-D amplifier circuit 100, as shown in FIG. 5A, in a case in which the DC current component that flows through the inductor L is smaller than the allowable current I.sub.DC.sub._.sub.MAX, i.e., in a range in which no magnetic saturation occurs, such an arrangement is capable of detecting an overcurrent state based on the first threshold value I.sub.OCP1 according to the first condition.

(35) On the other hand, in a case in which the inductance value of the inductor L falls due to magnetic saturation as a result of the DC current component that flows through the inductor L exceeding the allowable current I.sub.DC.sub._.sub.MAX, the current I.sub.ML that flows through the transistor M.sub.L reaches the second threshold value I.sub.OCP2. In this case, by asserting the overcurrent detection signal S.sub.3L with a delay that is shorter than the first period of time (judgment time) .sub.1, such an arrangement is capable of detecting an overcurrent state before the current that flows through the transistor M.sub.L rises excessively. This allows suitable protection to be performed before the current I.sub.ML enters a damage region represented by the hatched area.

(36) Here, immediately after the transistor M.sub.L of the output stage 102 is turned on, the effects of noise become greater. On the other hand, the DC current component that flows through the inductor L exceeds the allowable current I.sub.DC.sub._.sub.MAX after time elapses to a certain degree after the transistor M.sub.L of the output stage 102 is turned on. Accordingly, in many cases, the DC current component does not exceed the allowable current I.sub.DC.sub._.sub.MAX immediately after the transistor M.sub.L of the output stage 102 is turned on. Thus, by enabling the overcurrent detection based on the second threshold value I.sub.OCP2 after a predetermined second period of time .sub.2 elapses after the transistor M.sub.L to be monitored is turned on, which is employed as a condition for the overcurrent detection based on the second threshold value I.sub.OCP2, such an arrangement is capable of masking noise. This prevents false detection of the overcurrent state due to noise.

(37) FIG. 6 is an operation waveform diagram showing the operation of the Class-D amplifier circuit 100 when magnetic saturation continuously occurs. FIG. 6 shows the operation over multiple switching cycles, the number of which is greater than that shown in FIG. 5B. In a case in which magnetic saturation occurs, the current IM.sub.L that flows through the low-side transistor M.sub.L exceeds the second threshold value I.sub.OCP2 for every switching cycle. A counter counts the number of times the overcurrent detection signal S.sub.3L is asserted. When the count value reaches a predetermined number N, the OUT pin is set to the high-impedance state (both the high-side transistor M.sub.H and the low-side transistor M.sub.L are turned off), which suspends the switching operation of the output stage 102. With such an arrangement, while removing the effects of noise, when magnetic saturation occurs, this allows the playback of an audio signal to be suspended.

(38) The present invention encompasses various kinds of apparatuses and circuits that can be regarded as a circuit configuration shown in FIG. 4 or otherwise that can be derived from the aforementioned description. That is to say, the present invention is not restricted to a specific configuration. More specific description will be made below regarding an example configuration for clarification and ease of understanding of the essence of the present invention and the circuit operation. That is to say, the following description will by no means be intended to restrict the technical scope of the present invention.

(39) FIG. 7 is a circuit diagram showing a specific example configuration of the Class-D amplifier circuit 100. Current detection circuits 150H and 150L generate current detection signals V.sub.CSH and V.sub.CSL that indicate the currents that flow through the high-side transistor M.sub.H and the low-side transistor M.sub.L, respectively. The current detection signals V.sub.CSH and V.sub.CSL may correspond to voltage drops (i.e., drain-source voltages V.sub.DS) of the high-side transistor M.sub.H and the low-side transistor M.sub.L, respectively. In a case in which the on resistance R.sub.ON of the high-side transistor M.sub.H is a known value, the drain-source voltage V.sub.DSH is represented by the following Expression.
V.sub.DSH=R.sub.ONI.sub.MH

(40) The same can be said of the low-side transistor.

(41) The current detection circuit 150H shifts the voltage drop V.sub.DSH across the high-side transistor M.sub.H to a voltage with the ground voltage as a reference voltage, and amplifies the voltage drop thus shifted with a suitable gain as appropriate. The voltage drop V.sub.DSL across the low-side transistor M.sub.L occurs with the ground voltage as a reference voltage. Accordingly, there is no need to shift the voltage drop V.sub.DSL, and the current detection circuit 150L amplifies the voltage drop V.sub.DSL with a suitable gain as appropriate.

(42) As described above, the overcurrent detection circuit 130L may be configured including the first comparator 132, the second comparator 134, and the judgment circuit 136. When the assertion of the first comparison signal S.sub.4 continues for the judgment time .sub.1, a time constant circuit 140 of the judgment circuit 136 asserts (sets to the high level, for example) an output S.sub.6 thereof. By combining the first comparator 132 and the time constant circuit 140, this provides overcurrent detection based on the first condition using the first threshold I.sub.OCP1.

(43) A signal that indicates a turn-on event of the low-side transistor M.sub.L (e.g., gate signal of the low-side transistor M.sub.L or the like) is input to a mask circuit 142 of the judgment circuit 136. The mask circuit 142 masks the change of the second comparison signal S.sub.5 for the mask time .sub.2 from the turn-on event of the low-side transistor M.sub.L. In a case in which the second comparison signal S.sub.5 is asserted after the mask time .sub.2 elapses from the turn-on of the low-side transistor M.sub.L, an output signal S.sub.7 of the mask circuit 142 is asserted (set to the high level, for example). By combining the second comparator 134 and the mask circuit 142, such an arrangement provides overcurrent detection based on the second condition using the second threshold value I.sub.OCP2.

(44) When at least one from among the two signals S.sub.6 and S.sub.7 is asserted, a logic gate 144 asserts the overcurrent detection signal S.sub.3L. For example, the logic gate 144 may be configured as an OR gate.

(45) Description has been made above regarding the present invention with reference to the embodiment. The above-described embodiment has been described for exemplary purposes only, and is by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications.

(46) [First Modification]

(47) The present invention is also applicable to a BTL (Bridged Transformerless) Class-D amplifier circuit 100A having a full-bridge output stage. FIG. 8 is a block diagram showing a BTL Class-D amplifier circuit 100A. An output stage 102A includes four transistors M.sub.HP, M.sub.LP, M.sub.HN, and M.sub.LN. Overcurrent detection circuits 130H.sub.P, 130L.sub.P, 130H.sub.N, and 130L.sub.N are respectively configured to monitor the currents that flow through the four transistors M.sub.HP, M.sub.LP, M.sub.HN, and M.sub.LN. The other configurations are the same as those shown in FIG. 4. The operation method for such a BTL Class-D amplifier is not restricted in particular. Such an arrangement may employ a differential operation method in which the voltage V.sub.OUTP at an OUTP pin and the voltage V.sub.OUTN at an OUTN pin have a complementary relation

(48) Also, such a Class-D amplifier may be operated using a filterless method. Even in such a case of employing a filterless method, an inductor L is inserted in order to remove noise. Accordingly, such an arrangement also has the potential to have a problem of magnetic saturation in the inductor L. Thus, the present invention is effectively applicable.

(49) [Second Modification]

(50) The high-side transistor M.sub.H may be configured as a P-channel MOSFET.

(51) [Third Modification]

(52) The protection operation to be performed when an overcurrent state has been detected is not restricted in particular. For example, the overcurrent detection signals S.sub.3H and S.sub.3L may be supplied to an unshown higher-level controller or otherwise a CPU (Central Processing Unit) or microcomputer external to the Class-D amplifier circuit 100, instead of or in addition to the turn-off of a transistor at which an overcurrent state has been detected or suspension of the switching operation of the output stage. In this case, this allows such an external CPU or the like to execute an appropriate protection operation.

(53) [Usage]

(54) Lastly, description will be made regarding an application of the audio output device 200. FIGS. 9A through 9C are external views each showing an electronic device 1. FIG. 9A shows a display apparatus 600 which is an example of the electronic device 1. The display apparatus 600 includes a housing 602 and speakers 2. The audio output device 200 is built into the housing, and drives the speakers 2. The speakers 2 correspond to the electroacoustic conversion element 202.

(55) FIG. 9B shows an audio component device 700 which is an example of the electronic device 1. The audio component device 700 includes a housing 702 and speakers 2. The audio output device 200 is built into the housing 702, and drives the speakers 2.

(56) FIG. 9C shows a compact information terminal 800 which is an example of the electronic device 1. The compact information terminal 800 is configured as a cellular phone, PHS (Personal Handy-phone System), PDA (Personal Digital Assistant), tablet PC (Personal Computer), audio player, or the like. The compact information terminal 800 includes a housing 802, a speaker 2, and a display 804. The audio output device 200 is built into the housing 802, and drives the speaker 2.

(57) While the preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the appended claims.