Reducing Duration of Start-up Period for a Crystal Oscillator Circuit

Abstract

A crystal oscillator circuit comprises a crystal; oscillator circuitry for generating a crystal oscillation signal at an oscillation frequency; and a kick-start circuit for injecting pulses into the crystal during a start-up period. The oscillator circuitry comprises a differential pair of transistors and can operate in an oscillating mode or a start-up mode. In the oscillating mode, the differential pair of transistors is cross-coupled so that a gate terminal of one transistor is coupled to a drain terminal of the other transistor, and vice versa, and the drain terminals are coupled to the crystal to generate the crystal oscillation signal. In the start-up mode, the kick-start circuit drives the gate terminals of the transistors with said pulses. This crystal oscillator circuit has a decreased start-up time compared to prior art solutions and a reduced influence of parasitic oscillations.

Claims

1. An oscillator system, comprising: a crystal; oscillator circuitry connected to the crystal and configured to: generate a crystal oscillation signal at an oscillation frequency; and operate in a selectable one of at least an oscillating mode and a start-up mode; and a kick-start circuit configured to inject a number of pulses into the crystal during a start-up period of the oscillator system; wherein the kick-start circuit comprises an oscillator, said oscillator configured to: generate said number of pulses during the start-up period of the oscillator system; and be phase locked to said oscillator circuitry during a time period where the oscillator circuitry operates in the oscillating mode.

2. The oscillator system of claim 1 wherein the oscillator of the kick-start circuitry is configured to be fee running during the start-up period of the oscillator system.

3. The oscillator system of claim 1, wherein: the oscillator circuitry comprises a first differential pair of transistors; in the oscillating mode, the first differential pair of transistors are cross-coupled so that: a gate terminal of a first transistor of the first differential pair is coupled to a drain terminal of a second transistor of the first differential pair; and a gate terminal of the second transistor of the first differential pair is coupled to a drain terminal of the first transistor of the first differential pair; each one of the drain terminals of the first and second transistors of the first differential pair further being coupled to a terminal of the crystal to generate the crystal oscillation signal at the oscillation frequency; and in the start-up mode, the kick-start circuit is configured to drive the gate terminals of the first and second transistors of the first differential pair with said number of pulses during the start-up period of the oscillator system.

4. The oscillator system of claim 3 wherein the oscillator system is configured to, in the start-up mode of the oscillator circuit: disconnect the gate terminal of the first transistor of the first differential pair from the drain terminal of the second of the first differential pair; and disconnect the gate terminal of the second transistor of the first differential pair from the drain terminal of the first transistor of the first differential pair.

5. The oscillator system of claim 3 wherein: the oscillator circuitry further comprises a second differential pair of transistors, the second differential pair of transistors being complementary to the first differential pair of transistors; the second differential pair of transistors, in the oscillating mode, are cross-coupled so that: a gate terminal of a first transistor of the second differential pair is coupled to a drain terminal of a second transistor of the second differential pair; and a gate terminal of the second transistor of the second differential pair is coupled to a drain terminal of the first transistor of the second differential pair; each one of the drain terminals of the first and second transistors of the second differential pair further being coupled to a terminal of the crystal to generate the crystal oscillation signal at the oscillation frequency.

6. The oscillator system of claim 5, wherein the kick-start circuit, in the start-up mode, is configured to drive the gate terminals of the first and second transistors of the second differential pair with the number of pulses during the start-up period of the oscillator system.

7. The oscillator system of claim 5, wherein the oscillator system is configured to, in the start-up mode of the oscillator circuit: disconnect the gate terminal of the first transistor of the second differential pair from the drain terminal of the second transistor of the second differential pair; and disconnect the gate terminal of the second transistor of the second differential pair from the drain terminal of the first transistor of the second differential pair.

8. The oscillator system of claim 3, wherein each transistor of the first differential pair of transistors comprises a field effect transistor.

9. The oscillator system of claim 1 further comprising a capacitor configured to be: connected in parallel with the crystal for adjustment of the oscillation frequency when the oscillator circuitry is operating in the oscillating mode; and disconnected from the crystal in the start-up mode.

10. The oscillator system of claim 1, wherein the oscillator system is further configured to determine the number of pulses based on a difference in frequency between a frequency of the pulses and an oscillation frequency of an oscillation generated in the crystal by injecting the pulses into the crystal.

11. The oscillator system of claim 10, wherein the oscillator system is configured to determine the number of pulses so that a phase difference between each one of the pulses and the oscillation signal generated in the crystal by injecting that one and previous pulses of the number of pulses into the crystal is between /2 and /2.

12. The oscillator system of claim 11 wherein: the oscillator is further configured to inject at least a further number of pulses into the crystal during a further start-up period of the oscillator system, wherein a phase difference between pulses of the further start-up period and the crystal oscillation signal is between /2 and /2; and the start-up period and the further start-up period are separated by a time period where the phase difference exceeds /2.

13. An electronic apparatus, comprising an oscillator system comprising: a crystal; oscillator circuitry connected to the crystal and configured to: generate a crystal oscillation signal at an oscillation frequency; and operate in a selectable one of at least an oscillating mode and a start-up mode; and a kick-start circuit configured to inject a number of pulses into the crystal during a start-up period of the oscillator system; wherein the kick-start circuit comprises an oscillator, said oscillator configured to: generate said number of pulses during the start-up period of the oscillator system; and be phase locked to said oscillator circuitry during a time period where the oscillator circuitry operates in the oscillating mode.

14. The electronic apparatus of claim 13, wherein the electronic apparatus comprises a wireless communications device comprising a receiver and/or a transmitter for radio frequency signals.

15. The electronic apparatus of claim 13, wherein the wireless communications device comprises a base station for a wireless communications system.

16. The electronic apparatus of claim 13, wherein the wireless communications device comprises a mobile phone for use in a wireless communications system.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Embodiments of the invention will now be described more fully below with reference to the drawings, in which

[0031] FIG. 1 shows a basic configuration of a crystal oscillator having a cross-coupled core;

[0032] FIG. 2 shows a basic configuration of a crystal oscillator having a cross-coupled core and a complementary cross-coupled core;

[0033] FIG. 3 illustrates the properties of a general cross-coupled core;

[0034] FIG. 4 illustrates the properties of a cross-coupled core with high-pass feed-back;

[0035] FIG. 5 illustrates the properties of a cross-coupled core with capacitive degeneration;

[0036] FIGS. 6a and 6b show an embodiment of a crystal oscillator having a cross-coupled core that can be driven by a kick-start circuit during a start-up phase;

[0037] FIG. 7 shows control signals generated by the kick-start circuit of FIGS. 6a and 6b;

[0038] FIGS. 8a and 8b show another embodiment of a crystal oscillator having a cross-coupled core that can be driven by a kick-start circuit during a start-up phase;

[0039] FIGS. 9a and 9b show a further embodiment of a crystal oscillator having a cross-coupled core that can be driven by a kick-start circuit during a start-up phase;

[0040] FIGS. 10a and 10b show an embodiment of a crystal oscillator having a cross-coupled core and a complementary cross-coupled core that can be driven by a kick-start circuit during a start-up phase;

[0041] FIG. 11 shows control signals generated by the kick-start circuit of FIGS. 10a and 10b;

[0042] FIG. 12 shows a crystal oscillator circuit having a kick-start circuit with a free-running dedicated oscillator;

[0043] FIG. 13 shows a crystal oscillator circuit having a kick-start circuit with a dedicated oscillator that can be locked to an external reference frequency;

[0044] FIG. 14 shows a crystal oscillator circuit having a kick-start circuit with a free-running dedicated oscillator that can be calibrated by being phase locked to the crystal oscillator;

[0045] FIG. 15 shows a first embodiment of a calibrated oscillator for the kick-start circuit of FIG. 14;

[0046] FIG. 16 shows a second embodiment of a calibrated oscillator for the kick-start circuit of FIG. 14;

[0047] FIG. 17 shows how a crystal can be modelled electrically by a series branch in parallel with a shunt capacitance;

[0048] FIGS. 18a and 18b show an embodiment of a crystal oscillator having a cross-coupled core and a complementary cross-coupled core that can be driven by a kick-start circuit during a start-up phase, and which can further disconnect a frequency pulling capacitor;

[0049] FIG. 19 illustrates the phase relationship between kick-start pulses and the oscillation generated in a crystal;

[0050] FIG. 20 shows a diagram of a basic simulation setup demonstrate the effect of the proposed solution;

[0051] FIG. 21 shows simulation results with five injected kick-start pulses;

[0052] FIG. 22 shows simulation results with 10 injected kick-start pulses;

[0053] FIG. 23 shows simulation results with 20 injected kick-start pulses; and

[0054] FIG. 24 shows a base station and a mobile station in which the crystal oscillator can be used.

DETAILED DESCRIPTION

[0055] FIG. 1 shows an example of a basic configuration of a crystal oscillator 1 comprising a crystal or crystal resonator X.sub.1 (XTAL) and a control circuit or oscillator circuitry arranged to maintain oscillations in the oscillator by amplifying a voltage signal over the crystal resonator and feeding it back to the crystal. Crystal oscillators are typically integrated with transceiver chips on which they are used, so that only the crystal resonator itself is external, while the remaining part, the crystal oscillator core, is part of the chip. Further, such crystal oscillators often employ a differential architecture as the one shown in FIG. 1.

[0056] FIG. 1 is a simplified view disregarding some circuitry needed to ensure proper operating point. A cross coupled core (CCC) of two transistors M.sub.1 and M.sub.2 provides a negative resistance to compensate for the losses in the crystal resonator X.sub.1 and other losses associated with the nodes of the crystal as to ensure successful start of oscillation as well as maintaining the oscillation. The source terminals of transistors M.sub.1 and M.sub.2 are coupled to a ground terminal, while the drain terminals are coupled to the two terminals of the crystal X.sub.1. The transistors M.sub.1 and M.sub.2 are cross-coupled in that the gate terminal of each transistor is coupled to the drain terminal of the opposite transistor, thus providing positive feedback driving the crystal X.sub.1 to oscillate at its resonance frequency. An active load is represented by the current sources L.sub.1 and L.sub.2 connected to a positive supply voltage V.sub.DD. An output signal from the oscillator is provided from the output terminals V.sub.out, and V.sub.out. In FIG. 1, each one of the transistors M.sub.1 and M.sub.2 is implemented as an n-type MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), which may also be designated as an NMOS device. However, other transistor types, such as bipolar transistors, could be used as well. As mentioned, FIG. 1 is a simplified view disregarding some circuitry needed to ensure proper operating point, such as biasing circuitry or components as those illustrated in FIGS. 4 and 5 described below.

[0057] During start-up of the oscillator, any tiny fraction of noise around the resonance frequency of the crystal will, due to the positive feedback of the system, start to be amplified, thus ramping up an oscillation at the resonance frequency. However, this normal way of start-up takes a certain time before a stable oscillation is available at the oscillator circuit outputs. This relative long start-up time is unacceptable in the present application of the oscillator circuit.

[0058] Such a crystal oscillator generally has an over-provisioning of negative resistance to provide successful operation over all process, voltage, and temperature conditions (PVT) and to control the start-up time, i.e. the time from activation/power-up to stable output (with respect to amplitude and frequency).

[0059] A variant of the basic crystal oscillator architecture in FIG. 1 is shown as the crystal oscillator 2 in FIG. 2. Instead of having an active load towards V.sub.DD, there is now a complementary cross-coupled core (CCCC) of two transistors M.sub.3 and M.sub.4. This is a current-reuse architecture as the CCCC uses the same current as the CCC to generate negative resistance. The penalty may be somewhat larger parasitic capacitance from the CCCC as it is implemented with PMOS devices that need to have approximately 3 times the width of the NMOS devices in the CCC to generate the same amount of negative resistance.

[0060] Most crystal oscillator architectures suffer from the risk of parasitic oscillation, i.e. that the conditions for oscillations are also fulfilled for other frequencies than the desired. This may also be the case for the circuits of FIGS. 1 and 2, as it will be exemplified below with reference to FIGS. 3 to 5 by considering different biasing solutions. However, other aspects may further complicate the picture in this regard, including effects of package, wires on the printed circuit board used to connect the crystal and the chip etc.

[0061] First, FIG. 3 illustrates the properties of a general cross-coupled core (CCC) as it may be used in voltage-controlled oscillators (with an LC resonance circuit). In this case, the biasing of the gate is given by the DC path in the coil (not shown). FIG. 3 illustrates the core and a small signal model of each transistor. The admittance of the core with two transistors M.sub.1 and M.sub.2 is given by

[00001] $Y_{in} = \frac{i_{in}}{v_{in}} = - \frac{g_{m}}{2},$

where g.sub.m is the transconductance of each transistor, i.e. i.sub.d/v.sub.gs (small signal). This architecture is not possible to use in crystal oscillators as it will lead to a DC bistable solution. This does not happen in an LC-based VCO as the inductor (L) has a center-tap to e.g. the voltage supply (V.sub.DD), which will inhibit the bistable state.

[0062] FIG. 4 illustrates the properties of a cross coupled core with high-pass feed-back. In this crystal oscillator CCC the DC path in the CCC is cut and the biasing has to be given from an external reference, while the oscillating frequency signal is fed back to the gate terminals. FIG. 4 illustrates the core with high-pass feedback and a small signal model of each transistor. The admittance is given by

[00002] $Y_{in} = \frac{i_{in}}{v_{in}} = - \frac{1}{2} .Math. \frac{j .Math. .Math. .Math. .Math. C_{k} .Math. R_{k} (1 - j .Math. .Math. .Math. .Math. C_{k} .Math. R_{k})}{1 +^{2} .Math. C_{k}^{2} .Math. R_{k}^{2}} .Math. (g_{m} + j .Math. .Math. .Math. .Math. C_{k}) + \frac{1}{2} .Math. j .Math. .Math. .Math. .Math. C_{k} = [.Math._{k} = C_{k} .Math. R_{k}] == \frac{1}{2} .Math. (- g_{m} + \frac{1}{R_{k}}) .Math. \frac{^{2} .Math._{k}^{2}}{1 +^{2} .Math._{k}^{2}} + \frac{1}{2} .Math. (- g_{m} + \frac{1}{R_{k}}) .Math. \frac{j .Math. .Math._{k}}{1 +^{2} .Math._{k}^{2}} .$

[0063] As seen in the equation there is not only a negative conductance but a negative susceptance as well, giving that the core provides an inductance that can oscillate with the capacitance load, resulting in a potential parasitic oscillation frequency.

[0064] FIG. 5 illustrates the properties of a cross coupled core with capacitive degeneration. In this crystal oscillator CCC the DC path in the crystal is again cut, but the voltage bias is given from the drain output, which can be biased from an external reference. FIG. 5 illustrates the core with capacitive source degeneration and a small signal model of each transistor. The admittance is given by

[00003] $\frac{i_{in}}{v_{in}} = - \frac{1}{2} .Math. \frac{1}{\frac{1}{g_{m}} + \frac{1}{j .Math. .Math. .Math. .Math. C_{s}}} = - \frac{1}{2} .Math. \frac{j .Math. .Math. .Math. .Math. C_{s} .Math. g_{m} (g_{m} - j .Math. .Math. .Math. .Math. C_{s})}{g_{m}^{2} +^{2} .Math. C_{s}^{2}} = - \frac{g_{m}}{2} .Math. \frac{^{2} .Math. C_{s}^{2}}{g_{m}^{2} +^{2} .Math. C_{s}^{2}} - \frac{j .Math. .Math. .Math. .Math. C_{s}}{2} .Math. \frac{g_{m}^{2}}{g_{m}^{2} +^{2} .Math. C_{s}^{2}} == [_{s} = \frac{C_{s}}{g_{m}}] = - \frac{g_{m}}{2} .Math. \frac{^{2} .Math._{s}^{2}}{1 +^{2} .Math._{s}^{2}} - \frac{j .Math. .Math. .Math. .Math. C_{s}}{2} .Math. \frac{1}{1 +^{2} .Math._{s}^{2}} = - \frac{g_{m}}{2} .Math. \frac{^{2} .Math._{s}^{2}}{1 +^{2} .Math._{s}^{2}} - \frac{g_{m}}{2} .Math. \frac{j .Math. .Math._{s}}{1 +^{2} .Math._{s}^{2}}$

[0065] As seen in the equation there is not only a negative conductance but a negative susceptance as well, giving that the core provides an inductance that can oscillate with the capacitance load, again resulting in a potential parasitic oscillation frequency.

[0066] Thus it can be seen that crystal oscillator architectures often suffer from the risk of parasitic oscillation. Circuits in FIGS. 4 and 5 can have a configuration of capacitance and resistance that removes the parasitic oscillation, but it comes at the cost of reduced transconductance, or in other words loss of negative resistance.

[0067] Below a solution is proposed for ensuring a much faster start-up of the crystal oscillator circuit and at the same time reducing the risk of parasitic oscillations during the start-up phase. The proposed startup circuit is based on using a second source of signal (kick-start circuit) to alternatingly switch the transistors of the cross-coupled core so as to pump energy into the tank of the crystal oscillator. The proposed solution uses a large signal momentarily forcing a reduction of the influence of the parasitic oscillation created by the cross-coupled core itself.

[0068] FIGS. 6a and 6b show an embodiment, implemented as the oscillator circuitry 11 driven by a kick-start circuit 12, of how the crystal oscillator circuit of FIG. 1 can be configured for fast start-up. To control the start-up process, the circuit comprises switches S.sub.1a, S.sub.2a, S.sub.1b and S.sub.2b. In FIG. 6a illustrating the crystal oscillator circuit during a start-up phase, switches S.sub.1a and S.sub.2a are open to break the normal feedback path from the oscillator outputs to the gate terminals of transistors M.sub.1 and M.sub.2, while switches S.sub.1b and S.sub.2b are closed to enable the kick-start circuit 12 to drive the gate terminals of transistors M.sub.1 and M.sub.2 with control signals s.sub.s1 and s.sub.s2. These control signals s.sub.s1 and s.sub.s2 generated by the kick-start circuit 12 have a frequency roughly at the target frequency of the crystal oscillator during normal operation, and as illustrated in FIG. 7, they are 180 degrees out of phase with each other.

[0069] During this start-up phase, the transistors M.sub.1 and M.sub.2 may be driven with a limited amplitude of the kick-start circuit output such that they stay in saturation and switch between two current levels effectively leading to an alternating current through the crystal. Alternatively, M.sub.1 and M.sub.2 may be driven to act as switches effectively leading to that current through the crystal will be alternating between the current from L.sub.1 and L.sub.2. In the latter case, where the kick-start signals drive M.sub.1 and M.sub.2 to act as switches, the kick-start circuit outputs may be regular digital inverters.

[0070] In FIG. 6b illustrating the crystal oscillator circuit during regular operation, i.e. when the start-up phase has been completed, switches S.sub.1a and S.sub.2a are closed to provide the normal feedback path from the oscillator outputs to the gate terminals of transistors M.sub.1 and M.sub.2, while switches S.sub.1b and S.sub.2b are open to disconnect the kick-start circuit 12 from the gate terminals of transistors M.sub.1 and M.sub.2.

[0071] In an alternative embodiment implemented as the oscillator circuitry 21 in FIGS. 8a and 8b, switches S.sub.1a and S.sub.2a are replaced by short circuits, so that the normal feedback path from the oscillator outputs to the gate terminals of transistors M.sub.1 and M.sub.2 is still provided also during the start-up phase. Otherwise, the function of this circuit is the same as illustrated in FIGS. 6a and 6b.

[0072] In FIGS. 9a and 9b the active load towards V.sub.DD represented by the current sources L.sub.1 and L.sub.2, as illustrated in FIGS. 1, 6a, 6b, 8a and 8b has been replaced by the complementary cross-coupled core (CCCC) of the two transistors M.sub.3 and M.sub.4 that was also shown in FIG. 2. Otherwise, the function of this circuit is the same as illustrated in FIGS. 6a and 6b.

[0073] FIGS. 10a and 10b show an embodiment, in which the two transistors M.sub.3 and M.sub.4 are also used for injecting energy into the crystal oscillator 41, by also driving the gate terminals of these transistors with control signals from a kick-start circuit 42. To control the start-up process, the crystal oscillator circuit 41 comprises switches S.sub.1a, S.sub.2a, S.sub.1b, S.sub.2b, S.sub.3a, S.sub.4a, S.sub.3b and S.sub.4b.

[0074] In FIG. 10a illustrating the crystal oscillator circuit during the start-up phase, switches S.sub.1a, S.sub.2a, S.sub.3a and S.sub.4a are open to break the normal feedback path from the oscillator outputs to the gate terminals of transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4, while switches S.sub.1b, S.sub.2b, S.sub.3b and S.sub.4b are closed to enable the kick-start circuit 42 to drive the gate terminals of transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4 with control signals s.sub.s1, s.sub.s2, s.sub.s3 and s.sub.s4. These four control signals s.sub.s1, s.sub.s2, s.sub.s3 and s.sub.s4 generated by the kick-start circuit 42 have a frequency roughly at the target frequency of the crystal oscillator during normal operation, and as illustrated in FIG. 11, signals s.sub.s1 and s.sub.s3 are in phase, and so are signals s.sub.s2 and s.sub.s4. Further, signals s.sub.s1 and s.sub.s2 are 180 degrees out of phase and so are signals s.sub.s3 and s.sub.s4. In the general case, levels V.sub.n1 and V.sub.n2 of signals s.sub.s1 and s.sub.s2 can be different from levels V.sub.p1 and V.sub.p2 of signals s.sub.3 and s.sub.s4 as they are used to drive NMOS and PMOS devices, respectively. In the event that kick-start signals drive the transistors to act as switches, it is possible to use V.sub.n1=V.sub.p1 and V.sub.n2=V.sub.p2, and the kick-start circuit outputs may be regular digital inverters.

[0075] Also here, the transistors may, during the start-up phase, either be driven in saturation so that they switch between two current levels, or they may be driven in the triode region and thus essentially act as switches effectively alternating the crystal terminals between ground and supply.

[0076] In FIG. 10b illustrating the crystal oscillator circuit during regular operation, i.e. when the start-up phase has been completed, switches S.sub.1a, S.sub.2a, S.sub.3a and S.sub.4a are closed to provide the normal feedback path from the oscillator outputs to the gate terminals of transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4, while switches S.sub.1b, S.sub.2b, S.sub.3b and S.sub.4b are open to disconnect the kick-start circuit 42 from the gate terminals of transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4.

[0077] Also in this embodiment, switches S.sub.1a, S.sub.2a, S.sub.3a and S.sub.4a may be replaced by short circuits, so that the normal feedback path from the oscillator outputs to the gate terminals of transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4 is still provided also during the start-up phase.

[0078] The embodiments above are based on a kick-start circuit 12 or 42 that provides periodic square-wave signals. In the general case, however, the signals do not need to be periodic, but must at least have power around the target frequency of the crystal oscillator to be able to charge the oscillator tank with energy. There are a number of possibilities with respect to the source of the kick-start signal.

[0079] FIG. 12 shows a crystal oscillator circuit 40 using a dedicated kick-start oscillator 42 as described above for providing a relatively inaccurate (compared to crystal of crystal oscillator) frequency, e.g. a (free-running) ring oscillator, an LC-oscillator, or a relaxation oscillator to the crystal oscillator 41. A control circuit 43 controls the switches S.sub.1a, S.sub.2a,, S.sub.3a, S.sub.4a, S.sub.1b, S.sub.2b, S.sub.3b and S.sub.4b of the crystal oscillator 41, and thus also the duration of the start-up phase.

[0080] As shown in the crystal oscillator circuit 44 in FIG. 13, the dedicated kick-start circuit 45 may also be locked to an external source or reference 46. It can be envisioned that a mmW-based transceiver may be accompanied by other functions like traditional cellular or WiFi transceivers, localization function (e.g. GPS) etc. that may have a crystal oscillator on its own, which can then be used to act as a reference for the dedicated kick-start oscillator 45. Also in this embodiment, the control circuit 43 controls the switches S.sub.1a, S.sub.2a, S.sub.3a, S.sub.4a, S.sub.1b, S.sub.2b, S.sub.3b and S.sub.4b of the crystal oscillator 41, and thus also the duration of the start-up phase.

[0081] FIG. 14 shows an embodiment of a crystal oscillator circuit 47, in which the dedicated kick-start circuit 48 may be calibrated from the crystal oscillator 41 once or periodically to compensate for process spread and temperature to yield a more accurate frequency. Such a dedicated kick-start circuit will still be able to run at much lower power than the crystal oscillator. Also in this embodiment, the control circuit 43 controls the switches S.sub.1a, S.sub.2a, S.sub.3a, S.sub.4a, S.sub.1b, S.sub.2b, S.sub.3b and S.sub.4b of the crystal oscillator 41, and thus also the duration of the start-up phase.

[0082] The kick-start circuit runs over a given amount of time, e.g. determined by a given number of periods N of the kick-start outputs. This duration of the start-up phase is controlled by the control circuit 43, and later below it will be described how the duration and thus the number of kick-start pulses may be determined.

[0083] In the crystal oscillator circuits shown in FIGS. 12 to 14, the kick-start circuit and the crystal oscillator may of course be replaced by the kick-start circuit 12 and one of the crystal oscillators 11, 21 or 31 shown in FIG. 6a, 6b, 8a, 8b, 9a or 9b, only the transistors of the lower cross-coupled core is used for injecting kick-start pulses into the crystal.

[0084] A dedicated kick-start oscillator 48 can be calibrated versus the crystal frequency during time slots when the crystal oscillator 41 is turned on and in steady-state, e.g. right before the crystal oscillator is scheduled to be turned off, using a (simple) PLL structure. This is illustrated in FIGS. 15 and 16 below. At the end of such a time slot, the control input of the controlled kick-start oscillator is stored for use at a later time instance when the crystal oscillator will be turned on again. At power on of the crystal oscillator, the dedicated kick-start oscillator is operating as a free running oscillator driving the crystal oscillator core using said stored control input.

[0085] A more elaborate scheme could be to store control inputs for various operating conditions including e.g. temperature and supply voltage to be used at another time instance having an operating conditions that is similar to the one for which the control input was stored.

[0086] One embodiment of such a dedicated kick-start oscillator 48 is illustrated in FIG. 15, which shows a partly analog phase-locked loop comprising a phase detector 51, an analog loop filter 52, an analog-to-digital converter or sample/hold circuit 53, an oscillator 54, a divider 55, and two switches A and B. The control for the oscillator 54 is stored either as a digital word or as an analog sample and hold value in the analog-to-digital converter or sample/hold circuit 53. Switch A is not necessarily a physical switch, but could be a logical function. In PLL-mode, switch A is closed while switch B remains open. The A/D-converter is operating continuously and the sample and hold is a feed-through. When the loop is stable (PLL locked), the loop can be broken by opening switch A, and the result is stored in the ADC or S/H 53. During startup of the crystal oscillator, switch A remains open while switch B is closed. The duration of kick-start time, which controls switch B, is described in more detail below.

[0087] Another embodiment of such a dedicated kick-start oscillator is illustrated in FIG. 16, which shows an All-Digital phase-locked loop comprising a time-to-digital converter 57, a digital loop filter 58, the oscillator 54, the divider 55, and the two switches A and B. The control for the oscillator 54 is stored as a digital word. In PLL-mode, switch A is closed while switch B remains open. The Digital Loop Filter is operating continuously. When the loop is stable (PLL locked), the loop can be broken by opening switch A, and the result is stored in the Digital Loop Filter 58. During startup of the crystal oscillator, switch A remains open while switch B is closed.

[0088] The accuracy of the kick-start frequency is going to be dependent on the accuracy of the digital or analog control of the kick-start-oscillator, as well as time dependent variation in voltage supply, temperature, leakage etc. The maximum drift of the crystal oscillator is also added to the total frequency error. The useful number of pulses can then be calculated vs the power off/on cycle.

[0089] The oscillator circuitry shown in FIGS. 10a and 10b can also be extended to disconnect a capacitor, normally used for pulling the frequency of the crystal oscillator, during the start-up phase. FIG. 17 shows how a crystal X.sub.1 can be modelled electrically by a series branch consisting of R.sub.m, C.sub.m, and L.sub.m in parallel with a shunt capacitance C.sub.0. The series branch is also called the motional branch. By switching the crystal oscillator with the kick-start circuit as described above, a considerable part of the current will go through C.sub.0, leading to a high dynamic power consumption and this makes the kick-start less power efficient as the energy provided should be delivered to the motional branch.

[0090] Further, additional capacitance C.sub.L is generally added to the outputs of the crystal oscillator (in parallel with C.sub.0) to control frequency pulling of the crystal oscillator. Thus, C.sub.L will also contribute to dynamic power consumption when the crystal oscillator is driven by the kick-start circuit. FIGS. 18a and 18b show a crystal oscillator 61 where C.sub.L is disconnected during startup with switches S.sub.5p and S.sub.5n, as shown in FIG. 18a. FIG. 18b shows that these switches are closed during normal operation of crystal oscillator. Otherwise, the function of this circuit is the same as illustrated in FIGS. 10a and 10b.

[0091] When the cross-coupled cores are switched by the kick-start circuit, i.e. the transistors are in the triode region and thus essentially act as switches effectively alternating the crystal terminals between ground and supply, the maximum voltage that can appear over the crystal is limited by the supply voltage. Thus, for this case the disconnection of C.sub.L will not reduce start-up time as the maximum voltage is already applied over the motional branch of the crystal. The only way to decrease the start-up time further is by increasing the voltage further.

[0092] The duration of the startup mode, i.e. the time during which the kick-start circuit injects energy into the crystal, is limited by the difference between the crystal oscillator frequency f.sub.xo, and the kick-start output frequency f.sub.k. For some embodiments, the frequency of the kick-start circuit may be different, inaccurate and/or not exactly known. We may then estimate a maximum difference between the crystal oscillator frequency and the kick-start output frequency, e.g. based on PVT (process-voltage-temperature) simulations.

[0093] Due to the difference in frequency between f.sub.xo, and f.sub.k, there will be gradual difference in phase over time between the kick-start output and the crystal oscillation. Each kick-start pulse will generate an oscillation at frequency f.sub.xo in the crystal with a phase related to that pulse, and thus a sequence of pulses will generate a corresponding number of oscillations, where each oscillation has a different phase shift compared to the oscillation generated by the first kick-start pulse. The resulting oscillation in the crystal will be a superposition of these oscillations, and at any time during the sequence of kick-start pulses, the phase of this resulting oscillation compared to the oscillation generated by the first kick-start pulse will be half the phase shift of the oscillation generated by the latest kick-start pulse. In other words, the phase difference between the oscillation generated by the latest kick-start pulse and the resulting (superpositioned) oscillation in the crystal will also be the half of this phase shift, and it will increase for each kick-start pulse. Therefore, there will be a maximum number of kick-start cycles, beyond which pulses will actually start to pull energy from the crystal rather than injecting energy.

[0094] From this, it can be understood that the maximum duration of the kick-start out-put corresponds to a maximum range of phases being 180 degrees. This is exemplified in FIG. 19, where each vector represents the phase of each kick-start output period relative to the resulting crystal oscillator output. Thus, vectors adding up constructively will obviously give net contribution whereas adding more phases outside the 180 degrees range will yield a lower total resultant.

[0095] In other words, the phase difference between any one of the kick-start pulses and the resulting crystal oscillation should not exceed 90 degrees or /2, which means that the phase shift of the oscillation generated by the latest kick-start pulse compared to the oscillation generated by the first kick-start pulse should not exceed 180 degrees or . The sign of this phase shift of course depends on whether the kick-start frequency f.sub.k is higher or lower than the crystal oscillator frequency f.sub.xo.

[0096] Assuming that the kick-start output and crystal oscillator are in phase at the beginning of the startup mode (t=0) the phase difference is simply given by 2|f.sub.k-f.sub.xo| t. At some point in time t.sub.max this phase difference will reach , and as described above, the kick-start output will then start pulling energy from the crystal rather than injecting it. In other words, maximum energy is injected for 2|f.sub.k-f.sub.xo|t.sub.max=. With N.sub.max being the number of kick-start output periods, this equation can also be written as |f.sub.k-f.sub.xo|N.sub.max/f.sub.k=, which means that N.sub.max=f.sub.k/(2|f.sub.k-f.sub.xo|).

[0097] Thus, the maximum number of kick-start pulses that can be used can be determined from the difference between the crystal oscillator frequency f.sub.xo and the kick-start frequency f.sub.k. In some embodiments, this frequency difference may be measured and used to determine the number of pulses. However, in many situations, the solution is to estimate a maximum difference between the crystal oscillator frequency and the kick-start output frequency, e.g. based on PVT (process-voltage-temperature) simulations, and then use this estimated maximum difference for determining the number of kick-start pulses.

[0098] As described above, when the kick-start output has a frequency different from the crystal oscillator frequency there will be a burst of a maximum number of consecutive kick-start output periods that will add up constructively. When the kick-start frequency is different but accurate it is proposed to use at least one such burst. After this burst, the kick-start oscillator should, as described above, be disconnected from the oscillator circuitry, because its phase difference from the oscillation in the crystal will be too large. However, if the kick-start oscillator continues running after this first burst, there will be subsequent time instances where kick-start output and crystal oscillator output are again sufficiently aligned to add up constructively, such that additional bursts can be injected. With reference to FIG. 19, it can be seen that at any time where the phase of the kick-start output compared to the oscillation of the crystal is in the right part of the figure, i.e. the phase difference is between /2 and /2, pulses can advantageously be injected. When the phase difference is in the left half of the figure, the kick-start circuit should be disconnected from the oscillator circuitry, because its phase difference from the oscillation in the crystal will be too large. The number of bursts to use will be limited by at least one of the accuracy of frequency difference between kick-start output and crystal oscillator and the energy injection required to achieve proper crystal oscillator operation within a specified time.

[0099] To illustrate the function of the kick-start solution described above, a number of simulations have been performed. FIG. 20 shows a diagram of a basic simulation setup with linear and ideal components aimed to demonstrate the proposed solution. The schematic diagram contains the model of the crystal (C.sub.o, C.sub.m, L.sub.m, R.sub.m), the capacitor C.sub.L for pulling control, and two voltage signals V_kick and V_kickbar (having opposite phase) for generating voltage square-waves during the startup mode to drive an ideal inverter that in turns draws current from the supply V.sub.DD. Further, a voltage signal V_start controls the duration of the startup mode by connecting the inverter output and disconnecting C.sub.L during startup, and disconnecting inverter output and connecting C.sub.L during normal operation. Values given are hypothetical. The resonance frequency of the crystal is roughly 460 MHz. Note that this model does not include the negative resistance generated by the cross-coupled core that is used to compensate for the losses.

[0100] Simulation results are given below for various numbers of periods N to demonstrate the limit in relation to frequency difference between f.sub.k and f.sub.xo. In the simulation results shown in FIGS. 21 to 23, the kick-start frequency is set to f.sub.k=440 MHz. With f.sub.xO=460 MHz and f.sub.k=440 MHz, the maximum number of kick-start pulses N can be calculated from the equation above to be 11.

[0101] FIG. 21 illustrates simulated waveforms of the motional branch current, i.e. the current through C.sub.m, and the output voltage, i.e. the kick-start pulses applied to the crystal, for N=5. Thus, the number of applied pulses is here less than the calculated maximum number of pulses. It can be seen that the oscillation current rapidly increases due to the energy injected into the crystal by the kick-start circuit. It is noted that since the model of FIG. 20 does not include the negative resistance generated by the cross-coupled core, the amplitude of the oscillation current decreases slightly after the kick-start phase, where in the real oscillator circuit it would increase slowly towards a stable value.

[0102] In FIG. 22, corresponding simulated waveforms are shown for N=10, i.e. the number of pulses is here close to the calculated maximum number 11. It can be seen that the oscillation current now increases to a higher value, but also that the effect of the last pulses close to the limit is less, because of the increased phase difference between the kick-start pulses and the resulting oscillation in the crystal.

[0103] In FIG. 23, corresponding simulated waveforms are shown for N=20, i.e. the number of pulses is here considerably higher than the calculated maximum number 11. It can be seen that the oscillation current after the 11.sup.th pulse now decreases again, because the kick-start pulses are now too much out of phase with the oscillation in the crystal, so here N is obviously too large. Regarding the effect of disconnecting the capacitor C.sub.L during the start-up phase, it is noted that C.sub.L is typically much larger than C.sub.0 of the crystal and can amount to several pF. For example, the dynamic current consumption of 5 pF toggled between 1V and 0V at 500 MHz becomes 2.5 mA and that is comparable to the power consumption of the crystal oscillator in steady-state.

[0104] FIG. 24 shows an example of a wireless communications system, in which a crystal oscillator circuit as described above can be used. Radio frequency signals are transmitted between two wireless communications devices, which are here exemplified by a base station 62 and a wireless terminal 63, such as a mobile phone, a machine-type communication (MTC) device, or a computer, a tablet device, or other device equipped with a cellular data modem. In the base station 62, an antenna 64 is connected to a transmitter 65 and a receiver 66, which are both connected to a signal processing unit 67. As illustrated, the base station 62 comprises a crystal oscillator circuit, e.g. the circuit 40 of FIG. 12, for providing a reference clock signal to the transmitter 65 and the receiver 66. Alternatively, there may be more than one crystal oscillator, e.g. one crystal oscillator for the transmitter 65 and one crystal oscillator for the receiver 66. Similarly, in the wireless terminal 63, an antenna 68 is connected to a transmitter 69 and a receiver 70, which are both connected to a signal processing unit 71. As illustrated, the wireless terminal 63 comprises a crystal oscillator circuit, e.g. the circuit 40 of FIG. 12, for providing a reference clock signal to the transmitter 69 and the receiver 70. Alternatively, there may be more than one crystal oscillator, e.g. one crystal oscillator for the transmitter 69 and one crystal oscillator for the receiver 70.

[0105] In other words, there is disclosed a crystal oscillator circuit 40; 44; 47 comprising a crystal X.sub.1; oscillator circuitry 11; 21; 31; 41 connected to said crystal X.sub.1 and configured to generate a crystal oscillation signal at an oscillation frequency; and a kick-start circuit 12; 42; 45; 48 configured to inject a number of pulses into said crystal during a start-up period of the crystal oscillator circuit. The oscillator circuitry 11; 21; 31; 41 comprises a first differential pair of transistors M.sub.1, M.sub.2 and is configured to operate in a selectable one of at least an oscillating mode and a start-up mode, wherein the first differential pair of transistors, in the oscillating mode, are cross-coupled so that a gate terminal of a first transistor M.sub.1 of the first differential pair is coupled to a drain terminal of a second transistor M.sub.2 of the first differential pair, and a gate terminal of the second transistor M.sub.2 of the first differential pair is coupled to a drain terminal of the first transistor M.sub.1 of the first differential pair, each one of said drain terminals of the first and second transistors of the first differential pair further being coupled to a terminal of said crystal X.sub.1 to generate said crystal oscillation signal at said oscillation frequency; and said kick-start circuit 12; 42; 45; 48, in the start-up mode, is configured to drive the gate terminals of said first and second transistors M.sub.1, M.sub.2 of the first differential pair with said number of pulses during said start-up period of the crystal oscillator circuit.

[0106] Oscillator circuitry with a differential pair of cross-coupled transistors allows the crystal oscillator circuit to operate at the desired high frequencies, and when start-up pulses are injected into the crystal by driving the gate terminals of the cross-coupled transistors in a start-up mode, the start-up time of the crystal oscillator circuit is substantially decreased, and parasitic oscillations in the crystal oscillator circuit can be avoided or at least considerably reduced. Decreased time for start-up leads to lower power consumption, which will be increasingly important as the frequency of the crystal oscillator approaches the GHz regime.

[0107] In some embodiments, the crystal oscillator circuit is further configured to disconnect, in the start-up mode, the gate terminal of the first transistor M.sub.1 of the first differential pair from the drain terminal of the second transistor M.sub.2 of the first differential pair, and the gate terminal of the second transistor M.sub.2 of the first differential pair from the drain terminal of the first transistor M.sub.1 of the first differential pair.

[0108] The oscillator circuitry may further comprise a second differential pair of transistors M.sub.3, M.sub.4, said second differential pair of transistors M.sub.3, M.sub.4 being complementary to the first differential pair of transistors M.sub.1, M.sub.2, wherein the second differential pair of transistors, in the oscillating mode, are cross-coupled so that a gate terminal of a first transistor M.sub.3 of the second differential pair is coupled to a drain terminal of a second transistor M.sub.4 of the second differential pair, and a gate terminal of the second transistor M.sub.4 of the second differential pair is coupled to a drain terminal of the first transistor M.sub.3 of the second differential pair, each one of said drain terminals of the first and second transistors of the second differential pair further being coupled to a terminal of said crystal X.sub.1 to generate said crystal oscillation signal at said oscillation frequency. The use of a complementary cross-coupled differential pair of transistors reuses the same current as the first cross-coupled pair of transistors to generate negative resistance in the circuit.

[0109] In this case, said kick-start circuit 42; 45; 48 may, in the start-up mode, be configured to drive the gate terminals of said first and second transistors M.sub.3, M.sub.4 of the second differential pair with said number of pulses during said start-up period of the crystal oscillator circuit, and the crystal oscillator circuit may further be configured to disconnect, in the start-up mode, the gate terminal of the first transistor M.sub.3 of the second differential pair from the drain terminal of the second transistor M.sub.4 of the second differential pair, and the gate terminal of the second transistor M.sub.4 of the second differential pair from the drain terminal of the first transistor M.sub.3 of the second differential pair.

[0110] In some embodiments, each transistor M.sub.2, M.sub.3, M.sub.4 of said differential pair of M.sub.1, transistors comprises a field effect transistor.

[0111] In some embodiments, said kick-start circuit 12; 42; 45; 48 comprises an oscillator dedicated to generating said number of pulses. In such case, the dedicated oscillator may be a free-running oscillator, and the free-running oscillator may be configured to be calibrated by being phase locked to said oscillator circuitry during a time period where the oscillator circuitry is operating in the oscillating mode. In this way, a kick-start circuit having a frequency close to the target frequency of the crystal oscillator can be achieved. Alternatively, the dedicated oscillator may be configured to be locked to an external reference frequency, which also ensures a good accuracy of frequency of the kick-start circuit.

[0112] When a capacitor C.sub.L is arranged in parallel to said crystal X.sub.1 for adjustment of said oscillation frequency when the oscillator circuitry is operating in the oscillating mode, the crystal oscillator circuit may further be configured to disconnect said capacitor C.sub.L from the crystal X.sub.1 in the start-up mode. When the load capacitance used for pulling control and tuning is disconnected from the crystal oscillator output terminals during the start-up, it can be avoided that this capacitance sinks a large amount of current foremost yielding significant dynamic power consumption, but also effectively lowering the voltage across the crystal and thereby slowing energy injection.

[0113] In some embodiments, the crystal oscillator circuit is further configured to determine said number of pulses in dependence of a difference in frequency between a frequency of said pulses and an oscillation frequency of an oscillation generated in said crystal X.sub.1 by injecting said pulses into said crystal X.sub.1. In this way an optimal number of pulses, and thus an optimal duration of the start-up mode, can be determined.

[0114] The crystal oscillator circuit may be configured to determine said number of pulses so that a phase difference between each one of said pulses and the oscillation signal generated in said crystal X.sub.1 by injecting that one and previous pulses of said number of pulses into said crystal X.sub.1 is between /2 and /2.

[0115] The crystal oscillator circuit may further be configured to inject at least a further number of pulses into said crystal X.sub.1 during a further start-up period of the crystal oscillator circuit, wherein a phase difference between pulses of said further start-up period and said crystal oscillation signal is between /2 and /2, said start-up periods being separated by a time period where said phase difference exceeds /2.

[0116] An electronic apparatus may comprise at least one crystal oscillator circuit 40 as described above. In this way, the apparatus benefits from the described advantages of the crystal oscillator circuit. The electronic apparatus may be a wireless communications device comprising a receiver or a transmitter for radio frequency signals. In one embodiment, the wireless communications device is a base station 62 for a wireless communications system. In another embodiment, the wireless communications device is a mobile phone 63 for use in a wireless communications system.

[0117] As mentioned, the invention further relates to a method of reducing the duration of a start-up period for a crystal oscillator circuit 40; 44; 47 comprising a crystal X.sub.1; and oscillator circuitry 11; 21; 31; 41 connected to said crystal X.sub.1 and configured to generate a crystal oscillation signal at an oscillation frequency, said oscillator circuitry comprising a first differential pair of transistors M.sub.1, M.sub.2, wherein the first differential pair of transistors, in an oscillating mode, are cross-coupled so that a gate terminal of a first transistor M.sub.1 of the first differential pair is coupled to a drain terminal of a second transistor M.sub.2 of the first differential pair, and a gate terminal of the second transistor M.sub.2 of the first differential pair is coupled to a drain terminal of the first transistor M.sub.1 of the first differential pair, each one of said drain terminals of the first and second transistors of the first differential pair further being coupled to a terminal of said crystal X.sub.1 to generate said crystal oscillation signal at said oscillation frequency; wherein the method comprises the step of injecting from a kick-start circuit 12; 42; 45; 48 a number of pulses into said crystal X.sub.1 during a start-up period of the crystal oscillator circuit, said pulses being injected by driving the gate terminals of said first and second transistors M.sub.1, M.sub.2 of the first differential pair with said number of pulses during said start-up period of the crystal oscillator circuit.

[0118] Oscillator circuitry with a differential pair of cross-coupled transistors allows the crystal oscillator circuit to operate at the desired high frequencies, and when a number of start-up pulses are injected into the crystal by driving the gate terminals of the cross-coupled transistors in a start-up mode, the start-up time of the crystal oscillator circuit is substantially decreased, and parasitic oscillations in the crystal oscillator circuit can be avoided or at least con- siderably reduced. Decreased time for start-up leads to lower power consumption, which will be increasingly important as the frequency of the crystal oscillator approaches the GHz regime.

[0119] Although various embodiments of the present invention have been described and shown, the invention is not restricted thereto, but may also be embodied in other ways within the scope of the subject-matter defined in the following claims.

Reducing Duration of Start-up Period for a Crystal Oscillator Circuit

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