IMAGE SENSOR

Abstract

A CCD image sensor of the type for providing charge multiplication by impact ionisation has an image area and a plurality of pixels. A separate multiplication register has a plurality of multiplication elements arranged to receive charge from the pixels of the image area. Each multiplication element comprises a sequence of electrodes operable to cause multiplication, the electrodes of each multiplication element being adjacent one another and non-overlapping. The non-overlapping arrangement may be manufactured by a CMOS process thereby providing a CCD image sensor with the advantages of CCD multiplication but using a CMOS manufacturing process.

Claims

1. A CCD image sensor of the type for providing charge multiplication by impact ionisation, comprising an image area having a plurality of pixels and a separate multiplication register having a plurality of multiplication elements arranged to receive charge from the pixels of the image area, each multiplication element comprising a sequence of electrodes operable to cause charge multiplication, wherein the electrodes of each multiplication element are adjacent one another and non-overlapping.

2. The CCD image sensor according to claim 1, wherein the electrodes are derived from a single layer.

3. The CCD image sensor according to claim 1, wherein the electrodes are formed by etching.

4. The CCD image sensor according to claim 1, wherein the electrodes and manufactured using a CMOS process.

5. The CCD images sensor according to claim 1, wherein the electrodes are derived from a single layer of polysilicon.

6. The CCD image sensor according to claim 1, wherein each multiplication element comprises a sequence of electrodes on a gate dielectric, wherein the gate dielectric is thinner than 20 nm.

7. The CCD image sensor according to claim 1, wherein the electrodes of each multiplication element have inter-electrode gaps that are narrower than 100 nm.

8. The CCD image sensor according to claim 1, wherein the pixels of the image area are arranged in rows and columns and comprising a single multiplication register arranged to receive charge from the pixels of the image area.

9. The CCD image sensor according to claim 1, wherein the pixels of the image area are arranged in rows and columns and comprising a plurality of multiplication registers, each multiplication register arranged to receive charge from a subset of the pixels of the image area.

10. The CCD image sensor according to claim 9, wherein each multiplication register is arranged to receive charge from a corresponding column of the image area.

11. The CCD image sensor according to claim 9, comprising charge to signal converters arranged to produce a signal from each multiplication register and an output multiplexer arranged to receive the signals and implemented to reduce the number of output connections.

12. The CCD image sensor according to claim 1, wherein the electrodes are on a front face of a substrate and the CCD image sensor is arranged for illumination on the back face thereof.

13. An apparatus comprising a CCD image sensor according to claim 1.

14. (canceled)

15. A camera comprising the CCD image sensor according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Some ways in which the invention may be performed are described in more detail by way of example with reference to the accompanying drawings, in which:

[0017] FIG. 1: is a schematic view of a known EMCCD imager having a multiplication register;

[0018] FIG. 2: is a schematic view of a cross section of a multiplication element of a multiplication register;

[0019] FIG. 3: shows voltage levels of a multiplication element;

[0020] FIG. 4: is a schematic diagram of a first arrangement embodying the invention;

[0021] FIG. 5: is a schematic diagram of a second arrangement embodying the invention;

[0022] FIG. 6: is a schematic diagram of a third arrangement embodying the invention;

[0023] FIG. 7 shows the measured electron multiplication gain of a device embodying the invention;

[0024] FIG. 8 shows the electron multiplication gain in a known device such as the e2v CCD97;

[0025] FIG. 9 shows a pixel according to an embodiment of the invention;

[0026] FIGS. 10a-c show the manufacturing steps in a known CCD process;

[0027] FIGS. 11a-b show the manufacturing steps in a CMOS process for implementing an embodiment of the invention; and

[0028] FIG. 12 shows an optical device embodying the invention.

DETAILED DESCRIPTION

[0029] An embodiment may be an image sensor, a semiconductor-based imaging device, a method of manufacturing a semiconductor-based image sensor or imager device, semiconductor image sensor modules, cameras and other optical devices including semiconductor image sensor modules.

[0030] The present disclosure describes an arrangement that significantly reduces the voltage required to achieve EM gain values compared to traditional EM CCDs. By using low voltage CMOS arrangements for EM elements the voltage level at the HV Gate can be reduced by a factor of at least 2, leading to the added advantage of a reduction of the power dissipation by a factor of at least 4.

[0031] In addition, the electron multiplication is realised outside the photosensitive area of the device, giving higher fill factor and improved quantum efficiency. This allows the photosensitive area to be optimised for only electro-optical performance and in particular for lower dark current. The electron multiplication provides a gain from input to output. Gain uniformity may also be improved in an embodiment due to the use of common gain elements per column or for the whole device. The number of EM elements is reduced in comparison with devices using EM per pixel, resulting in reduced power dissipation.

[0032] In a low voltage CMOS fabrication process, as used in an embodiment, the gate dielectric is much thinner than in traditional CCD technology; typically the CMOS gate dielectric is less than 20 nm thick while in EMCCDs it is usually more than 100 nm thick. For example, the dielectric thickness used may be 12.5 nm in a 5V CMOS process, but the dielectric breakdown voltage may be much higher than 5V. In 3.3V devices the dielectric may be 7 nm thick. In general, the thickness of dielectric in an embodiment is less than 20 nm.

[0033] In such a CMOS fabrication process normally a single polysilicon layer is used to manufacture the gates of the charge transfer structure, and the gaps between electrodes are obtained using deep-submicron etching. This process could achieve inter-electrode gaps below 100 nm. In contrast, traditional CCD technology uses multiple layers of polysilicon as gate electrodes. After each layer of polysilicon is deposited and patterned, its surface is thermally oxidised until a thin layer of silicon dioxide is grown. This oxide insulates any polysilicon layer from any subsequent polysilicon layers deposited on top of it, and forms the inter-electrode gap with the polysilicon serving as various electrodes. Usually, the inter-electrode gap created by polysilicon oxidation has thickness in the range 200 to 300 nm.

[0034] The effects of the thinner gate dielectric and narrower inter-electrode gaps combine to allow the generation of higher electric field at the same applied voltage (or generating higher electric field than possible in traditional designs), thus increasing the EM gain for the same applied voltage. Simulations indicate that the voltage applied to the HV Gate can be reduced by at least a factor of 2 while achieving the same EM gain.

[0035] FIG. 4 shows one possible architecture for the EM device in an image sensor embodying the invention using low voltage CMOS manufacturing process. This is similar to the traditional EM CCD architecture. This example is a full frame CCD architecture without a store section between the image and register, though a store region could be inserted in an embodiment if desired. The device is manufactured according to a CMOS process, an example of which is given later. An image area 41 comprises pixels arranged to receive illumination and to generate charge. After an illumination period, the charge in each pixel is clocked to a serial register 44 and then to a multiplication register 45. An output amplifier 46 then converts the amplified charge to an output signal.

[0036] Typically CCD processes do not have capability for integrating logic and amplifiers using complementary MOS devices. FIG. 5 and FIG. 6 show two further embodying architectures using column-parallel read-out. The high density output circuitry becomes possible by the use of deep-submicron CMOS process. FIG. 5 shows an arrangement of an image sensor having similar features as before, namely an image area 51 having pixels manufactured according to a CMOS process and arranged to generate charge. The charge is clockable as previously described, after an illumination period, to a plurality of multiplication registers 55 arranged as an electron multiplying area. In this example, each column of pixels in the image area 51 has a corresponding column of multiplication elements and a corresponding output amplifier 56.

[0037] FIG. 7 shows the measured EM gain in a prototype device embodying the invention using the described low voltage CMOS manufacturing process, and for comparison FIG. 8 shows the EM gain in an e2v CCD97, a typical representative EMCCD. Due to the higher electric fields possible in the CMOS device the required high voltage clock amplitude is reduced from 46V to 13.5V for the same gain of 1000. This reduction of operating voltages could reduce the power dissipation in the EM circuitry by a factor of 10 or more, as the power is proportional to the voltage squared.

[0038] FIG. 9 shows the dimensions of one multiplication element of an embodiment with a width of 10 m, which would be the column pitch in the devices shown in FIGS. 4 and 5.

[0039] FIGS. 10 and 11 show the steps in manufacturing a traditional CCD and a CMOS device, respectively. An explanation of these will assist in understanding the nature of a CCD embodying the invention but manufactured according to a CMOS process.

[0040] FIG. 10a shows the steps of a known CCD manufacturing process showing a silicon layer with gate dielectric deposited thereon. In step 1 a first level of polysilicon deposition is undertaken and in step 2 a required pattern is etched by photolithography. FIG. 10b shows an oxidation step at step 3 followed by a second polysilicon deposition step at step 4. Step 5 shows patterning of the second level polysilicon by photolithography. FIG. 10c shows the remaining steps of the process. Step 6 shows a second level polysilicon oxidation. Step 7 shows a third layer of polysilicon deposition and step 8 patterning of the third level by photolithography. Further layers of polysilicon may be used. Finally step 9 shows passivation of the device.

[0041] As can be seen from the steps shown in FIG. 10, four partially overlapping gate electrodes are formed by the combination of deposition and photolithography. The gates are all formed on a dielectric layer separating the gates from the underlying crystalline silicon.

[0042] FIGS. 11a and 11b show the steps in a CMOS manufacturing process as used to manufacture an image sensor embodying the invention. Initially crystalline silicon 110 with gate dielectric 111 thereon is provided. In step 1, polysilicon 112 is deposited on the gate dielectric. The process then differs from the previous CCD process at step 2 in that the gate electrodes 113 are formed by photolithography of the polysilicon layer 112 without the need for multiple deposition steps. Lastly, at step 3 a passivation process is undertaken. As can be seen, the process does not use multiple deposition steps, but a single deposition step for the electrode layer of polysilicon.

[0043] As discussed above, the embodiment is a CCD image sensor because charge is shifted from one element to another element to achieve transfer from an image area and subsequent multiplication prior to conversion to a signal. However, the techniques for creating the device are typically used to manufacture CMOS devices of the type having signal charge to voltage conversion within each image element.

[0044] An apparatus such as a camera or scientific apparatus embodying the invention is shown schematically in FIG. 12. A housing 120 contains a lens arrangement 121 which focuses received illumination onto an image sensor 122 of the type described in relation to the embodiment. Circuitry 123 is provided to receive signals from the image sensor 123 for subsequent processing.