COMPONENT WITH A THIN-LAYER COVERING AND METHOD FOR ITS PRODUCTION

Abstract

A component (B) comprising a carrier (TR), on which a functional structure (FS) is covered by a thin-layer covering (DSA) spanning across and resting on the carrier. On a planarization layer arranged above the thin-layer covering (DSA), a wiring level (M1, M2) is realized, which comprises structured conductor paths and which is connected via through-connections to the functional structure (FS).

Claims

1. A component (B) comprising a carrier (TR), a functional structure (FS) on the carrier (TR), a thin-layer covering (DSA) spanning across the functional structure (FS) and resting on the carrier, a planarization layer arranged above the thin-layer covering (DSA), a wiring level (M1, M2) applied onto the planarization layer, wherein the wiring level (VE) comprises structured conductor paths and is connected to the functional structure (FS) via through-connections.

2. The component according to claim 1, in which the wiring level (VE) comprises solderable connecting pads (AP) arranged on the planarization layer.

3. The component according to a preceding claim, in which the thin-layer covering (DSA) comprises several partial layers in which the partial layers comprise a mechanically stable layer and a sealing layer in which the mechanically stable layer encloses above the carrier a cavity, in which at least a portion of the functional structure is enclosed.

4. The component according to a preceding claim, wherein the functional structure (FS) is selected from: a MEMS structure, a micro-acoustic structure, an SAW structure, a BAN structure, or a GBAW structure.

5. The component according to any of the preceding claims, furthermore, comprising a connecting face (AF) arranged externally to the thin-layer covering on the carrier (TR) and connected both to the functional structure (FS) and, via a through-connection, to the wiring level (VE).

6. The component according to the preceding claim, in which the connecting faces (AF) and the solderable connecting pads (AP) are present in different numbers and/or have a different distribution and/or are switched in the respective horizontal positions.

7. The component according to any of the preceding claims, furthermore, comprising one or more circuit components on the planarization layer, which circuit components are connected to the functional structure (FS) and selected from inductances, capacitances, and resistances.

8. The component according to any of the preceding claims, in which a plurality of functional structures (FS) working with acoustic waves is respectively covered by a separate thin-layer covering (DSA) and connected to form an HF filter in which the connection of the functional structures (FS) to form an HF filter is at least partially realized in the wiring level.

9. A method for producing a component (B), comprising the steps: Providing a carrier (TR), Arranging a functional structure (FS) and connecting faces connected to it on a carrier (TR), Covering the functional structure (FS) with a thin-layer covering (DSA) and structuring of the thin-layer covering (DSA) (DSA) such that the connecting faces remain free of the thin-layer covering (DAS), Producing and structuring a planarization layer such that the connecting faces remain exposed or are exposed, Producing a structured wiring level on the planarization layer and connecting the wiring level to the connecting faces in an integrated manner.

10. The method according to the preceding claim, wherein a metal layer is deposited onto the planarization layer and structured in order to form the wiring level, and an electrically insulating layer is produced above the wiring level and structured such that exposed areas remain a solderable metallization is applied onto the exposed areas in order to produce solderable connecting pads.

11. The method according to a preceding claim, wherein the planarization layer is either already applied in a planar manner by a planarizing method or applied as an arbitrary, even non-planar, layer and subsequently planarized, wherein the planarization layer comprises a lacquer, a polymer, or another organic material.

12. The method according to a preceding claim, in which the production of the structured wiring level comprises the production of two metallic partial layers, of which a first one is applied onto the entire surface as a growth layer, wherein the structure of the wiring level is defined by means of a photoresist, and wherein the second metallic partial layer is carried out by means of layer thickness reinforcement of the growth layer in the areas free of photoresist, in which the growth layer is removed in the areas next to the structure of the wiring level.

13. The method according to a preceding claim, in which the solderable contact pads are produced by applying a solderable metal layer onto corresponding areas of the wiring level, wherein the definition of contact pads takes place by means of photolithography.

Description

EXEMPLARY EMBODIMENTS AND DESCRIPTION OF THE FIGURES

[0031] A method for producing a component according to the invention with a thin-layer covering and a wiring level is explained below with reference to the exemplary embodiments and the associated figures. The figures are used solely for a better understanding of the invention, and are, therefore, partially only schematic and not true to scale. For a better understanding, individual parts can be illustrated in an enlarged or scaled-down manner.

[0032] Shown are:

[0033] FIGS. 1A through 1E various method stages in the production known per se of a thin-layer covering,

[0034] FIGS. 2A to 2J various method stages in the production of a component according to the invention with a wiring level,

[0035] FIG. 3 a component according to the invention in a schematic top view.

[0036] FIGS. 1A to 1E show, by means of various schematic cross sections, various method stages of the method known per se for the production of a known component with traditional thin-layer covering. For this purpose, a functional structure FS, including supply lines and connecting faces AF, is initially produced on a carrier TR. The functional structures FS, for example, constitute transducer structures for an acoustic component, especially an SAW or BAW component.

[0037] Above the functional structures FS, a sacrificial layer OS is now applied and structured such that it defines the areas for the subsequent cavities underneath the thin-layer covering DSA. The sacrificial layer OS preferably comprises an easily structurable material, especially a lacquer layer.

[0038] Onto the entire surface of the structured sacrificial layer OS, a mechanically stable layer MSS is now applied, such as a SiO2 layer by means of sputtering or CVD. FIG. 1A shows the component at this method stage.

[0039] Subsequently, openings OE are produced in the mechanically stable layer MSS; through these openings, the sacrificial layer underneath the mechanically stable layer MSS can now be dissolved away. One or more openings OE can be provided for each provided cavity or for each thin-layer covering DSA. FIG. 1B shows the arrangement at this method stage.

[0040] In the next step, the openings OE are sealed using a sealing layer VS. The sealing layer VS is preferably applied onto the entire surface and subsequently structured, exposing the connecting faces AF as shown in FIG. 1C. The cavity is thus sealed in an air-tight manner.

[0041] The sealing layer VS is preferably an organic lacquer or a polymer.

[0042] FIG. 1D shows the arrangement after the production of a hermetic layer HS above the sealing layer VS as well as after the production of solderable connecting pads AP directly above the connecting faces AF on the surface of the carrier TR. The sequence for the production of the connecting pads AP and the hermetic layer HS can also be switched.

[0043] The hermetic layer HS is preferably a thick and electrically insulating layer, especially a silicon nitride layer.

[0044] FIG. 1E shows the connection of such a component provided with a thin-layer covering DSA by means of bumps BU, which are produced above and in contact with the solderable connecting pads AP. The bumps U can be stud bumps or solder bumps. In this known embodiment, the bumps must be sufficiently large and especially sufficiently high so that they project above the thin-layer covering DSA and still have a sufficient stand-off of the component relative to the circuit environment after the soldering of the component.

[0045] A method for the production of a component according to the invention with a thin-layer covering is specified below and explained in more detail using different method stages illustrated in FIGS. 2A to 2J.

[0046] FIG. 2A shows a component provided with a thin-layer covering DSA as can be obtained in a known method, for example according to FIG. 1C. Underneath the possibly multilayer thin-layer covering, functional structures of the component are embedded into a cavity. The functional structures are connected via supply lines (not shown) to connecting faces AF on the surface of the carrier. The connecting faces can consist of a traditional metallization as can be used for normal connecting lines on a component.

[0047] A planarization layer PS is now applied above this arrangement. This planarization layer comprises a lacquer, a polymer, or a different organic compound.

[0048] The planarization layer PS can be applied using different methods, such as by spin coating using spin-on materials having good planarization properties. It is also possible to laminate organic materials, especially thin films. This does not necessarily have to directly result in a planar surface. Rather, it is possible to apply a polymer or a lacquer in any manner onto the surface of the carrier TR and planarize it subsequently. The application can be carried out by imprinting, appliquing, or even via the gas phase, for example by means of PECVD or PVD.

[0049] The planarization process of a not completely planar organic layer can be carried out, for example, via chemical-mechanical planarization (CMP). The planarization layer is preferably applied or planarized such that it subsequently has local layer thickness deviations of less than 5 m. The thickness of the planarization layer is at least adjusted high enough for the thin-layer covering DSA to still be covered by a sufficient layer thickness.

[0050] In the next step, recesses AN of the planarization layer PS are produced. On the bottom of the recesses, the connecting faces AF on the surface of the carrier TR are exposed. The recesses can be defined and produced using photolithography. It is, for example, possible to apply a photomask onto the planarization layer PS and structure it. In the areas of the planarization layer PS not covered by the photomask, the planarization layer can be removed to produce the recesses AN, for example using a solvent or by means of etching. In doing so, wet and dry etching methods are possible.

[0051] The recesses AN can be produced in any arbitrary cross section, they must have a sufficiently large cross-sectional area in order to later use such recesses as a basis for a through-connection. FIG. 1C shows the arrangement at this method stage.

[0052] It is advantageous to use for the planarization layer PS a material that can be transformed in a curing process into a more resistant structure, toughening it in order for the planarization layer to remain on the component. In the uncured state, the structuring of the planarization layer is thereby also facilitated. Subsequently to the production of the recesses, the planarization layer PS can then be cured, for example by the effect of heat and/or radiation, for example using UV light. Subsequently, a treatment with a plasma can optionally be performed to remove not completely removed residues of the planarization layer PS from the recesses AN. For this purpose, a CF.sub.4- and O.sub.2-containing plasma is, for example, suitable.

[0053] In the next step, a thin metal layer M1 is applied onto the entire surface of the planarization layer such that it also contacts the side walls of the recesses An and the connecting faces AF exposed therein.

[0054] This metal layer M1 should be sufficiently tight so that it can serve as a growth layer for a subsequent thicker metallization. The metal layer M1 for the growth layer can be vapor coated, sputtered or produced using a metal-containing seed solution. FIG. 2D shows the arrangement at this method stage.

[0055] As shown in FIG. 2E, in the next step, a first resist layer R1 is applied and structured such that the conductor paths required for the execution of the wiring level and areas required for other metallic structures remain uncovered. This first resist layer R1 is subsequently used to reinforce, for example, by an electroless method or electroplating, the first metallization M1 by a second metal layer M2 in the exposed areas not covered by the resist layer. For this purpose, a copper layer can be applied galvanically, which is additionally covered by a nickel layer, if necessary.

[0056] The method is carried out until a sufficiently high layer thickness of the second metal layer M2 is achieved, which ensures a sufficient conductivity within the wiring level. In the recesses, the metallization consisting of a first and second metal layer M1, M2 now has electrical contact with the connecting faces AF, which in turn are connected to the functional structures underneath the thin-layer coverings DSA. On the surface of the planarization layer PS, the conductor paths for the wiring level and optionally also structures for integrated circuit components are now produced from the metallization. In this way, inductances in the form of meandering conductor paths or in the form of helical structures can, for example, be implemented. Capacitances can be implemented via adjacent metallization not electrically connected to one another. Resistances can be implemented via conductor paths with appropriately adjusted conductor path cross sections. FIG. 2F shows the arrangement at this method stage.

[0057] In the next step, the remaining first resist layer R1 is removed and the first metal layer M1 remaining thereunder is removed so that only the metallization in the area of the areas defined by the first resist layer R1 remains. The removal of the first metal layer M1 can be carried out, for example, by wet etching, wherein the adhesion of the thick metallization remains ensured in the other areas. The etching can be carried out such that the surface of the second metallization is roughened at the same time in order to ensure good adhesion to the subsequent connecting pad and the subsequent second resist mask R2 on the second metallization M2. It is, however, also possible to carry out the removal of the first metallization M1 and the roughening of the second metallization M2 in two different steps. FIG. 2G shows the arrangement at this method stage.

[0058] In the next step, a second resist mask R2 is produced in order to define the solderable connecting pads AP. As a resist for the second resist layer, a solder-resistant resist is used, since the second resist layer R2 can remain on the component. The second resist layer R2 has openings, in which the surface of the second metal layer M2 is exposed in the areas provided for the connecting pads AP.

[0059] The second resist layer R2 can be applied in a vacuum lamination process. The structuring takes place using photolithography, wherein either the resist itself is a photoresist or a normal resist structured with a photoresist layer. FIG. 2H shows the arrangement at this method stage.

[0060] In the next step, the surface of the second metal layer M2 exposed in the openings of the second resist layer R2 is now provided with a solderable layer in order to obtain the solderable connecting pads AP. Since they only require a small layer thickness, an electroless method can be used in this case. The exposed second metal layer M2 can, for example, be reinforced by a thin nickel and/or gold layer.

[0061] FIG. 2J shows the component at this method stage, at which it now is connected via its solderable connecting pads AP to an external circuit environment and can be soldered, for example, onto a circuit board.

[0062] The method shown in FIGS. 2A to 2J can be performed on the wafer level so that a plurality of components with a possibly even higher number of thin-layer coverings DSA can be processed in parallel.

[0063] Subsequently to the method stage shown in FIG. 2J, the components can be separated, for example by sawing along saw lines, in which no structure elements are present on the wiring level or on the surface of the carrier TR.

[0064] FIG. 3 shows a schematic top view of a possible structure of a component with the wiring level applied onto the planarization layer PS. On the carrier TR, functional structures of the component are arranged (not shown in the figure), whereby the structures are covered by thin-layer coverings DSA. Directly on the carrier, the functional structures are connected to connecting faces AF, which are produced in the form of a suitable metallization on the carrier surface. The carrier TR is covered across the entire surface of the thin-layer coverings by a planarization layer PS, which is only removed in the recesses AN above the connecting faces. There, the connecting faces AF are at least partially exposed.

[0065] The metallization M2 produced on the surface of the planarization layer PS at the same time serves to contact the connecting faces AF in the recesses AN.

[0066] In the areas intended for the external connection of the component, the metallization is completed by applying a solderable layer to form a solderable connecting pad.

[0067] Of the wiring level, FIG. 3 only shows the supply lines, which were formed by the metallization and which connect the connecting faces on the bottom of the recesses AN to the solderable connecting pads AP. In a real component, however, a plurality of such lines is produced in the wiring level, wherein individual connecting pads AP can be connected to a plurality of connecting faces AF and thus to a plurality of functional structures of the component. The wiring level then constitutes an interconnection of the functional structures and is not only used to ensure solderable connections for the functional structures.

[0068] Also not shown are the passive circuit components mentioned, which can be produced in the wiring level in a manner integrated into the metallization.

[0069] The method steps and component details explained using the figures only specify simple examples for the implementation of the invention so that a component according to the invention is not limited to the embodiments shown in the figures.

TABLE-US-00001 List of Terms and References B Component TR Carrier FS Functional structure VE1 First wiring level DSA Thin-layer covering Structured conductor paths AF Solderable connecting face AP Connecting pad SK Circuit components TS Partial layers MSS Mechanically stable layer VS Sealing layer HS Hermetic layer HR Cavity VE2 Second wiring level FIL HF filter MS Metal layer PL Electrically insulating layer FF Free areas UBM Solderable metallization for solderable connecting face