VOLTAGE-TO-CURRENT CONVERSION

Abstract

The present invention relates to circuitry for voltage-to-current conversion, and in particular to differential voltage-to-current conversion circuitry. Such circuitry is operable to receive a differential voltage input signal and output a corresponding differential current signal.

Claims

1. Differential voltage-to-current conversion circuitry, comprising: a power supply node for connection to a power supply voltage source; a first current path extending from the power supply node via a first intermediate node to a first load node to provide a first load current at the first load node for use by load circuitry when connected to the first load node, wherein a first supply-connection impedance is connected along the first current path between the poser supply node and the first intermediate node and a first load-connection impedance is connected along the first current path between the first intermediate node and the first load node; a second current path extending, in parallel with the first current path, from power supply node via a second intermediate node to a second load node to provide a second load current at the second load node for use by the load circuitry when connected to the second load node, wherein a second supply-connection impedance connected along the second current path between the power supply node and the second intermediate node and a second load-connection impedance is connected along the second current path between the second intermediate node and the second load node; a differential voltage input connected between the first and second intermediate nodes via first and second input-connection impedances, respectively, for application of a differential input voltage signal, supplied at the differential voltage input, between the first and second input-connection impedances so that the first and second load currents together define a differential current signal dependent on the differential input voltage signal; and control circuitry, wherein: the first and second load-connection impedances are implemented as first and second transistors, respectively; and the control circuitry configured to control a bias voltage provided to the gate or base terminals of the first and second transistors so as to control a gain relationship between the differential input voltage signal and the differential current signal.

2. The differential voltage-to-current conversion circuitry as claimed in claim 2, wherein the control circuitry is configured to control the bias voltage provided to the gate or base terminals of the first and second transistors based on a common-mode voltage indicative of a common mode between the source or emitter voltages of the first and second transistors.

3. The differential voltage-to-current conversion circuitry as claimed in claim 2, wherein the control circuitry comprises first and second measurement impedances connected in series between the source or emitter terminals of the first end second transistors, and is configured to obtain the common-mode voltage from a node between the first and second measurement impedances.

4. The differential voltage-to-current conversion circuitry as claimed in claim 3, wherein: the first and second measurement impedances are implemented as resistors; or the first and second measurement impedance have the same impedance as one another.

5. The differential voltage-to-current conversion circuitry as claimed in claim 2, wherein the control circuitry configured to control the bias voltage provided to the gate or base terminals of the first and second transistors based on a difference between the common-mode voltage and a target voltage.

6. The differential voltage-to-current conversion circuitry as claimed in claim 1, where the control circuitry is configured to control the bias voltage provided to the gate or base terminals of the first and second transistors such that the first and second load-connection impedances associated with the first and second transistors, respectively, are lower in impedance than the impedances of the first and second supply-connection impedances, respectively.

7. The differential voltage-to-current conversion circuitry as claimed in claim 1, comprising a first current sink connected to the first load node so as to draw a first sink current from the first load node, and a second current sink connected to the second load node so as to draw a second sink current from the second load node.

8. The differential voltage-to-current conversion circuitry as claimed in claim 7, wherein: the first and second load currents comprise respective component currents of the differential current signal superimposed on a load bias current; the first and second current sinks are controllable current sinks; and the control circuitry is configured to control the load bias currents by controlling the first and second sink currents.

9. The differential voltage-to-current conversion circuitry as claimed in claim 7, wherein: the control circuitry is configured to control the first and second sink currents so as to regulate the load bias currents at a target bias current value, or so as to compensate for changes in the drain or collector currents of the first and second transistors due to changes in the bias voltages provided to the gate or base terminals of the first and second transistors.

10. The differential voltage-to-current conversion circuitry as claimed in claim 9, wherein the control circuitry is configured to adjust the target bias current value based on a control input signal.

11. The differential voltage-to-current conversion circuitry as claimed in claim 1, wherein: the first and second supply-connection impedances are implemented as resistors; or the first and second supply-connection impedances have the same impedance as one another; or the first and second input-connection impedances are implemented as resistors; or the first and second input-connection impedances have the same impedance as one another.

12. Analogue-to-digital conversion circuitry operable to generate a digital output signal based upon an analogue input differential current signal, wherein: the analogue-to-digital conversion circuitry comprises the differential voltage-to-current conversion circuitry of claim 1; and the differential voltage-to-current conversion circuitry is configured to generate the input differential current signal as said differential current signal dependent on the differential input voltage signal.

13. Integrated circuitry, comprising the differential voltage-to-current conversion circuitry of claim 1.

14. The integrated circuitry of claim 13, wherein the integrated circuit is an IC chip.

15. Integrated circuitry comprising the analogue-to-digital conversion circuitry of claim 12.

16. The integrated circuitry of claim 15, wherein the integrated circuitry is an IC chip.

Description

[0035] Reference will now be made, by way of example only, to the accompanying Figures, of which:

[0036] FIG. 1A, considered above, is a schematic circuit diagram of a multiphase current-mode sampler;

[0037] FIG. 1B, is a schematic circuit diagram of a multiphase current-mode sampler corresponding to FIG. 1A but using PMOS transistors;

[0038] FIG. 2, considered above, shows schematic waveforms useful for understanding the sampler of FIG. 1A;

[0039] FIG. 3, considered above, is a schematic circuit diagram of an example implementation of the FIG. 1A sampler;

[0040] FIG. 4 is a schematic diagram of differ voltage-to-current conversion circuitry embodying the present invention;

[0041] FIG. 5 is an equivalent circuit diagram of the conversion circuitry of FIG. 4;

[0042] FIG. 6A is a schematic diagram useful for understanding one way of regulating the bias current in FIG. 4;

[0043] FIG. 6B is a schematic diagram useful for understanding one way of biasing the current sinks in FIG. 4;

[0044] FIG. 7 is a flow diagram of an example method useful for understanding the operation of the logic unit of FIG. 6B; and

[0045] FIG. 8 is a schematic diagram of a circuitry system comprising the FIG. 4 circuitry.

[0046] FIG. 4 is a schematic diagram of differential voltage-to-current conversion circuitry 200 shown receiving a differential input voltage signal and outputting a corresponding differential current signal to load circuitry 300.

[0047] The conversion circuitry 200 is shown effectively drawing the current from a power supply voltage source VDDH (VDD High) with that current being sinked to a ground (GND) power supply voltage source via the load circuitry 300 (which has its own supply voltage source VDDL or VDD Low, where VDDH>VDDL). However, the reverse situation is also possible, with the current effectively flowing down from VDD (e.g. VDDH) through the load circuitry 300 and then through the conversion circuitry 200.

[0048] This latter case may indeed seem more appropriate given the direction of current flow through the tail nodes 60 and 66 from the switching transistors 58 and 64 in the sampler 42 of FIG. 1A.

[0049] However, equally, the sampler 42 general configuration could provided effectively the other way up as shown in FIG. 1B by way of sampler 42a which corresponds to sampler 42. Sampler 42a sinks currents at the corresponding tail nodes 60a and 66a from the conversion circuitry 200 and passes them through the corresponding switching transistors 58a and 64a towards ground (GND) (being the case which aligns with that depicted in FIG. 4). The sampler 42a receive currents at the tail nodes 60a and 66a from the FIG. 4 conversion circuitry 200 (nodes 206 and 210) and passes them through the switching transistors 58a and 64a towards the ADC's sampling capacitors (not shown) effectively serving as a virtual GND.

[0050] It will thus be understood that the sampler 42aand ADC circuitry comprising the sampler 42amay serve as the load circuitry 300. As such, the conversion circuitry 200 may be considered front-end circuitry for the sampler 42a and ADC circuitry comprising the sampler 42a. The present disclosure will be understood accordingly.

[0051] The conversion circuitry 200 comprises a first (e.g. plus) current path extending from a power supply voltage node 202 at VDDH (VDD High) via a first intermediate node 204 to a first load node 206 to provide a first load current I.sub.L1 at the first load node 206 for use by the load circuitry 300 when it is connected to the first load node 206 as in FIG. 4. The conversion circuitry 200 also comprises a second (e.g. minus) current path extending, in parallel with the first current path, from the power supply voltage node 202 via a second intermediate node 208 to a second load node 210 to provide a second load current I.sub.L2 at the second load node 210 for use by the load circuitry 300, again when it is connected to the second load node 210 as in FIG. 4.

[0052] The first and second load currents I.sub.L1 and I.sub.L2 may thus be considered as plus and minus component currents of a differential current signal provided by the conversion circuitry 200 to the load circuitry 300.

[0053] A first supply-connection impedance 212 is connected along the first current path between the power supply node 202 and the first intermediate node 204, and a first load-connection impedance 214 is connected along the first current path between the first intermediate node 204 and the first load node 206. Similarly, a second supply-connection impedance 216 is connected along the second current path between the power supply node 202 and the second intermediate node 208, and a second load-connection impedance 218 is connected along the second current path between the second intermediate node 208 and the second load node 210.

[0054] The first and second supply-connection impedances 212 and 216 are implemented as resistors having resistances R.sub.B1 and R.sub.B2, respectively. The first and second-connection impedances 214 and 218 are both implemented as transistors, in this case as PMOS MOSFETs M1 and M2, respectively, in a common gate configuration so that they present input impedances Z.sub.G1 and Z.sub.G2, respectively, which can be controlled by gate bias voltages V.sub.BIAS1 and V.sub.BIAS2, respectively. Optional smoothing capacitors are shown at their gate terminals. The bias voltages are bias voltages in the sense that they are stable or effectively DC voltages, independent of the differential input voltage signal Vindiff. It will become apparent that, although not necessary, the transistors 214 and 218 are configured (e.g. in terms of transistor size) in the same way as one another and are controlled in the same way (e,g. with V.sub.BIAS=V.sub.BIAS2) so that Z.sub.G1=Z.sub.G2.

[0055] A differential voltage input 220 is connected between the first and second intermediate nodes 204 and 208 via first and second input-connection impedances 222 and 224, respectively, for application of a differential input voltage signal Vindiff, supplied at the differential voltage input 220, between the first and second input-connection impedances 222 and 224 as shown in FIG. 4. Thus, the first and second load currents I.sub.L1 and I.sub.L2, which define the differential current signal, are dependent on the differential input voltage signal Vindiff. The first and second input-connection impedances 222 and 224 are implemented as resistors having resistances R.sub.O1 and R.sub.O2, respectively.

[0056] Looking at FIG. 4, it is assumed that bias currents I.sub.B1 and I.sub.B2 flow through resistors 212 and 216, respectively, that current I.sub.S flows from intermediate node 208 to intermediate node 204 dependent on the differential input voltage signal Vindiff, that signal currents I.sub.SIG1 and I.sub.SIG2 flow through transistors 214 and 218, respectively, and that currents I.sub.L1 and I.sub.L2 are provided at load nodes 206 and 210, respectively. The bias currents are bias currents in that they are stable or DC currents, independent of the differential input voltage signal Vindiff. Further, sink currents I.sub.SK1 and I.sub.SK2 (to be described later) are drawn from the drain terminals of the transistors 214 and 218, respectively. Thus, I.sub.SIG1=I.sub.B1+I.sub.S and I.sub.SIG2=I.sub.B2I.sub.S. Further, I.sub.L1=I.sub.SIG1I.sub.SK1; and I.sub.L2=I.sub.SIG2I.sub.SK2.

[0057] Control circuitry 230 is provided to control the bias voltages V.sub.BIAS1 and V.sub.BIAS2, since this has the effect of controlling the gain relationship between the differential input voltage signal Vindiff and the differential current signal. In this regard, controlling the bias voltages V.sub.BIAS1 and V.sub.BIAS2 controls the impedance values Z.sub.G1 and Z.sub.G2, respectively. The significance of this can be better appreciated through consideration of FIG. 5, which presents an equivalent circuit diagram 200-E of the conversion circuitry 200 of FIG. 4.

[0058] In FIG. 5, like components are denoted with like reference signs for ease of comparison with FIG. 4, and duplicate description is omitted. For simplicity, and symmetry/balance in the operation, it is assumed in FIGS. 4 and 5 that the first and second current paths are configured in the same way as one another, and in particular that R.sub.B1=R.sub.B2=R.sub.B, R.sub.O1=R.sub.O2=R.sub.O, and that Z.sub.G1=Z.sub.G2=Z.sub.G(in terms of their common-mode value). Thus, it is also assumed that I.sub.B1=I.sub.B2=I.sub.B. It is also assumed that I.sub.SK1=I.sub.SK2=I.sub.SK.

[0059] As an overview, the front-end circuitry (conversion circuitry 200) exhibits highly linear voltage-to-current conversion, highly efficient signal power conversion by means of highly-controlled input impedance, direct signal current feedthrough from the first and second current paths to the subsequent load circuitry (e.g. through the switching transistors 58 and 64 of the sampler 42), and adjustable gain of the swing of the differential input voltage signal Vindiff to the swing of the differential current signal.

[0060] Looking at FIG. 5, Vindiff is the differential input voltage signal applied o the circuit via input-connection resistors 222 and 224 to the first current path (plus or P-branch) and the second current path (minus or N-branch) as in FIG. 4. In order to maximize the effective signal current i.sub.S, the active stage input impedance Z.sub.G (i.e. associated with the transistors 214 and 218) is dimensioned to be much smaller than the bias resistance R.sub.B through which the effective bias current i.sub.S flows. Furthermore it is possible to vary the loop current ratio i.sub.S/i.sub.B and therefore the gain of the transfer function i.sub.S=f(Vindiff) can be adjusted.

[0061] The transfer function calculates to:

[00001]$i_s=\frac{R_B}{Z_G+R_B}.Math.\frac{\mathrm{Vindiff}}{R_0+\frac{R_B.Math.Z_G}{R_B+Z_G}}$

[0062] It can be appreciated that if Z.sub.G<<R.sub.B, then the transfer function simplifies to:

[00002]$i_s=\frac{\mathrm{Vindiff}}{R_0+Z_G}$

[0063] Varying impedance Z.sub.G then leads to slight adjustments of the gain of the transfer function.

[0064] In order to realize a low impedance Z.sub.G in FIG. 4, the transistors 214 and 218 (M1, M2) form a common gate stage. This stage is biased and dimensioned in a way to have a very low input impedance (i.e. Z.sub.G<<R.sub.B) and a very high output impedance providing the subsequent load circuitry 300 with a bias current on which is superimposed a differential signal current (the two together constituting the current componentsi.e. the load currentsof the overall differential current signal). This current is highly proportional to the differential input voltage signal Vindiff. Therefore the subsequent load circuitry 300 can be treated low-ohmic and it does not affect signal power-to-current conversion.

[0065] The impedance Z.sub.G1/gm proportional to 1/I.sub.D, where I.sub.D is the drain current and gm is the transconductance of the transistors. Thus, the impedance Z.sub.G can be controlled by controlling the common mode value of the drain current I.sub.D (effectively by controlling the bias current I.sub.B), i.e. by controlling the gate-source voltages of the transistors 214 and 218 by controlling the bias voltages V.sub.BIAS1 and V.sub.BIAS2 as mentioned above. In the present embodiment, the bias current I.sub.B (recall that I.sub.B1=I.sub.B2=I.sub.B in FIG. 4) is regulated by means of common gate bias V.sub.BIAS (recall that V.sub.BIAS1=V.sub.BIAS2=V.sub.BIAS in FIG. 4) using bias circuitry containing a voltage regulator and current DAC (as considered later in connection with FIG. 6A).

[0066] Furthermore Z.sub.G=1/gm can be adjusted'by programmable or other control of the bias current I.sub.B (i.e. by adjusting the V.sub.BIAS gate signals) while keeping the output signal current unaffected by means of adding programmable/controllable current sinks 232 and 234 to draw sink currents I.sub.SK1 and I.sub.SK2 (recall that I.sub.SK1=I.sub.SK2=I.sub.SK in FIG. 4) at the drain terminals of the transistors 214 and 218 as shown in FIG. 4. The current sinks 232 and 234 may then be biased (controlled, e.g. being programmable) by way of control signals SINK1 and SINK2 (assume that SINK1=SINK2=SINK), i.e. such that the difference between the bias current 1B and the sink current I.sub.SK (being I.sub.L) is regulated (e.g. unaffected by changes in the bias current I.sub.B). This regulation can be done in an automatic control loop, as considered later in connection with FIGS. 6B and 7. The control may also be such that the value of the difference between the bias current I.sub.B and the sink current I.sub.SK can be varied to vary the amount of current supplied to the load circuitry 300, for example to optimize the operation of the load circuitry 300. This will also be considered later in connection with FIGS. 6B and 7.

[0067] Returning to FIG. 4, the control circuitry 230 is configured to receive a control signal CONTROL, and based on that signal to generate the control signals V.sub.BIAS1, V.sub.BIAS2, SINK1 and SINK2. The control circuitry 230 is also configured to receive a common-mode voltage V.sub.CM being representative of the common-mode value of the source voltages of the transistors 214 and 218. Measurement impedances 240 and 242 are connected in series between the source terminals 244 and 246 of the transistors 214 and 218, respectively, and the V.sub.CM signal is taken from a node 248 between the measurement impedances 240 and 242. The measurement impedances 240 and 242 are implemented as resistors having resistances R.sub.M1 and R.sub.M2, respectively. It is assumed that R.sub.M1=R.sub.M2.

[0068] FIG. 6A is a schematic diagram which, as mentioned above, is useful for understanding one way of regulating the bias current I.sub.B (recall that I.sub.B1=I.sub.B2=I.sub.B in FIG. 4) by means of common gate bias V.sub.BIAS (recall that V.sub.BIAS1=V.sub.BIAS2=V.sub.BIAS in FIG. 4) using bias circuitry.

[0069] For ease of understanding, parts of the conversion circuitry 200 containing the transistors 214 and 218 are presented, with the other parts of the conversion circuitry 200 being omitted for simplicity. A part 230-A of the control circuitry 230 is shown, comprising a current DAC (Digital-to-Analogue Converter) or DAC 402, a resistor 404 and a differential amplifier 406 (e.g. an operational amplifier).

[0070] The IDAC 402 is connected in series with the resistor 404 between VDD (e.g. VDDH) and GND to form a potential divider arrangement. The DAC 402 is controlled by part of the (digital) control signal CONTROL to cause a current I.sub.PD1 to flow through the resistor 404 such that a desired reference voltage Vref1 is produced at a node 408 along the potential divider between the IDAC 402 and the resistor 404.

[0071] The differential amplifier 406 is connected to receive the reference voltage Vref1 and the common-mode voltage V.sub.CM at its input terminals, and to output the common gate bias V.sub.BIAS based upon a difference between the reference voltage Vref1 and the common-mode voltage V.sub.CM. The differential amplifier 406 controls or regulates the common gate bias V.sub.BIAS such that it tends towards the reference voltage Vref1 at which the difference between the reference voltage Vref1 and the common-mode voltage V.sub.CM is minimized. This has the effect of regulating the bias current I.sub.B. The control signal CONTROL can thus be adjusted to adjust the reference voltage Vref1 and therefore the bias current I.sub.B. This enables digital (programmable) control of the bias current I.sub.B.

[0072] FIG. 6B is a schematic diagram which, as mentioned above, is useful for understanding one way of biasing the current sinks 232 and 234 by way of control signals SINK1 and SINK2 (assume that SINK1=SINK2=SINK) such the sink current I.sub.SK compensates for changes in the bias current I.sub.B, i.e. such that the difference between the bias current I.sub.B and the sink current I.sub.SK is regulated (e.g. unaffected by changes in the bias current I.sub.B). As also mentioned above, the control may be such that the value of the difference between the bias current I.sub.B and the sink current I.sub.SK can be varied to vary the amount of current supplied to the load circuitry 300, for example to optimize the operation of the load circuitry 300.

[0073] For ease of understanding, parts of the conversion circuitry 200 containing the current sinks 232 and 234 are presented, with the other parts of the conversion circuitry 200 being omitted for simplicity. A part 230-B of the control circuitry 230 is shown, comprising an IDAC 502, a resistor 504 and a logic unit 506 (which may be implemented as a processor executing a computer program).

[0074] The IDAC 402 is connected in series with the resistor 404 between VDD (e.g. VDDH) and GND to form a potential divider arrangement. The IDAC 502 is controlled by part of the (digital) control signal CONTROL to cause a current I.sub.PD2 to flow through the resistor 404 such that a desired reference voltage Vref2 is produced at a node 508 along the potential divider between the IDAC 502 and the resistor 504.

[0075] The logic unit 506 is connected to receive the reference voltage Vref2, the common-mode voltage V.sub.CM and the common gate bias V.sub.BIAS (generated by part 230-A of the control circuitry 230) at its input terminals, and to output the control signal SINK based on those input signals.

[0076] The common-mode voltage V.sub.CM and the common gate bias V.sub.BIAS together give a measure of the common-mode gate-source voltage V.sub.GS of the transistors 214 and 218, as indicated in FIG. 6B. The common gate bias V.sub.BIAS itself may also be considered a measure of the common-mode gate-source voltage V.sub.GS of the transistors 214 and 218 in which case the common-mode voltage V.sub.CM need not be supplied to the logic unit 506. The measure of the common-mode gate-source voltage V.sub.GS of the transistors 214 and 218 is taken as a measure of the bias current I.sub.B (i.e. the common mode drain current I.sub.D). The reference voltage Vref2 is taken as a measure of a target bias current I.sub.T (i.e. a target common mode drain current I.sub.D). The logic unit 506 then adjusts the control signal SINK so that the bias current I.sub.B tends towards or is regulated at the target bias current I.sub.T.

[0077] The control signal CONTROL can thus be adjusted to adjust the reference voltage Vref2 and therefore the target bias current I.sub.T. This enables digital (programmable) control of the target bias current I.sub.T, and thus of the difference between the bias current I.sub.B and the sink current I.sub.SK. Thus, if the control signal CONTROL is maintained the same in respect of the target bias current I.sub.T, then the difference between the bias current I.sub.B and the sink current I.sub.SK is regulated to that value. By adjusting the control signal CONTROL in respect of the target bias current I.sub.T, i.e. adjusting the reference voltage Vref2, the control may be such that the value of the difference between the bias current I.sub.B and the sink current I.sub.SK can be varied to vary the amount of current supplied to the load circuitry 300.

[0078] Incidentally, although the bias current I.sub.B here is defined as that following through the transistors 214 and 218 (i.e. prior to the drawing of current I.sub.SK by the current sinks 232 and 234), there could also be considered to be a load bias current I.sub.BL which forms part of the load currents I.sub.L, where I.sub.BL=I.sub.BI.sub.SK. Thus, it could be considered that the control based on Vref2 serves to control the sum of the load bias current I.sub.BL and the sink current I.sub.SK.

[0079] FIG. 7 is a flow diagram of example method 600 useful for understanding the operation of the logic unit 506 and in addition takes into account a possible logic operation which is more sophisticated than the corresponding operation of the differential amplifier 406 (it will be appreciated that the amplifier 406 could be replaced with a logic unit operating in accordance with the relevant steps of method 600). Method 600 has steps S2 to S20.

[0080] In overview, method 600 is a two-step DC regulation scheme, comprising overall Steps 1 and 2 as indicated. Step 1 (corresponding to the operation in FIG. 6A) is for optimization of the input impedance Z.sub.G by adjustment of bias current I.sub.B (by adjusting the V.sub.BIAS gate signals) through control of target value I.sub.BT. Step 2 (corresponding to the operation in FIG. 6B) if for optimization of the DC load current I.sub.L (which is I.sub.L1, I.sub.L2 in FIG. 4 and shown as I.sub.LOAD in FIG. 7) with respect to a maximum voltage range V.sub.CapDC on a sampling capacitor C.sub.Load by adjustment of sink current I.sub.SK to a target value of the load current I.sub.LoadT.

[0081] Here, the sampling capacitor C.sub.Load may be consider to be at the end of each of the paths shown in FIG. 1B (e.g. to be charged up by the current IOUT.sub.A within the sampling frequency fSampling to values V.sub.CapDCsee below).

[0082] In step S2, a value of the target bias current I.sub.BT is set based on the reference voltage Vref1 (see FIG. 6A) to optimize input impedance Z.sub.G. The method then proceeds to step S4 in which the target sink current I.sub.SKT is set based on Vref2 (see FIG. 6B) to optimize operating range on sampling capacitor C.sub.LOAD. Two constraints exist to set this current:

[0083] Constraint 1: I.sub.Load,min=I.sub.L1,min, I.sub.L2,min>0 (refer to FIG. 4)

[0084] Constraint 2: V.sub.CapDC<VDDL (maximum charge on sampling capacitor C.sub.Load)

[0085] This leads to the following condition for the target sink current I.sub.SKT:

I.sub.BT+I.sub.S.maxVDDL*fSampling*C.sub.Load<I.sub.SKT<I.sub.BTI.sub.S.max

where:

[0086] I.sub.S.max is the maximum signal DC current;

[0087] V.sub.CapDC is the voltage on the sampling capacitor C.sub.LOAD;

[0088] C.sub.LOAD is the sampling capacitor within the load circuitry 300, which is charged to a target DC voltage of V.sub.CapDC within the sampling time 1/fSampling; and

[0089] fSampling is the sampling frequency.

[0090] The method then proceeds to step S6 in which the existing bias current I.sub.B is measured based on V.sub.GS. Recall that the common-mode voltage V.sub.CM and the common gate bias V.sub.BIAS together give a measure of the common-mode gate-source voltage V.sub.GS of the transistors 214 and 218, as indicated in FIG. 6B. The method then proceeds to step S8.

[0091] In step S8 it is determined whether the existing bias current I.sub.B is greater than the target bias current I.sub.BT. If it is (step S8, I.sub.B>I.sub.BT), the method proceeds to step S14. Otherwise (step S8, I.sub.B<I.sub.BT), the method proceeds to step S16. In step S14 the V.sub.BIAS1,2 signals are controlled to both decrease the bias current I.sub.B to or towards the target value I.sub.BT. In step S16 the V.sub.BIAS1,2 signals are controlled to both increase the bias current I.sub.B to or towards the target value I.sub.BT.

[0092] If the measured value I.sub.B equals the target value I.sub.BT the method proceeds with step S10. The correct value of I.sub.B is desireable to optimize the input impedance of Z.sub.G1, Z.sub.G2.

[0093] In step S10 the existing load current I.sub.LOAD (I.sub.L) feeding load capacitors in the subsequent load circuitry 300 (ADC stage) is measured. The method then proceeds to step S12.

[0094] In step S12 it is determined whether the existing load current I.sub.LOAD is greater than the target load current I.sub.LoadT. If it is (step S12, I.sub.LOAD>I.sub.LoadT), the method proceeds to step S18. Otherwise (step S12, I.sub.LOAD<I.sub.LoadT), the method proceeds to step S20. In step S18 the SINK signals are controlled to increase the sink currents I.sub.SK to bring the load currents I.sub.LOAD to or towards the target value I.sub.LoadT. In step S20 the SINK signals are controlled to decrease the sink currents I.sub.SK to bring the load currents I.sub.LOAD to or towards the target value I.sub.LoadT. If the measured value I.sub.LOAD equals the target value I.sub.LoadT the method ends. The correct value of I.sub.LOAD is desireable to optimize the operating voltage range on the sampling capacitor C.sub.LOAD.

[0095] Either way, the method 600 then continues until operation is stoppedfor example if it is determined that the V.sub.BIAS and SINK signals have optimal values which need not be changed for the time being. Thus, the method 600 may be run from time to time. The logic unit 506 (along with a corresponding unit replacing amplifier 406) may be implemented in software running on a processor or in analogue circuitry.

[0096] FIG. 8 is a schematic diagram of a circuitry system 700, comprising the conversion (or front-end) circuitry 200 and the load circuitry 300 coupled together as in FIG. 4.

[0097] Thus, the conversion circuitry 200 receives a differential input voltage signal Vindiff and outputs a corresponding differential current signal as the input differential current signal Iindiff for the load circuitry 300.

[0098] As indicated in FIG. 8, the load circuitry 300 may be ADC circuitry configured based on the sampler 42a (see FIG. 1B) and explained in more detail in EP-A1-2211468 to generate a digital output signal as shown in FIG. 8 based on the input differential current signal Iindiff. Thus, the circuitry system 700 could be referred to as ADC circuitry. Further, the conversion (or front-end) circuitry 200 and the load circuitry 300 could both be implemented as integrated circuitry, provided for example on an IC chip. Thus, the circuitry system 700 could be referred to as integrated circuitry, and may be provided on or as a single IC chip.

[0099] It will incidentally be appreciated that the MOSFET or FET transistors 214 and 218 could instead be BJTs, and the present disclosure will be understood accordingly.

[0100] Circuitry of the present invention may be implemented as integrated circuitry, for example on an IC chip such as a flip chip. The present invention extends to integrated circuitry and IC chips as mentioned above, circuit boards comprising such IC chips, and communication networks (for example, Internet fiber-optic networks and wireless networks) and network equipment of such networks, comprising such circuit boards.

[0101] In any of the above method aspects, the various features may be implemented in hardware, or as software modules running on one or more processors. Features of one aspect may be applied to any of the other aspects.

[0102] The invention also provides a computer program or a computer program product for carrying out any of the methods described herein, and a computer readable medium having stored thereon a program for carrying out any of the methods described herein. A computer program embodying the invention may be stored on a computer-readable medium, or it could, for example, be in the form of a signal such as a downloadable data signal provided from an Internet website, or it could be in any other form.

[0103] Further embodiments may be provided within the spirit and scope of the present invention as disclosed herein.