Wide Band-Gap II-VI Heterojunction Solar Cell for Use In Tandem Structure

Abstract

A photovoltaic solar cell comprises a thin silicon or silicon dioxide substrate. The photovoltaic solar cell also comprises a first layer over said substrate. The first layer comprises tellurium (Te) and one or more of cadmium (Cd) and zinc (Zn). Additionally, the first layer is doped p-type. The photovoltaic solar cell also comprises a second layer adjacent to the first layer. The second layer comprises Te and two or more of Cd, Zn, magnesium (mg), and selenium (Se). The photovoltaic solar cell also comprises a third layer adjacent to the second layer. The third layer comprises Zn and one or more of Cd, Se, and Sulphur (S). The third layer is doped n-type.

Claims

1.-13. (canceled)

14. A multi-junction photovoltaic system, comprising: a photovoltaic device comprising an p-n junction and a Group IV material, wherein said photovoltaic device produces electricity upon exposure to light; a first layer over said photovoltaic device, wherein said first layer comprises tellurium (Te) and one or more of cadmium (Cd) and zinc (Zn), and wherein said first layer is doped p-type; a second layer adjacent to said first layer, wherein said second layer comprises three or more of Cd, Zn, magnesium (Mg), selenium (Se), and Te; and a third layer adjacent to said second layer, wherein said third layer comprises Zn and one or more of Cd, Se, and sulphur (S), and wherein said third layer is doped n-type.

15. The multi junction photovoltaic system of claim 14, wherein said first layer is ZnTe.

16. The multi junction photovoltaic system of claim 14, wherein said third layer is ZnSe.

17. The multi junction photovoltaic system of claim 14, wherein said second layer comprises Cd, Zn and Te.

18. The multi junction photovoltaic system of claim 14, wherein said second layer is compositionally graded in Cd and Mg or Zn.

19. The multi junction photovoltaic system of claim 14, wherein said second layer is compositionally graded in Te and Se.

20. The multi junction photovoltaic system of claim 14, further comprising a transparent conductive oxide layer adjacent to said third layer.

21. The multi junction photovoltaic system of claim 14, further comprising a thin silicon substrate adjacent to said first layer.

22. The multi junction photovoltaic system of claim 21, wherein the thin silicon substrate provides an electrical contact to said first layer.

23. The multi junction photovoltaic system of claim 14, wherein the first and third layers are interchanged.

24. A photovoltaic solar cell, comprising: a thin silicon substrate; a first layer over said substrate, wherein said first layer comprises tellurium (Te) and one or more of cadmium (Cd) and zinc (Zn), and wherein said first layer is doped p-type; a second layer adjacent to said first layer, wherein said second layer comprises Te and two or more of Cd, Zn, magnesium (Mg), and selenium (Se); and a third layer adjacent to said second layer, wherein said third layer comprises Zn and one or more of Cd, Se, and sulphur (S), and wherein said third layer is doped n-type.

25. The photovoltaic solar cell of claim 24, wherein said first layer is ZnTe.

26. The photovoltaic solar cell of claim 24, wherein said third layer is ZnSe.

27. The photovoltaic solar cell of claim 24, further comprising a transparent conductive oxide layer adjacent to said third layer.

28. The photovoltaic solar cell of claim 24, wherein said second layer comprises three or more of Cd, Zn, Mg, and Te.

29. The photovoltaic solar cell of claim 24, wherein said second layer is compositionally graded in Se and Te and in Cd, Mg or Zn.

30. The photovoltaic solar cell of claim 24, wherein said substrate is a thin single crystal or polycrystal silicon.

31. The photovoltaic solar cell of claim 24, wherein said substrate is between 1 and 3 microns thick.

32. The photovoltaic solar cell of claim 24, wherein said substrate provides an electrical contact to said first layer.

33. The photovoltaic solar cell of claim 24, wherein the first and third layers are interchanged.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The novel features of the invention are set forth with particularity. A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description that sets forth illustrative embodiments, in which the principles of the invention are utilized, and the accompanying drawings of which:

[0020] FIG. 1A shows a heterojunction photovoltaic (PV) device comprising a charge-blocking layer, in accordance with an embodiment of the invention;

[0021] FIG. 1B illustrates a series of steps that can be used to form the PV device of FIG. 1A, in accordance with an embodiment of the invention;

[0022] FIG. 1C shows an energy diagram (valence band, bottom, and conduction band, top) for the heterojunction PV device of FIG. 1A, i.e., a device comprising an n-type CdSe layer, a graded Cd.sub.xZn.sub.1-xSe blocking layer, and a p-type ZnTe layer, in accordance with an embodiment of the invention;

[0023] FIG. 1D schematically illustrates a CdSe/CIGS two-terminal PV cell incorporating a graded blocking layer, in accordance with an embodiment of the invention;

[0024] FIG. 2 is a schematic illustration of a PV cell comprising n-CdSe/p-ZnTe, but not having a graded blocking layer, in accordance with an embodiment of the invention;

[0025] FIG. 3 is a schematic illustration of a PV cell having a graded blocking layer that produces a spatial separation of regions for electron and hole charge accumulation, in accordance with an embodiment of the invention;

[0026] FIG. 4 shows a current-voltage (IV) plot for a baseline case (i.e., a PV cell without a graded blocking layer), in accordance with an embodiment of the invention;

[0027] FIG. 5 shows (a) conduction and valence band plots (energy diagram), (b) carrier density plots and (c) current density plots for a baseline PV device at 0.65 V forward bias, in accordance with an embodiment of the invention;

[0028] FIG. 6 shows an IV curve for an n-CdSe/graded blocking layer/p-ZnTe PV device, in accordance with an embodiment of the invention;

[0029] FIG. 7 a shows (a) conduction and valence band plots, (b) carrier density plots and (c) current density plots for an n-CdSe/graded blocking layer/p-ZnTe PV device at about 0.65 V forward bias, in accordance with an embodiment of the invention;

[0030] FIG. 8 shows (a) conduction and valence band plots (energy diagram), (b) carrier density plots and (c) current density plots for a PV device incorporating a graded blocking layer at near Voc conditions of about 1.25 V, in accordance with an embodiment of the invention;

[0031] FIG. 9 shows Voc as a function of interfacial defect density for a PV device having a graded blocking layer (top) and a PV device without a graded blocking layer (bottom), in accordance with an embodiment of the invention; and

[0032] FIG. 10 shows the cell efficiency as a function of interfacial defect density for a PV device having a graded blocking layer (top) and a PV device without a graded blocking layer (bottom), in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF INVENTION

[0033] While preferable embodiments of the invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous variations, changes, and substitutions will now occur to those skilled in the art without departing from the invention. It should be understood that various alternatives to the embodiments of the invention described herein can be employed in practicing the invention.

[0034] A preferable embodiment of the invention provides a heterojunction photovoltaic solar cell device that includes the following components: i) an n-type semiconductor layer; ii) a charge-blocking layer; and iii) a p-type semiconductor layer. At least some elements defining the charge-blocking layer can be in a compositionally graded configuration. The n-type semiconductor layer forms a chemically doped n-type (also n-doped herein) side of the PV cell; the p-type semiconductor layer forms the chemically doped p-type (also p-doped herein) side of the PV cell.

[0035] PV devices of embodiments of the invention can minimize, if not eliminate, problems associated with electron-hole recombination within a PV device. PV devices of preferable embodiments offer increased recombination lifetimes, while permitting flexibility in the design and implementation of PV cells.

[0036] The charge-blocking layer of preferable embodiments can ensure or at least facilitate the spatial separation of electrons and holes in order to avoid or significantly reduce interfacial recombination. The blocking layer of preferable embodiments can provide or enable a larger operating voltage for overall improved photovoltaic device efficiency. The blocking layer can be compositionally graded in order to provide a smooth compositional transition from one interface to another. In some embodiments, the blocking layer can be graded in a stepwise fashion rather than smoothly graded. A graded blocking layer can minimize interfacial defects that can contribute to interfacial recombination. Compositions of the graded blocking layer can vary through the thickness of the charge-blocking layer. As an illustrative example, in a CdSe/Graded Cd.sub.xZn.sub.1-xSe/ZnTe device, the Zn concentration, can be set to a low value (e.g., x in the range of about 0 and about 0.3) at the CdSe/Graded Cd.sub.xZn.sub.1-xSe interface, and grading up to a high Zn, low Cd concentration at the Graded Cd.sub.xZn.sub.1-xSe/ZnTe interface (e.g., x in the range of about 0.5 and about 1.0).

[0037] When reference is made to a layer having an element, such as cadmium (Cd), Zinc (Zn) or tellurium (Te), it will be appreciated that the layer comprises atoms of that element. For example, a layer comprising Cd is formed, at least in part, of Cd atoms. As another example, a layer comprising Cd, Zn and selenium (Se) is formed, at least in part, of Cd, Zn and Se atoms. In at least some cases, the composition of such a layer can be CdZnSe. The CdZnSe layer can be compositionally graded in two or more of the elements. As yet another example, a layer comprising Te and one or more of Cd and Zn is formed, at least in part, of Te atoms and Cd atoms and/or Zn atoms. In at least some cases, the composition of such a layer can be CdTe, ZnTe, or CdZnTe. PV devices having charge blocking layers

[0038] In one aspect of the invention, a PV device comprises a first semiconductor layer over a substrate; a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer is a charge-blocking layer; and a third semiconductor layer over the second semiconductor layer. In an embodiment, the first semiconductor layer is chemically doped with a p-type dopant (i.e., the first semiconductor layer comprises a p-type dopant). In another embodiment, the third semiconductor layer is chemically doped with an n-type dopant (i.e., the third semiconductor layer comprises an n-type dopant). In an embodiment, the first layer and the third layer are compositionally different (or dissimilar). In an embodiment, the charge-blocking layer is configured to prevent the recombination of electrons and holesformed upon exposure of the photovoltaic cell to photonsby spatially separating regions of electron accumulation from regions of hole accumulation. In an embodiment, regions of hole accumulation are in the first (p-type) layer and regions of electron accumulation are in the third (n-type) layer. In an embodiment, the first layer is disposed over a substrate. In an alternative embodiment, the third layer is disposed below the substrate.

[0039] In embodiments of the invention, the first layer comprises tellurium (Te) and one or more of zinc (Zn) and cadmium (Cd); the second layer comprises two or more of Cd, magnesium (Mg), selenium (Se), Te and Zn; and the third layer comprises one or more of Cd and Zn and one or more of Se and sulfur (S). The second layer can be compositionally graded in two or more of the elements comprising the second layer. In an embodiment, the first layer is doped with a p-type dopant and the third layer is doped with an n-type dopant.

[0040] In an embodiment, the first layer is formed of Te and Zn; the second layer is formed of Cd, Zn and Se, and it is graded in Cd and Zn; and the third layer is formed of Cd and Se. In an alternative embodiment, the second layer is formed of Cd, Mg and Se, and it is graded in Cd and Mg. In a preferable embodiment, the second layer is a charge-blocking layer configured to prevent the recombination of electrons and holes.

[0041] Reference will now be made to the figures, wherein like numerals refer to like parts throughout. It will be appreciated that the figures are not necessarily drawn to scale.

[0042] With reference to FIG. 1A, a photovoltaic structure 100 is provided in accordance with an embodiment of the invention is shown. The photovoltaic structure 100 comprises, from bottom to top, a substrate 110, a p-type semiconductor layer 120, a charge-blocking layer 130 and an n-type semiconductor layer 140. The PV structure 100 can include other layers between the substrate 110 and the p-type semiconductor layer 120 (as illustrated by the broken lines), as well as additional layers over the n-type semiconductor layer 140. For example, the PV structure may include a CIGS cell (see FIG. 1C). During operation of the PV device 100, photons (light) enter the PV device 100 from the top of the device 100, i.e., light first enters the n-type semiconductor layer 140 before entering the charge-blocking layer 130.

[0043] With continued reference to FIG. 1A, in an embodiment, the n-type semiconductor layer 140 can comprise n-CdSe (i.e., CdSe doped with an n-type chemical dopant); the charge-blocking layer 130 can comprise graded Cd.sub.xZn.sub.1-xSe, wherein x is a number between 0 and 1; and the p-type semiconductor layer 120 can comprise p-ZnTe (i.e., ZnTe doped with a p-type chemical dopant). The substrate 110 can be formed of a dielectric material (e.g., glass), stainless steel, titanium, a flexible polymeric material, or any semiconductor material, such as single crystal Si, polycrystalline Si, or a Group III-V semiconductor, such as, e.g., GaSb or GaAs. In one embodiment, the substrate is formed of stainless steel sheets or rolls. In another embodiment, the substrate is formed of polymeric sheets or rolls. The substrate can be of any shape and thickness suitable for a desirable application of the PV device.

[0044] In some embodiments, the relative ratios of various elemental species within each of the material layers can be varied as desired to achieve optimum device performance. In an embodiment, the ratio of elemental species in the p-type semiconductor layer 120 and the n-type semiconductor layer 140 is one-to-one.

[0045] With continued reference to FIG. 1A, in an embodiment, the p-type semiconductor layer 120 can have a thickness between about 50 nanometers (nm) and 4000 nm, or between about 50 nm and 2000 nm, or between about 50 nm and 500 nm; the charge-blocking layer 130 can have a thickness between about 10 nm and 300 nm, or between about 15 nm and 150 nm, or between about 20 nm and 50 nm; and the n-type semiconductor layer 140 can have a thickness between about 50 nm and 4000 nm, or between about 500 nm and 3000 nm, or between about 2000 nm and 3000 nm.

[0046] N-type doping (also chemical doping herein) can be achieved with the aid of, e.g., chlorine (Cl), Iodine (I), or bromine (Br) atoms, either during formation of various material layers or following formation of various material layers. P-type doping can be achieved with the aid of, e.g., nitrogen (N), phosphorous (P), arsenic (As), or antimony (Sb) atoms.

[0047] In an alternative embodiment, the charge-blocking layer can be formed of CdMgSe and graded in Cd and Mg, i.e., Cd.sub.xMg.sub.1-xSe, wherein x is a number between 0 and 1.

[0048] In an alternative embodiment, the doping configuration of the layers of FIG. 1A can be reversed. In such a case, the PV device can include an n-type semiconductor layer over the substrate; a charge-blocking layer over the n-type semiconductor layer; and a p-type semiconductor layer over the charge-blocking layer.

[0049] The charge blocking layers of various embodiments provide solar cells that allow particular engineering of the band gap, valence band offsets, and conduction band offsets for various applications. Accordingly, electron and hole accumulations occur on either side of the blocking layer (e.g., CdZnSe blocking layer), that results in charge separation by roughly the thickness of the blocking layer. This separation can be sufficient to prevent interfacial recombination. In addition, with the desired engineering or modification of the blocking layer, either through grading of composition or the selection of a specific composition, the carrier injection for either holes or electrons can be selectively inhibited such that the device turn-on voltage can be set so as to achieve solar cell efficiencies that are relatively higher that those achievable using prior art solar cells. In an embodiment, the device turn-on voltage can be increased to achieve relatively high solar cell efficiencies. In addition, for certain solar cell applications, it can be preferable to engineer or design the blocking layer in accordance with the invention so that holes and electrons generated in the absorber layer or region are able to be transported out of the device.

[0050] FIG. 1B illustrates a series of steps that can be employed to form the PV cell of FIG. 1A. First, in step 210 a p-ZnTe layer is formed over a substrate. The p-ZnTe layer can be formed using any deposition technique known in the art (see below). As an example, the p-ZnTe layer can be formed via co-evaporation using fluxes of Zn and Te. P-type doping of the ZnTe layer can be achieved either during deposition of the ZnTe layer or following formation of the ZnTe layer.

[0051] Next, in step 220 a CdZnSe charge-blocking layer, compositionally graded in Cd and Zn, is formed. Grading can be accomplished by a decreasing amount of Zn in going from the p-ZnTe side of the device to the n-CdSe side of the device. The relative composition of Se is kept constant. As the composition of Zn is decreased, the composition of Cd is increased. Formed in such manner, at a first interface adjacent the ZnTe layer, the charge-blocking layer comprises substantially all ZnSe (i.e., there is substantially little Cd); at a second interface adjacent the CdSe layer, the charge-blocking layer comprises substantially all CdSe (i.e., there is substantially little Zn).

[0052] Next, in step 230 an n-CdSe layer is formed over the charge-blocking layer. The n-CdSe layer can be formed using any deposition technique known in the art (see below). As an example, the ZnTe layer can be formed via co-evaporation using fluxes of Cd and Se precursors. N-type doping of the CdSe layer can be achieved either during deposition of the CdSe layer or following formation of the CdSe layer.

[0053] Following formation of one or more of the p-ZnTe layer, charge-blocking layer and n-CdSe layer, the substrate can be annealed for a predetermined period of time. Annealing can aid in curing defects formed during deposition of one or more layers of the PV device.

[0054] In alternative embodiment (now shown), the steps used in forming the PV device of FIG. 1A are reversed. In such a case, the n-type CdSe layer is formed first over, e.g., a TCO layer or a substrate. Next, the graded charge-blocking layer is formed over the n-type CdSe layer. Next, the p-type ZnTe layer is formed over the graded charge-blocking layer.

[0055] The p-type ZnTe layer, charge-blocking layer, and n-type CdSe layer can be formed using any technique known in the art, such as, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), electroplating, co-evaporation, sputtering, inkjet printing techniques, sintering, plasma-enhanced CVD (PECVD) or plasma-enhanced ALD (PEALD), molecular beam epitaxy, or a technique that combines two or more of these methods.

[0056] FIG. 1C illustrates an energy diagram of a heterojunction photovoltaic solar cell comprising Cd.sub.xZn.sub.1-xSe for a blocking layer that can be used, for example, in the solar cell of FIG. 1A (i.e., a solar cell formed of an n-type CdSe layer, a graded Cd.sub.xZn.sub.1-xSe blocking layer, and a p-type ZnTe layer), in accordance with a preferable embodiment of the invention. The discontinuity in the energy band diagram (valance and conduction bands) at the interface between the blocking layer and the p-type ZnTe layer substantially prevents electron-hole recombination, thereby providing for enhanced PV device efficiencies in relation to other prior art solar cells.

[0057] FIG. 1D illustrates a two-terminal PV device, in accordance with an embodiment of the invention. The PV device comprises an upper cell over a lower cell, the upper cell comprising a CdSe layer over a charge-blocking layer, which is in turn disposed over a ZnTe layer; the lower cell comprising a copper indium gallium (di) selenide (CIGS) cell. The PV device comprises, from bottom to top, a substrate, a molybdenum (Mo) layer, a CIGS layer (or cell), an n-type CdS layer, a tunnel junction, a p-type ZnTe layer, a charge-blocking layer, an n-type CdSe layer, and a transparent conducting oxide (TCO) layer. The tunnel junction can comprise a highly-doped ZnTe/CdSe bilayer. The PV device can comprise additional layers. For example, the PV device can comprise an electrode in electrical contact with the substrate and en electrode in electrical contact with the TCO layer.

[0058] In an embodiment, the n-type CdS layer adjacent the CIGS cell can be replaced by a lower band gap material, such as CdSe, to give more flexibility in manufacturing and device optimization.

[0059] According to other aspects of the invention, the blocking layer described herein can be structured in several ways. For example, many of the possible manifestations of the invention include grading of the blocking layer to reduce interfacial trap densities at one of the two interfaces, while some use a blocking layer that is not graded. Alternative embodiments of the invention include, but are not limited to, PV devices comprising the following structures: i) n-CdSe/graded Cd.sub.xZn.sub.1-xSe/p-ZnTe; ii) n-CdSe/graded Mg.sub.xCd.sub.1-xSe.sub.yTe.sub.1-y/p-ZnTe; iii) n-CdSe/graded Mg.sub.xCd.sub.1-xSe.sub.yTe.sub.1-y/p-CdZnTe; iv) n-Cd.sub.xZn.sub.1-xSe/graded Mg.sub.xCd.sub.1-xSe.sub.yTe.sub.1-y/p-CdZnTe; v) n-CdSe/Graded Mg.sub.xCd.sub.1-xSe/p-ZnTe; vi) n-CdSe/ZnSe blocking layer/p-ZnTe and vii) n-CdS/Graded Zn.sub.xCd.sub.1-xS/p-CdTe.

[0060] Although in the above examples Group II-VI wide semiconductors have been used, it will be appreciated that other photovoltaic semiconductors, such as, for example, Group III-V or Group IV semiconductors, can be used.

[0061] Furthermore, for embodiments of the invention in which Mg is used in the blocking layer, it is possible to use Te in the ternary (three types of atoms)/quaternary (four types of atoms) blocking layer in order to raise the valence band edge. Unlike devices such as light emitting diodes (LEDs) where the minority carrier transportation is relatively unimportant, that is not the case usually for solar cells. More specifically, if or when there is a barrier to minority carrier transportation, the performance of the solar device can be negatively impacted. Moreover, due to the slight lowering of the valence band edge in ternaries such as Mg.sub.xCd.sub.1-xSe, there can be additional benefits to device performance with the addition of some Te to the blocking layer. In this case the Te replaces Se with a resulting quaternary compound of Mg.sub.xCd.sub.1-xSe.sub.yTe.sub.1-y. In addition, if the valence band edge position becomes a challenge for the extraction of minority carriers, deeper energy states can be introduced at the interface in order to enable tunneling and extraction of the carriers.

[0062] While single PV devices (or cells) have been shown, it will be appreciated that a PV device can comprise multiple PV cells. For example, PV devices of embodiments of the invention can be arranged in a parallel or series fashion to form PV arrays.

[0063] PV cells of embodiments of the invention can be incorporated in devices having various form factors. As an example, PV cells (or devices) of embodiments of the invention can be incorporated in flat-panel PV devices. As another example, PV devices of embodiments of the invention can be incorporated in cylindrical PV devices.

[0064] PV devices of embodiments of the invention can have various uses. For example, PV devices of embodiments of the invention can be used in solar cell arrays in, e.g., solar farms. As another example, PV cell of embodiments of the invention can be used in PV devices disposed on the rooftops of cars. Such devices can provide power to electric or hybrid (gas-electric) vehicles.

Energy Diagrams

[0065] Energy diagrams of PV devices with and without the charge-blocking layer of preferable embodiments of the invention can illustrate the benefits that can be derived from PV devices having the charge-blocking layer.

[0066] FIG. 2 shows energy band diagrams for a PV device without a charge-blocking layer. The energy band diagrams are directed to a PV device having an n-type CdSe overlying a p-type ZnTe layer; there is no charge-blocking layer between the n-type CdSe layer and the p-type ZnTe layer. The top diagram in FIG. 2 shows the relative band alignments for the two materials; the middle diagram shows the device at zero bias (voltage); and the bottom diagram shows the device at forward bias when exposed to sunlight. Before the PV device can reach a 1.2 V bias, which might be desired for ideal device performance, electron and hole accumulation can start to occur at the CdSe/ZnTe interface. With these high levels of carrier concentration at a heterojunction interface, high recombination currents can be triggered, leading to a decrease in device performance (or efficiency).

[0067] With reference to FIG. 3, the addition of a graded blocking layer results in the spatial separation of regions (also charge accumulation regions herein) of electron and holes, leading to improved device performance. The band diagrams of FIG. 3 are directed to a device comprising an n-type CdSe layer, a charge-blocking layer, and a p-type ZnTe layer. In one embodiment, the charge-blocking layer is formed of CdZnSe and compositionally graded (also graded herein) in Cd and Zn, i.e., Cd.sub.xZn.sub.1-xSe, wherein x is a number between 0 and 1. In another embodiment, the charge-blocking layer is formed of CdMgSe and graded in Mg and Cd, i.e., Cd.sub.xMg.sub.1-xSe, wherein x is a number between 0 and 1. The top plot of FIG. 3 shows a representative example for the relative band alignments prior to charge redistribution. The grading can be engineered such that there is a smooth composition change at the interface between the n-type semiconductor layer (e.g., n-type CdSe) and the graded blocking layer. Grading can be accomplished by an increasing amount of either Zn or Mg in going from the n-CdSe side of the device to the p-ZnTe side of the device. The conduction band edge and band gap can be gradually increased as the ZnTe/graded layer interface is approached. The bottom plot of FIG. 2 shows the band diagram and the desired effect of spatial separation of the regions of charge accumulation at a 1.2 V forward bias.

[0068] In embodiments of the invention, a semiconductor heterojunction photovoltaic solar cell can be formed with a blocking layer, wherein the blocking layer is used to (i) spatially separate electrons and holes to significantly reduce interfacial recombination; and/or (ii) prevent early turn-on of the device in order to increase the operating voltage of the device. These two functions can significantly improve the efficiency of a solar cell incorporating a semiconductor heterojunction of embodiments of the invention. These functions can be also achieved by engineering the blocking layer in accordance with the invention. Moreover, the blocking layer can be engineered or designed to satisfy or meet the following conditions: (i) the blocking layer can block a majority of carrier transport at its two ends (the blocking layer band offsets to the adjacent semiconductors can take the form of either an abrupt band offset or a graded band offset); and/or (ii) the blocking layer can sufficiently provide for the free flow of minority carriers in order for the photo-generated current and power to be effectively extracted from the device.

[0069] Alternative embodiments of the invention can be used in a stand-alone single junction solar cell. The invention can also be used in the upper or lower cell in a multi junction solar cell structure (e.g., tandem junction, or three or more junctions). The invention can be used as the upper or lower cell in a two terminal, three terminal, or four terminal multi junction solar devices.

EXAMPLES

[0070] FIGS. 4-10 show plots from solar cell capacitance simulator (SCAPS) simulations, in accordance with embodiments of the invention.

[0071] FIG. 4 shows the current-voltage (IV) plots for a PV device formed of an n-type CdSe layer overlying a p-type ZnTe layer (also baseline case herein). The device of FIG. 4 does not have a charge-blocking layer. As can be seen in the plot, the current densities start to increase at about 0.6 V. At about 0.65 V, the device current flow is in the forward bias direction. The PV device of FIG. 4 had a Jsc of about 22.9 mA/cm.sup.2, a voltage open circuit (Voc) of about 0.69 V, and an efficiency of about 13.0%.

[0072] FIG. 5 shows an energy band diagram (top), carrier density profile (middle) and current density profile (bottom) for a baseline n-CdSe/p-ZnTe device at 0.65V forward bias. At this voltage, the conduction and valence bands are approaching the flat band conditions. While both the n-CdSe and p-ZnTe layers remain slightly depleted at the interface between the two materials, the product of the hole and electron concentrations reaches a peak at this interface. Recalling that the slope of the current density profiles are proportional to the recombination rate, it can be seen from the sharp step function shifts in this plot that the high combined concentration of holes and electrons at the interface is resulting in significant interfacial recombination. This recombination is responsible for the low Voc observed in the simulation results and provides further support for explanations of results from earlier experiments within this material system.

[0073] FIG. 6 shows an IV curve for a PV device comprising an n-CdSe layer, a graded charge-blocking layer (CdZnSe), and a p-type ZnTe layer. The turn-on voltage for the device is significantly higher than the turn-on voltage for the device in the baseline case. The PV device of FIG. 6 had a Voc of about 1.4V, a Jsc of about 22.9 mA/cm.sup.2, and a final efficiency of greater than about 26%. With these results, there was an improvement in overall PV device performance in relation to the baseline case.

[0074] FIG. 7 shows energy band diagram (top, showing conduction and valence band plots), carrier density profile (middle) and current density profile (bottom) for a PV device having an n-CdSe layer, a graded charge-blocking layer, and a p-ZnTe layer. The device was simulated at 0.65V forward bias. To emulate the graded charge-blocking layer, five layers with incrementally increasing band gaps were used. At 0.65 V forward bias, the baseline device was already approaching forward current flow. As with the baseline device, the band diagram shows nearly flat band type conditions. However, examining the charge density profiles, the electron and hole concentrations decreased sharply at either end of the graded blocking layer, resulting in substantially no spatial overlap of the regions of high electron and hole concentration. Similarly, the current density profiles do not show step function changes that are indicative of elevated interfacial recombination. As a result, current flow remains in the reverse bias direction, therefore resulting in higher efficiency.

[0075] FIG. 8 shows energy band diagram (top, showing conduction and valence band plots), carrier density profile (middle) and current density profile (bottom) for a PV device having an n-CdSe layer, a graded charge-blocking layer, and a p-ZnTe layer. The device was simulated at 1.25V forward bias. At this bias the device is beyond flat band conditions. The hole and electron concentration profile plots (middle) show carrier accumulation at the two interfacesi.e., the interface between the n-CdSe layer and charge-blocking layer, and the interface between the p-ZnTe layer and the charge-blocking layerto the graded blocking layer. Even though the carrier concentrations are high, the regions of high concentration advantageously remain spatially separated. At 1.25 V forward bias there is substantially little interfacial recombination.

[0076] FIG. 9 shows SCAPS simulations results of Voc as a function of interface defect density (interface between the ZnTe layer and the charge-blocking layer) for a standard CdSe/ZnTe device (bottom plot, data points marked by diamonds) and a device incorporating the graded blocking layer (top plot, data points marked by boxes). The incorporation of the blocking layer can enable a significant improvement in device Voc at realistic interface defect densities of about 110.sup.11 cm.sup.2. Voc remained in the 1.4 V range, as compared to a significant drop in Voc levels for a PV device not incorporating the blocking layer.

[0077] FIG. 10 shows PV cell efficiency as a function of interface defect density (interface between the ZnTe layer and the charge-blocking layer) for a standard CdSe/ZnTe device (bottom plot, data points marked by diamonds) and a device incorporating the graded blocking layer (top plot, data points marked by boxes). At interface defect densities of about 110.sup.11 cm.sup.2 efficiencies greater than about 20% were observed for the device having the charge-blocking layayerfor; at about the same defect density, the device lacking the charge-blocking layer had a defect density of about 10%. FIG. 10 shows that the graded blocking layer can render the PV device relatively insensitive to the density of defects at the interface between the ZnTe layer and the graded charge-blocking layer.

[0078] It should be understood from the foregoing that, while particular implementations have been illustrated and described, various modifications can be made thereto and are contemplated herein. It is also not intended that the invention be limited by the specific examples provided within the specification. The concepts of the invention can be applied to other known devices using multi-junction and heterojunction structures known in the art such as the following which are entirely incorporated herein by reference: U.S. Pat. No. 5,371,409, entitled, WIDE BANDGAP SEMICONDUCTOR LIGHT EMITTERS; U.S. Pat. No. 4,680,422, entitled, TWO-TERMINAL, THIN FILM, TANDEM SOLAR CELLS; U.S. patent application Ser. No. 10/551,598, now U.S. Patent Publication No. 2007/0137698, entitled, MONOLITHIC PHOTOVOLTAIC ENERGY CONVERSION DEVICE; M. W. Wang et al., n-CdSe/p-ZnTe based wide band-gap light emitters: Numerical simulation and design, J. Appl. Phys. 73 (9).; P. Gashin, A. Focsha, T. Potlog, A.V. Simashkevich, V. Leondar, n-ZnSe/p-ZnTe/n-CdSe tandem solar cells Solar Energy Materials and Solar Cells, 46, no. 4 (1997), pg. 323-331; P. Mahawela, S. Jeedigunta, S. Vakkalanka, C. S. Ferekides, D. L. Morel, Transparent high-performance CdSe thin-film solar cells, Thin Solid Films 480-481,2005, pg. 466-470.; and S. Vakkalanka, C. S. Ferekides, D. L. Morel, Development of ZnSexTelx p-type contacts for high efficiency tandem structures, Thin Solid Films 515 (2007), pg. 6132-6135.

[0079] While the invention has been described with reference to the aforementioned specification, the descriptions and illustrations of the preferable embodiments herein are not meant to be construed in a limiting sense. Furthermore, it shall be understood that all aspects of the invention are not limited to the specific depictions, configurations or relative proportions set forth herein which depend upon a variety of conditions and variables. Various modifications in form and detail of the embodiments of the invention will be apparent to a person skilled in the art. It is therefore contemplated that the invention shall also cover any such modifications, variations and equivalents.