Transducer driver circuitry

Abstract

This application relates to method and apparatus for driving acoustic transducers, such as speakers or haptic transducers. A transducer driver circuit (200) has a hysteretic comparator (201) configured to compare, with hysteresis, an input signal (S.sub.IN) received at a first comparator input to a feedback signal (S.sub.FB) received at a second comparator input. Based on the comparison the hysteretic comparator (201) generates a pulse-width modulation (PWM) signal (S.sub.PWM) at a comparator output (206). An inductor (203) is coupled between the comparator output and an output node (204). In use a resistive component (208), which may comprise the transducer (301) is coupled to output node (204). The inductor (203) and resistive component (208) provide filtering to the PWM signal (S.sub.PWM). A feedback path extends between the output node (204) and the second comparator input to provide the feedback signal (S.sub.FB).

Claims

1. A transducer driver circuit comprising: an input node for receiving an input acoustic signal waveform; an output node for outputting a driving signal waveform for driving an acoustic output transducer based on the input acoustic signal waveform; a hysteretic comparator configured to compare, with hysteresis, the input acoustic signal waveform received at a first comparator input to a feedback signal received at a second comparator input and to generate a pulse-width modulation (PWM) signal at a comparator output; an inductor coupled between the comparator output and the output node; and a feedback path between the output node and the second comparator input to provide the feedback signal.

2. A transducer driving circuit as claimed in claim 1 further comprising a hysteresis controller for controlling hysteresis of the hysteretic comparator.

3. A transducer driving circuit as claimed in claim 2 wherein the hysteresis controller is configured to control the hysteresis of the hysteretic comparator based on the PWM signal.

4. A transducer driving circuit as claimed in claim 3 further comprising a time-to-digital-converter configured to receive the PWM signal and output a digital control signal based on a parameter of the PWM signal, wherein the hysteresis controller is configured to receive the digital control signal.

5. A transducer driving circuit as claimed in claim 4 wherein said parameter comprises one of: a duration of a cycle period of the PWM signal; a duty-cycle of the PWM signal and a duration of a pulse of the PWM signal.

6. A transducer driving circuit as claimed in claim 4 wherein the time-to-digital converter is configured to receive a reference clock signal and comprises a counter configured to produce at least one count value of the number of clock cycles of the reference clock signal in a period defined by the parameter of the PWM signal.

7. A transducer driving circuit as claimed in claim 2 wherein the hysteresis controller is configured to control the hysteresis of the hysteretic comparator based on an indication of a level of the input signal waveform.

8. A transducer driving circuit as claimed in claim 1 further comprising an acoustic output transducer coupled to be driven by the driving signal waveform at the output node.

9. A transducer driving circuit as claimed in claim 8 wherein the transducer comprises a resistive load.

10. A transducer driving circuit as claimed in claim 9 further comprising a capacitance connected between the output node and a reference potential.

11. A transducer driving circuit as claimed in claim 8 wherein the transducer comprises a capacitive load.

12. A transducer driving circuit as claimed in claim 11 comprising a resistance in series between the transducer and the output node.

13. A transducer driving circuit as claimed in claim 8 wherein the transducer comprises at least one of: a piezoelectric transducer, a haptic output transducer, an ultrasonic output transducer and an audible audio output transducer.

14. A transducer driving circuit as claimed in claim 1 wherein the hysteretic comparator is formed as at least part of an integrated circuit.

15. A transducer driving circuit as claimed in claim 14 wherein the inductor is an external component to the integrated circuit and is coupled to the integrated circuit.

16. A transducer driving circuit as claimed in claim 1 wherein the hysteretic comparator is not implemented as part of an integrated circuit and the transducer driving circuit is coupled to a first output of an integrated circuit and is operable so that an analogue output signal at said first output can be supplied to the hysteretic comparator as said input signal waveform.

17. A transducer driving circuit as claimed in claim 16 wherein the transducer driving circuit is coupled to said first output of the integrated circuit via a switch arrangement, wherein the switch arrangement is operable to selectively supply the analogue output signal at said first output to the hysteretic comparator or to a second signal path wherein said second signal path leads to a contact of a device connector for making a connection with a removable accessory apparatus.

18. An electronic device comprising a transducer driving circuit as claimed in claim 1.

19. A transducer driver circuit for driving a transducer comprising: an input node for receiving an input time-varying signal waveform; a PWM node for outputting a pulse-width modulation (PWM) signal to drive a transducer via an inductor; a feedback node for receiving a feedback signal tapped from one node downstream of the inductor and upstream of the transducer; a hysteretic comparator having a first comparator input coupled to the input node; a second comparator input coupled to the feedback node and a comparator output coupled to the PWM node, the hysteretic comparator being configured to compare the feedback signal to the input signal to generate the PWM signal; and a hysteresis controller for controlling hysteresis of the hysteretic comparator.

20. A transducer driver circuit for driving an acoustic signal waveform into an acoustic transducer to provide an acoustic output therefrom comprising: a hysteretic comparator configured to compare, with hysteresis, an input signal received at a first comparator input to a feedback signal received at a second comparator input and to generate a pulse-width modulation (PWM) signal at a comparator output; and an inductor coupled between the comparator output and an output node; wherein the feedback signal is tapped from one point of a signal path between the comparator and the acoustic transducer which is downstream of the inductor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of examples of the present disclosure, and to show more clearly how the examples may be carried into effect, reference will now be made, by way of example only, to the following drawings in which:

(2) FIG. 1 illustrates one example of a conventional Class D signal path for driving a transducer;

(3) FIG. 2 illustrates one example of an embodiment of transducer driving circuitry;

(4) FIG. 3 illustrates an example of an embodiment for driving a resistive load;

(5) FIG. 4 illustrates the principle of the PWM signal generated by the hysteretic comparator;

(6) FIG. 5 illustrates another example of a transducer driving circuit that receives a look-ahead signal indicative of the input signal;

(7) FIG. 6 illustrates another example of an embodiment for driving a resistive load;

(8) FIG. 7 illustrates an example of an embodiment for driving a capacitive load;

(9) FIG. 8 illustrated an embodiment of off-chip transducer driving circuitry; and

(10) FIG. 9 illustrates one example of a hysteretic comparator with controllable hysteresis.

DETAILED DESCRIPTION

(11) Embodiments relate to methods and apparatus for generating driving signals for driving transducers and, in particular, for driving of acoustic transducers such as loudspeakers, ultrasonic transducers, haptic transducers and the like. In particular, some embodiments relate to transducer driving circuitry having a hysteretic comparator configured to compare, with hysteresis, an input signal received at a first comparator input to a feedback signal received at a second comparator input and to generate a pulse-width modulation (PWM) signal at a comparator output. An inductor is coupled between the comparator output and an output node and a feedback path extends between the output node and the second comparator input to provide the feedback signal.

(12) The transducer driving circuitry is advantageous in that it can be implemented in a relatively small circuit implementation, especially for smaller IC process node geometries, and can be implemented with relatively low power consumption.

(13) FIG. 2 illustrates the general form of transducer driving circuitry 200 according to an embodiment. Hysteretic comparator 201 is arranged to receive an input signal S.sub.IN from input node 202. The input signal S.sub.IN is a time varying input signal comprising some encoded content that is used to drive the transducer. For example the input signal S.sub.IN may be an audio signal representative of some sound to be generated by a speaker.

(14) The input node 202 may be some terminal or contact for receiving the input signal S.sub.IN, e.g. a pad of an integrated circuit, or an output of some upstream processing block/circuitry or could just be a suitable node of a signal path. The input signal S.sub.IN is provided to a first comparator input (+) of the hysteretic comparator 201.

(15) The hysteretic comparator 201 compares the input signal S.sub.IN at the first comparator input with a feedback signal S.sub.FB received at a second comparator input (−) and generates an output signal S.sub.OUT based on the comparison. The hysteretic comparator 201 is operable to apply hysteresis to the comparison.

(16) An inductor 203 is coupled between the output of the comparator 201 and an output node 204 and a feedback path also extends from the output node 204 to the second comparator input for providing a feedback signal S.sub.FB to the second comparator input.

(17) In some implementations the hysteretic comparator 201 may be implemented as at least part of an integrated circuit 205, which may for instance be an audio circuit such as a codec or the like. In some instances it may be possible to integrate a suitable inductor 203 as part of the integrated circuit 205. In which case the output node 204 may be part of the integrated circuit 205 and could for instance be a terminal of the integrated circuit 205, e.g. a contact pad or the like, or may be any suitable node of the signal path for the output signal S.sub.OUT. In other implementations, as illustrated in FIG. 2, the inductor 203 could be an external component to an integrated circuit 205, i.e. off-chip component. In which case the integrated circuit 205 may include a PWM node 206, e.g. a suitable output terminal, for outputting the comparator output, and a feedback node 207, e.g. a suitable input terminal, for receiving the feedback signal SFB.

(18) In use, the output node 204 will be coupled to a resistive component 208. The resistive component 208 may, in some cases, comprise the transducer to be driven, for instance a loudspeaker or similar as will be described in more detail below. Additionally or alternatively the resistive component 208 could be a resistive component other than transducer which is connected to the output node, and could for instance be an on-chip resistor (e.g. coupled to the feedback path extending from feedback node 207) or off-chip resistor.

(19) The inductor 203 together with resistive component 208 thus, in use, acts as a filter for filtering the PWM output signal S.sub.OUT which is output from the hysteretic comparator 201. This means that the signal S.sub.D at the output node is an analogue driving signal which is suitable for driving the transducer. The feedback signal SFB which is derived from the output node 204 is thus an indication of the driving signal S.sub.D. In the example illustrated in FIG. 2, with just a resistive component coupled between the output node 204 and a reference potential, e.g. ground, the inductor 203 and resistive component provide low-pass filtering.

(20) The hysteretic comparator 201 compares the signals at the first and second comparator inputs, i.e. the input signal S.sub.IN and the feedback signal S.sub.FB, and outputs either of two output states, V.sub.H and V.sub.L, depending on the result of the comparison. The hysteretic comparator 201 is operable to apply hysteresis to the comparison such that a differential voltage between the signals S.sub.IN and S.sub.FB at the first and second comparator inputs must be greater (i.e. more positive or less negative) than a first threshold to transition from one output state to the other, say from output state V.sub.L to the output state V.sub.H, but must be lower (i.e. less positive or more negative) than a second, different threshold to make the opposite transition, e.g. to swap from the output state V.sub.H to the output state V.sub.L. The difference between these first and second thresholds corresponds to the amount of hysteresis applied. In some implementations the first and second thresholds may be equal in magnitude and opposite in polarity, i.e. the difference between the input signal S.sub.IN and the feedback signal S.sub.FB must be greater than an amount +H to transition to one state, say V.sub.H, and must be lower than −H to transition to the other state. In this instance the magnitude of H can be seen as a measure of the hysteresis applied by the hysteretic comparator 201. However other arrangements could be implemented.

(21) The output states V.sub.H and V.sub.L may be high and low voltage levels respectively, for instance a supply voltage V.sub.DD and ground, or a positive voltage and a negative voltage, possibly of equal magnitude. Thus the output signal S.sub.OUT may be a square wave type voltage signal produced as the hysteretic comparator 201 transitions between the two output voltage states.

(22) The inductor 203 is thus driven, on one side, i.e. at PWM node 206, by the output signal S.sub.OUT that alternates between the high voltage V.sub.H and the low voltage V.sub.L. The inductor 203 will (in use connected in series with resistance 208), provide some averaging, or low pass filtering, as will be understood by one skilled in the art, so the voltage at the output node 204 will be somewhere within the range V.sub.H to V.sub.L, with the actual voltage depending on the proportion of time spent in the high state V.sub.H compared to the low state V.sub.L.

(23) The hysteretic comparator 201 thus effectively compares the voltage at the output node 204 (via the feedback signal S.sub.FB) to the input signal S.sub.IN. If the feedback signal S.sub.FB drops below the input signal S.sub.IN by the relevant amount of hysteresis, the hysteretic comparator 201 will swap to the high output state V.sub.H. At this point there will be a positive voltage difference across the inductor 203 and the inductor current, and voltage at the output node 204, will ramp up. This ramp will continue until the first threshold is reached, e.g. feedback signal S.sub.FB exceeds the input signal S.sub.IN by the relevant hysteresis amount, say +H, at which case the hysteretic comparator 201 will swap to the low output state V.sub.L. At this point the inductor current, and voltage at the output node 204 will ramp down until the relevant threshold is reached and the output swaps state again.

(24) Thus the hysteretic comparator 201 will continually cycle between the first and second output states V.sub.H and V.sub.L in order to maintain the voltage at the output node 204 to be the same as the input signal S.sub.IN (within the defined hysteresis limit).

(25) In effect the hysteretic comparator 201 with inductor 203 and the feedback path replaces the functionality of the PWM modulator 101, output stage 102 and filter 103 discussed with reference to FIG. 1. This provides a very compact transducer driver circuit arrangement, which is also power efficient as all energy supplied to inductor 203 is available for a load connected to the output node 204. Also the feedback is taken from the output node 204 which couples to the load, rather than being taken before any filtering component in series with the load. This means that the output accuracy is not impaired by any non-linearity or pass-band filter ripple of any filter component, i.e. the output signal to the transducer accurately corresponds to the input signal S.sub.IN (disregarding any higher-frequency residual sideband components due to the PWM switching). Thus the feedback signal S.sub.FB supplied to the second comparator input of the hysteretic comparator is derived wholly from downstream of the inductor, i.e. from the signal path between the inductor and the transducer. As illustrated the feedback signal may be tapped from one point of the signal path between the comparator output and the transducer, and the tap point is downstream of the inductor. Thus the PWM signal S.sub.OUT only contributes to the feedback signal after having passed via the inductor 203 (there is no significant contribution to the feedback signal S.sub.OUT before filtering by the inductor 203), i.e. all signal components of the feedback signal are derived from a signal path between the inductor and the transducer.

(26) As noted above the resistive component 208 may, in some instances, comprise the relevant transducer being driven. FIG. 3 illustrates an embodiment, in which similar components to those illustrated in FIG. 2, are identified using similar components. FIG. 3 illustrates that a transducer 301, which presents a resistive load, is connected to the output node 204 to be driven by the driving signal S.sub.D.

(27) In the embodiment of FIG. 3 the transducer 301 provides the resistive component 208 in series with the inductor 203 and thus forms part of the filter of the transducer driving circuitry. This means that the value of the resistance presented by transducer 301 has an impact on the cycle period of the PWM output signal S.sub.OOT generated by the hysteretic comparator 201.

(28) As noted above the hysteretic comparator 201 will cyclically alternate between instances of the high output state V.sub.H and the low output state V.sub.L to effectively increase and then decrease the voltage at the output node 204. This cycling between output states of the hysteretic comparator 201 can thus appear as a type of ripple voltage in driving signal S.sub.D.

(29) The time spent in each output state in each cycle will depend on how long it takes for the feedback signal S.sub.FB to change by the amount defined by the hysteresis, e.g. from a value equal to S.sub.IN−H to a value S.sub.IN+H or vice versa. This will depend on the amount of hysteresis and the rate of change of the feedback signal S.sub.FB. The rate of change of the feedback signal S.sub.FB will itself depend on the then-current value of the feedback signal S.sub.FB, i.e. the voltage at the output node 204, which, as noted above depends on the level of the input signal S.sub.IN. It will be understood that the rate of current ramping within the inductor 203 will depend on the voltage difference across the inductor 203, which depends on the present output of the hysteretic comparator 201 and the voltage at the output node 204.

(30) For example, if the voltage at the output node is relatively high, e.g. near V.sub.H, then, when the hysteretic comparator 201 output is in the high state V.sub.H, there will be a relatively small positive voltage difference across the inductor 203 and the inductor current will ramp relatively slowly. It will therefore take a relatively long time for the feedback signal S.sub.FB to increase to exceed the input signal S.sub.IN by the relevant hysteresis amount, e.g. for S.sub.FB to reach S.sub.IN+H. However once the hysteretic comparator 201 output swaps to the low state V.sub.L there will then be a relatively high negative voltage difference across the inductor and the current will rapidly ramp downwards. Thus it will take only a relatively short period of time for the feedback signal S.sub.FB to drop below the input signal S.sub.IN by the relevant hysteresis amount, e.g. for S.sub.FB to reach S.sub.IN−H. The reverse would be true if the voltage at the output node were a relatively low voltage.

(31) The duration of a pulse corresponding to the high state V.sub.H in the output signal S.sub.OUT (and correspondingly the duration of a pulse corresponding to the low state V.sub.L in the output signal S.sub.OUT) thus depends on the level of the input signal S.sub.IN.

(32) FIG. 4 illustrates the principles of the output signal S.sub.OUT from the hysteretic comparator in a circuit arrangement such as illustrated in FIG. 2. The duration of a pulse of the high state V.sub.H is denoted by α and the duration of a pulse of the low state V.sub.L is denoted by β. The cycle period T is equal to α+β. The cycle period T can also be seen as the period between an instance of a transition from one output state to the other output state and the next instance of the same transition.

(33) As described above the duration a of the pulse of the high state V.sub.H depends on the level of the input signal S.sub.IN, as does the duration of the pulse of the low state V.sub.L. For signals of zero magnitude (which corresponds to a voltage value equal to the midlevel voltage V.sub.MID between V.sub.H and V.sub.L) the periods of the pulses of each state, illustrated in FIGS. 4 as α.sub.0 and β.sub.0, will be equal to one another, i.e. each equal to T.sub.0/2 where T.sub.0 is the cycle period at zero magnitude.

(34) If the magnitude of the input signal S.sub.IN increases the duration of the pulse of one state will increase and the duration of the pulse of the other state will decrease to first order by:
α=T.sub.0/2.(1−X) β=T.sub.0/2.(1+X)  (eqn. 1)

(35) where X is the level of the normalised input signal, i.e.
X=S.sub.IN/S.sub.MAX  (eqn. 2)

(36) where S.sub.MAX is the maximum magnitude of the input signal defined as (V.sub.H−V.sub.L)/2, i.e. X is a level of the input signal normalised with respect to an input range to lie within a range +1 to −1, where a magnitude of 1 corresponds to a signal level that asymptotically leads to an output frequency of zero.

(37) It will be appreciated from equation 1 that increase in duration of one pulse is not equal to the decrease in duration of the other pulse and the overall cycle period T will change approximately according to:
T=α+β=T.sub.0/(1−X.sup.2)  (eqn. 3)

(38) Thus any increase in the magnitude of the input signal (from zero magnitude) will result in an increase in the cycle period, as illustrated by the durations α.sub.1 and β.sub.1 and duration T.sub.1 for a cycle period at a non-zero input signal magnitude. Thus the cycle period T.sub.0 (equal to α.sub.0+β.sub.0) corresponding to an input signal of zero magnitude will be the cycle period of shortest duration. This condition is referred to as the “limit cycle” and the period T.sub.0 is the “limit cycle period”. This corresponds to the fastest cycle frequency f.sub.0=1/T.sub.0 which is referred to as the “limit cycle frequency”.

(39) For the embodiment illustrated in FIG. 2, with an inductor 203 of inductance L in series with a resistive load 208 having a resistance R, the limit cycle period is given by:
T.sub.0=(2L/R).In{(V.sub.MID+H)/(V.sub.MID−H)}  (eqn. 4)

(40) where H is indicative of the amount of hysteresis. For H small compared to V.sub.MID this may be approximated as:
T.sub.0≈(2L/R),In{(1+2H/V.sub.MID)=4(L/R).H)}  (eqn. 5)

(41) It can therefore be seen from equations 4 or 5 that the limit cycle period, and hence frequency for the PWM signal S.sub.OUT, thus depends on the value of the resistance R of the resistive component 208. Further it can be seen from equation 3 that the cycle period of the PWM signal S.sub.OUTcan vary significantly from this limit cycle frequency with increasing magnitude of the input signal S.sub.IN.

(42) As noted above the voltage V.sub.D of the driving signal S.sub.D will include a ripple component at the frequency of the cycle period of the PWM output signal S.sub.OUTGenerally it may be desirable to ensure that such a component does not extend into the signal band of interest.

(43) If the resistance R of the resistive component 208, e.g. the transducer 301, is known, then it may, in some instances, be possible to select an appropriate value for the inductance L of inductor 203 and hysteresis value H that ensures that the cycle period is always outside the signal band of interest for the expected input signal S.sub.IN levels.

(44) However in some instances the resistance R of the transducer 301 may not be known. For instance, if the hysteretic comparator 201 were implemented as an integrated circuit 205, possibly with an integrated inductor 203, the manufacturer of the integrated circuit 205 may not know what transducer 301 a device manufacturer may choose to use in a host device. In some implementations the circuit 205 may be operable, in use, with different transducers, especially for instance if the transducer 301 is a transducer of an accessory apparatus connected via some suitable connection 302. In such cases therefore it may not be possible to design the transducer driving circuitry for operation with a specific transducer resistance.

(45) Also, even if the resistance of the transducer 301 is known it may not be desirable or practical in some implementations to use a value of inductance L to ensure that the cycle period does not extend into the signal band of interest, at least not without some compromise on performance.

(46) To avoid these issues, FIG. 3 illustrates that the transducer driving circuitry 205 may include a controller 303 for controlling the cycle period of the PWM output signal S.sub.OUT. In the example illustrated in FIG. 3 the controller 303 is a hysteresis controller operative to apply adaptive hysteresis control so as to vary the hysteresis applied by the hysteretic comparator 201, i.e. the magnitude of the hysteresis. In the embodiment of FIG. 3 the transducer driving circuitry monitors the output signal S.sub.OUT from the comparator 201 and adjusts the applied hysteresis accordingly, for instance to maintain the cycle period in a defined range.

(47) The embodiment of FIG. 3 thus includes a Time-Decoding-Converter (TDC) 304 that receives the output PWM signal S.sub.OUT and determines a time parameter T.sub.X of the PWM output signal S.sub.OUT. The time parameter T.sub.X may be any parameter of the time PWM signal S.sub.OUT that varies with signal magnitude in a known way. Conveniently the time parameter T.sub.X may be the present cycle period T, although equally the time parameter could be the duration of a pulse of one output state, α or β, or the duty cycle α/T. This time parameter T.sub.X is provided to adaptive hysteresis controller 303, which controllably varies the hysteresis H.sub.X applied by the hysteretic comparator 201. There are many ways the magnitude of the hysteresis applied by a hysteretic comparator 201 may be varied as will be understood by one skilled in the art.

(48) As noted above in equation 4, the limit cycle period varies with the hysteresis H applied by the hysteretic comparator 201. The hysteresis controller 303 may thus controllably vary a value H.sub.X of the hysteresis applied by the hysteretic comparator 201 so as to reduce the amount of hysteresis applied as the magnitude of the input signal increases, as indicated by the time parameter T.sub.X, so as to maintain the cycle period, and hence the cycle frequency, within a defined range. Where the time parameter is the cycle period, the controller 303, i.e. the adaptive hysteresis controller, may reduce the amount of hysteresis as the time period T increases and vice versa in order to reduce the variation in the time period T by this feedback.

(49) In some instances the hysteresis may be generally controlled according to:
H.sub.MX=H.sub.0.(1−X.sub.e.sup.2)  (eqn. 6)
where H.sub.0 is the hysteresis applied at zero signal magnitude and X.sub.e is an estimate of the normalised signal X, derived from the time parameter. Then combining equations 3 and 5 and substituting for H.sub.M:

(50) $\begin{array}{cc}\begin{array}{c}T\approx 4\left(L/R\right).Math.H_x/\left(1-X^2\right)\\ =4\left(L/R\right).Math.H_0.Math.\left(1-X_{e^2}\right)/\left(1-X^2\right)\end{array}& \left(\mathrm{eqn}.7\right)\end{array}$

(51) Thus, assuming the estimate X.sub.e is an accurate estimate of the actual X, the last two terms cancel and
T≈T.sub.0≈4(L/R).H.sub.0  (eqn. 8)

(52) For economic but adequate hysteresis control a relatively accurate or precise indication of the level of the input signal may not be needed and it may be sufficient to determine the time parameter T.sub.X relatively crudely. The TDC 304 may, in some embodiments comprise a counter 305 which is clocked by a reference clock signal CLK. The counter 305 may be configured to determine at least one count value of the number of reference clock cycles in a portion of the cycle period corresponding to the relevant time parameter, for instance the counter 305 may count the number of reference clock cycles in each period between successive rising edges in the output signal S.sub.OUT and provide the cycle-by-cycle count value as the measure T.sub.X of the cycle period T, although in other implementations the count values may be used to determine the duty cycle or a count of the duration of one of the pulse, e.g. the duration α, may be sufficient. As mentioned for the hysteresis control, a high level of accuracy may not be needed and thus the reference clock signal CLK need only be fast enough to provide the required time resolution of the period or pulse length of the time encoded signal.

(53) The hysteresis controller 303 may be implemented as part of an integrated circuit 205 with the hysteretic comparator 201 and used to generate a driving signal S.sub.D for any of a range of different transducers. The hysteresis controller 303 may control the hysteresis to maintain the cycle period of the PWM signal S.sub.OUT in a range defined by a control setting C.sub.R.

(54) The speed and bandwidth of this hysteresis control loop, i.e. the TDC 304 and hysteresis controller 303 should be relatively high so that the circuit responds rapidly to any changes in cycle period.

(55) FIG. 5 illustrates a further embodiment in which similar components to those discussed previously are identified by the same reference numerals. The embodiment of FIG. 5 includes a hysteretic comparator 201 whose hysteresis H.sub.X is controlled by control block 303. In this embodiment the control block 303 is configured to accept an indication Dx of an estimate Xe of the signal to be driven, rather than a time parameter. This estimate Xe may be obtained from a module/circuitry upstream of the comparator signal input node 202, rather than from monitoring the comparator output at the PWM node 206. For instance, as illustrated in FIG. 5 a digital signal may be available from the signal path prior to an upstream digital-to-analogue converter (DAC) 501. The indication Dx may constitute a look-ahead signal that is derived from the signal path ahead of circuitry that has inherent delay and that is already in the signal path, such as the DAC 501. Alternatively and/or additionally, the indication Dx may constitute a look-ahead signal that is derived from the signal path ahead of a delay block/circuitry (not illustrated) that has purposely been introduced into the signal path. The purpose of the look ahead signal being to advantageously allow the control block 303 and comparator 201 time to react when the, otherwise delayed, input signal S.sub.IN arrives at the input (+) of the hysteretic comparator 201.

(56) In some embodiments the indication Dx input to the control block 303 may comprise all bits of a digital input signal D.sub.IN or may only comprise a number of the most significant bits (MSBs) that may still afford adequate resolution. The indication D.sub.x may also be a version of D.sub.IN at a different sample rate. Indication D.sub.x may be subject to some retiming to synchronise changes in the hysteresis value applied to the comparator to avoid changes in hysteresis on data changes of D.sub.x from causing immediate changes in comparator output, i.e. to avoid the comparator output edges becoming at least partly synchronised to the sample clock of D.sub.IN. However, in some embodiments the sample rate of D.sub.X and/or the DAC output may be high enough relative to the PWM pulse widths that the comparator switching is deliberately synchronised to a high speed sampling clock.

(57) The above description of the embodiments of FIG. 3 and FIG. 5 illustrate the transducer driving circuitry being arranged to drive a resistive load, i.e. the only significant impedance connected to output node 204, other than the inductance 203, is the resistance of transducer 301.

(58) In some instances with a resistive load 301 it may be beneficial to connect a capacitance to the output node 204. FIG. 6 illustrates transducer driving circuitry in which similar components to those discussed previously are identified by the same reference numerals. The capacitance may, in effect, be connected in parallel with the transducer 301. Where the hysteretic comparator 201 is implemented as at least part of an integrated circuit 205 some or all of this capacitance may be formed as part of the integrated circuit 205 as illustrated by capacitor 601 or some or all of this capacitance may be implemented as an off-chip component as illustrated by capacitor 601a.

(59) The capacitance 601 and/or 601a and inductance 203 in cooperation with the load resistance 301 may be regarded as applying a second-order filter, rather than a first-order LR filter as illustrated in the embodiments of FIGS. 2 and 3, to the variable duty-cycle square wave of voltage on node 206 so as to provide the waveform on output node 204. A second order filter may more strongly attenuate higher-frequency voltage components applied to the load, and thus the energy dissipated by such components in the load resistance may be less. Also higher-frequency electromagnetic emissions may be reduced. Also the value of inductance required in conjunction with a selected capacitance may be smaller, possibly by an order of magnitude, allowing a physically smaller and/or cheaper inductor to be used.

(60) The transducer illustrated in FIG. 3 or 5 may also present a more complex impedance to the driving circuitry than a pure resistance. For example an electrodynamic loudspeaker may have inductance and stray capacitance associated with a voice coil, and coil motion may induce back e.m.f. effects when driven, possibly including peaking due to mechanical resonances or mechanical or acoustic power dissipation that may be modelled by electrical equivalent circuits including further inductance and capacitance and resistances. However operation may still be qualitatively similar and/or these effects allowed for in the detailed design and component value choice.

(61) The transducer driving circuitry may also be implemented to drive a capacitive transducer load, as illustrated in FIG. 7. FIG. 7 illustrates transducer driving circuitry in which similar components to those discussed previously are identified by the same reference numerals.

(62) In this instance the transducer 701 may be a transducer that presents a capacitive load. Such a transducer may, for instance, be a piezoelectric transducer as may be used for ultrasonic emission or may be a haptic actuator or an electrostatic or MEMS loudspeaker. The transducer 701 may present a substantially capacitive load 702. However in practice since there is power being dissipated (vibrations/acoustic signals) by the transducer 701, this has to be reflected in an electrical equivalent circuit for the transducer 701, for instance by including a series resistance element 703a and/or parallel resistance element 703b as illustrated.

(63) A more complete model of the transducer 701 may need to include other effects such as mechanical resonances or mechanical or acoustic power losses that may be modelled by electrical equivalent circuits including further inductance and capacitance and resistances. However operation may still be qualitatively similar and/or these effects may be allowed for in the detailed design and/or component value choice.

(64) The principle of operation of the embodiment of FIG. 7 is essentially the same as described previously. Such an arrangement provides a very compact, simple and power efficient driver circuit for a capacitive acoustic output transducer.

(65) FIG. 7 also illustrates that the feedback path from the output node 204 to the second comparator input (−) may not be a direct connection. In this example the feedback path is coupled via a resistive voltage divider (704, 705). This is advantageous in that the comparator's input stage (not separately illustrated) and any upstream circuitry may operate from a relatively low supply voltage, for power efficiency and chip area and cost reasons. Conversely the transducer 701 may require a relatively high signal swing driving it in order to produce a strong enough output and therefore the comparator's output stage (not separately illustrated) may thus need special or large structures, e.g. transistors, to drive the transducer which consequently means the comparator's output stage needs a relatively high supply voltage. The potential divider allows the feedback signal S.sub.FB presented to the comparator's input stage to be within the range of the relatively low supply voltage of the comparator's input stage rather than being within the range of the relatively high supply voltage of the comparator's output stage.

(66) As noted above, in various embodiments the hysteretic comparator 201 may be formed as part of an integrated circuit, which could be an audio circuit such as a codec or the like or some other driver circuit. In an integrated circuit embodiment the circuit may include an adaptive hysteresis controller 303 to maintain the cycle period of the PWM output signal S.sub.OUT, and hence on ripple component of the driving signal S.sub.D within certain limits with a range of different transducers. The input signal S.sub.IN supplied to the hysteretic comparator 201 is a voltage signal and may comprise an analogue signal received at the integrated circuit or the integrated circuit may comprise a digital-to-analogue converter (DAC) to convert a received digital signal into the input signal S.sub.IN for the hysteretic comparator.

(67) In some embodiments however a transducer driving circuit may be implemented externally to an integrated circuit for providing the input signal S.sub.IN, that is to say the hysteretic comparator 201 may be provided as an off-chip component, for instance assembled or located on a PCB of the host device. FIG. 8 illustrates an embodiment where an integrated circuit 801, for instance an audio circuit 801 such as a codec or the like, outputs an analogue output signal A.sub.OUT at a terminal 802. A hysteretic comparator 201 is arranged as an off-chip component to receive the analogue output signal A.sub.OUT as the comparator input signal S.sub.IN. The output of the comparator is coupled to an off-chip inductor 203 with a feedback path from the other side of the inductor to the second input of the hysteretic comparator. The output node 204 of a transducer driving circuit comprising comparator 201 and inductor 203 is coupled to a transducer 803, which may be a purely resistive load, or a purely capacitive load (in which case there may be series resistance) or a mixed capacitive and resistive load.

(68) A hysteretic comparator can be readily implemented by a few off-chip components and the inductor may in any case be an off-chip component. Such a transducer driver circuit can thus be easily implemented as off-chip components, e.g. mounted on a printed circuit board or the like, and provides a simple and low cost way of driving a transducer.

(69) FIG. 9 illustrates one example of a simple hysteretic comparator circuit 201 with programmable hysteresis. MOS transistors M1 to M8 are arranged as a differential-input MOS comparator with a first input (IN+) and a second input (IN−). When used in embodiments of the transducer driving circuitry the first input (IN+) may receive the input signal S.sub.IN and the second input (IN−) may receive the feedback signal S.sub.FB. Bias current source 901 outputs a bias current IB to both input branches. The operation of the differential-input MOS comparator with bias source 901 would be such that, if the voltages at the first and second inputs IN+ and IN− were equal then (assuming, for simplicity of explanation, that all transistor widths and lengths are equal) each of the eight transistors M1 to M8 would pass a current equal to IB/2. In particular, transistors M8 and M6 would pass exactly the same current and node N1 will be ideally mid-way between the supply voltage VDD and a reference voltage, in this case ground. If the voltage at the first input IN+ increases relative to the voltage at the second input IN−, i.e. goes higher, the voltage on node N1 will go high. Conversely, if the voltage at the first input IN+ were to decrease below the voltage at the second input IN− the voltages at node N1 will go low. The voltage at node N1 is buffered to provide the output signal S.sub.OUT. The voltage at node N1 is buffered by series connected inverters INV1 and INV2 to provide output signals OUT1 and OUT2, where OUT2 is in phase with the voltage at node N2 and OUT1 is an inverted version. The output signal S.sub.OUT may be derived from the buffered output OUT2. Were the comparator implemented by transistors M1 to M8 operated just with bias source 901, the switching point, i.e. the point at which the comparator output would change state, would be the point at the voltages at the first and second input IN+ and IN− are equal. The operation of the comparator circuitry would be symmetric in that the change from low-to-high would occur at the same point as the change from high-to-low.

(70) In addition to this symmetric comparator circuitry, the hysteretic comparator circuit 201 includes current source 902 that outputs a current IH and switches S1 and S2 (typically implemented using MOS transistors). In operation, if OUT2 is high, indicating that voltage at the first input IN+ has been higher than that at the second input IN−, then switch S2 allows current IH to be injected into node N2. In order for both M3 and M4 to now pass equal current, (equal to (IB+IH)/2) then transistor M1 must carry a current equal to IB/2−IH/2 and transistor M2 must carry a current equal to IB/2+IH/2. Thus the switching point is now such that second input IN− must be at a significantly higher voltage than the first input IN+ rather than just equal (or very marginally greater).

(71) The amount of this hysteresis is dependent on the magnitude of IH and the transconductance of input transistors M1 and M2. It is greater for larger values of IH. Thus IH may be provided as a digitally programmable current source (e.g. comprising a plurality of MOS current sources in parallel, with bits of a digital word H.sub.[n] either turning each element on or off or steering the respective currents to N2 and/or N3.

(72) In some embodiments switches S1 and S2 may comprise multiple switches in parallel to a plurality of current sources of equal or say binary-weighted magnitudes, controlled by a logical combination of OUT, OUTB and H.sub.[n].

(73) Referring back to FIG. 8 the analogue output signal A.sub.OUT may be provided by a simple DAC 804 on the integrated circuit 801 although in some instances there may be an on chip amplifier 805. In some instances the output 802 of the driver circuit 801 could be multiplexed between the input to the hysteretic comparator 201, for driving the on-board transducer 803, or a second signal path, which may for instance be a signal path for connecting to an accessory device via a suitable contact 807 of a device connector.

(74) It will be understood that in embodiments of the disclosure the input signal S.sub.IN of interest is a signal with some time varying signal component that comprises some information content for driving an acoustic transducer. Note that as used herein the term acoustic shall be used to refer to transducers that operate by generating some pressure wave or vibration as the output. The term acoustic shall not be taken to imply any particular frequency range and is not used restricted to producing sound in the human audible hearing range. The term audio is also not restricted to frequencies in the human audible hearing range and the term audio shall be used to include ultrasonic frequencies and signals for driving haptic transducers.

(75) Thus the input signal S.sub.IN is not a reference voltage having a constant level or having some defined variation that does not vary from cycle-to-cycle, e.g. a triangular waveform or the like. The input signal S.sub.IN may, for instance, be a time varying voltage signal. In some implementations the input signal S.sub.IN could, for example, be an analogue input signal such as an analogue audio signal or an analogue signal derived from an audio signal. Likewise, the driving signal S.sub.D is thus a time varying signal that comprises some information content for driving an acoustic transducer to reproduce the content. The output signal is not simply a power supply for the transducer.

(76) The skilled person will thus recognise that some aspects of the above described apparatus and methods may be embodied as processor control code, for example on a non-volatile carrier medium such as a disk, CD- or DVD-ROM, programmed memory such as read only memory (Firmware), or on a data carrier such as an optical or electrical signal carrier. For many applications, embodiments of the present invention will be implemented on a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). Thus the code may comprise conventional program code or microcode or, for example, code for setting up controlling an ASIC or FPGA. The code may also comprise code for dynamically configuring re-configurable apparatus such as re-programmable logic gate arrays. Similarly, the code may comprise code for a hardware description language such as Verilog™ or VHDL. As the skilled person will appreciate, the code may be distributed between a plurality of coupled components in communications with one another. Where appropriate, the embodiments may also be implemented using code running on a field-(re)programmable analogue array or similar device in order to configure analogue hardware.

(77) Some embodiments of the present invention may be arranged as part of an audio processing circuit, for instance an audio circuit which may be provided in a host device. A circuit according to an embodiment of the present invention may be implemented as an integrated circuit. One or more output transducers may be connected to the integrated circuit in use.

(78) Embodiments of the present invention may be implemented in a host device, especially a portable and/or battery powered host device such as a mobile telephone, an audio player, a video player, a PDA, a mobile computing platform such as a laptop computer or tablet and/or a games device, for example.

(79) It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in the claim, “a” or “an” does not exclude a plurality, and a single feature or other unit may fulfil the functions of several units recited in the claims. Any reference numerals or labels in the claims shall not be construed so as to limit their scope. Terms such as amplify or gain include possibly applying a scaling factor or less than unity to a signal.