Imaging sensor and pixel structure for simultaneous imaging and energy harvesting

Abstract

An energy harvesting imaging sensor includes an array of pixel structures each formed from a semiconductor having a photodiode overlying a photovoltaic diode. The photodiode and photovoltaic diode are implemented as a vertically stacked P+/N.sub.WELL/P.sub.SUB junction. This structure enables simultaneous imaging and energy harvesting by generating charge in the photodiode that is indicative of light impinging on the photodiode and simultaneously generating charge from the light in the photovoltaic diode located underneath the photodiode.

Claims

1. An imaging sensor, comprising: a substrate; a pixel array comprising a plurality of pixel structures formed on the substrate, wherein each of the pixel structures includes a P+/N.sub.WELL/P.sub.SUB junction forming a first, photodiode overlying a second, photovoltaic diode.

2. The imaging sensor set forth in claim 1, wherein the P+/N.sub.WELL/P.sub.SUB junction of each of the pixel structures forms the photodiode and the photovoltaic diode as a pair of cathode-connected diodes with the photodiode having a P+ layer forming an anode located at an upper portion of the pixel structure and an N.sub.WELL layer forming a cathode underlying the P+ layer, and with the photovoltaic diode having the N.sub.WELL layer forming a cathode of the photovoltaic diode and a P.sub.SUB layer forming an anode of the photovoltaic diode that is located at a lower portion of the pixel structure underlying the N.sub.WELL layer.

3. The imaging sensor set forth in claim 2, wherein the anode of the photodiode includes a first electrode and wherein each of the pixel structures includes readout circuitry connected to the first electrode, and wherein the pixel structure further includes a second electrode connected to the photovoltaic diode.

4. The imaging sensor set forth in claim 3, further comprising a voltage output terminal supported by the substrate, wherein the second electrodes of each of the pixel structures are electrically coupled to the output terminal so as to provide harvested electrical energy to the output terminal.

5. The imaging sensor set forth in claim 4, further comprising a voltage input terminal supported by the substrate and coupled to the pixel array to provide operating power to the imaging sensor from an external power supply that converts the harvested electrical energy from the output terminal into the operating power received at the input terminal.

6. The imaging sensor set forth in claim 5, wherein the anode of the photovoltaic diode is connected to the second electrode to supply the harvested electrical energy to the output terminal, wherein the pixel structure includes an N+ region formed in the N.sub.WELL layer at the upper portion of the pixel structure adjacent the layer, and wherein the N+ region is connected to a bias voltage source that provides positive voltage to the cathode of the photovoltaic diode to thereby reverse bias the photovoltaic diode.

7. The imaging sensor set forth in claim 3, wherein the pixel structure includes an N+ region formed in the N.sub.WELL layer at the upper portion of the pixel structure adjacent the P+ layer, wherein the second electrode is connected to the N+ region, and wherein the anode of the photovoltaic diode is connected to a circuit ground.

8. The imaging sensor set forth in claim 3, wherein each of the pixel structures includes reset circuitry connected to the first electrode.

9. The imaging sensor set forth in claim 1, wherein each of the pixel structures includes readout circuitry and wherein the imaging sensor further comprises a column read circuit connected to the pixel readout circuitry, wherein the column readout circuit includes an analog to digital converter (ADC) that detects a voltage level provided by the photodiode, a resettable counter that provides a digital value indicative of the detected voltage level, and a latch that stores the digital value at least until the digital value is read out from the latch.

10. The imaging sensor set forth in claim 1, wherein each pixel structure includes readout circuitry and pixel circuitry that together comprise a 3T pixel formed from PMOS transistors inside the N.sub.WELL.

11. An energy harvesting imaging sensor comprising an array of P+/N.sub.WELL/P.sub.SUB junctions each forming a vertically stacked photodiode and photovoltaic diode pair.

12. An energy harvesting pixel imaging structure comprising a semiconductor having a photodiode overlying a photovoltaic diode.

13. The imaging sensor set forth in claim 12, wherein the semiconductor is a complementary metal-oxide semiconductor.

14. The imaging sensor set forth in claim 12, wherein the photodiode and photovoltaic diode together comprise a vertically stacked P+/N.sub.WELL/P.sub.SUB junction.

15. A method of simultaneous imaging and energy harvesting, comprising the steps of generating charge in a photodiode indicative of light impinging on the photodiode and simultaneously generating charge from the light in a photovoltaic diode located underneath the photodiode.

16. The method of claim 15, wherein the steps of generating charge further comprise generating the charge using a P+/N.sub.WELL/P.sub.SUB junction.

17. The method of claim 15, wherein the photodiode and photovoltaic diode form a portion of a pixel structure having a readout circuit, and wherein the method further comprises carrying out the charging steps at each of a plurality of said pixel structures formed into an array.

18. The method of claim 17, further comprising the steps of: accumulating the charge from the photodiodes at each pixel structure in the array, providing the charge from the photovoltaic diodes of each of the pixel structures to a power management circuit, receiving operating power from the power management circuit that was generated using the charge from the photovoltaic devices, and reading out the accumulated charge at each of the pixel structures using the readout circuit that is powered using the operating power received from the power management circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) One or more embodiments of the invention will hereinafter b described in conjunction with the appended drawings, wherein like designations denote like elements, and wherein:

(2) FIG. 1A is a diagram of an imaging sensor and external power management circuit constructed in accordance with an embodiment of the invention;

(3) FIG. 1B is a schematic diagram of one embodiment of a pixel structure that includes a photodiode and photovoltaic diode and that may be used in the imaging sensor of FIG. 1A;

(4) FIG. 1C is a schematic diagram of another embodiment of a pixel structure that includes a photodiode and photovoltaic diode and that may be used in the imaging sensor is of FIG. 1A;

(5) FIG. 1D shows the relative functions of the photodiodes and photovoltaic diodes in the pixel structures used in the imaging sensor of FIG. 1A;

(6) FIG. 2 depicts the pixel structure of FIG. 1B along with a column read circuit;

(7) FIG. 3 depicts the pixel structure of FIG. 1C along with a column read circuit;

(8) FIG. 4 is a graph of the timing diagram of the inputs and outputs for the pixel structures of FIGS. 2 and 3;

(9) FIGS. 5 and 6 show the measured harvested power and power dissipation of a prototype imaging sensor as a function of illumination levels for each pixel structure of FIGS. 2 and 3; and

(10) FIG. 7 is a table comparing the performance of the prototype imaging sensor with two known multiplexing imaging/energy harvesting devices.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

(11) Described below are embodiments of a method and device for providing self-sustainable CMOS image sensing with concurrent energy harvesting without additional area penalty of photodiodes or the degradation of energy-harvesting efficiency as are experienced with known techniques. The proposed pixel structures described below utilize two vertically-stacked diodes realized in the same pixel using a conventional CMOS fabrication process: one diode for hole-accumulation photodiode (P+/N.sub.WELL) inside the N-well and the other diode for the photovoltaic energy harvesting diode (N.sub.WELL/P.sub.SUB) below the N-well.

(12) FIG. 1A depicts an imaging sensor 10 with an external power management circuit 12 that receives harvested electrical charge from the imaging sensor 10 and stores and conditions it into the voltage supply(ies) needed to run the imaging sensor. The imaging sensor 10 is a semiconductor device that includes a substrate 14 containing at least one input 16 (V.sub.IN) and at least two outputs 18 (V.sub.EH) and 20 (DATA), all of which may be formed as terminals on the substrate 14. Formed on the substrate 14 using a CMOS fabrication process is a pixel array 22 containing an n×m array of pixel structures 24 (also referred to simply as pixels), two examples of which are shown generally in FIGS. 1B and 1C. These will be described in greater detail below in connection with FIGS. 2 and 3. Also formed on the substrate 14 are additional CMOS circuits including a row scanner 26 and column scanner 28, analog-to-digital converter (ADC) 30 run by a ramp signal generator 32, a counter 34, and a latch 36 that temporarily stores bytes of imaging data until output via the DATA output 20. These additional circuits 26-36 may be implemented in various ways as are known to those skilled in the art, including by the use of conventional circuits that may be fabricated onto the substrate 14.

(13) FIGS. 1B and 1C depict circuit diagrams for two different embodiments 23, 25 either of which may be used to form the pixel structures 24. Each pixel structure includes a photodiode (D.sub.P1, D.sub.P3) for imaging and a photovoltaic diode (D.sub.P2, D.sub.P4) for energy harvesting. Contrary to typical CMOS image sensors, these two diodes, D.sub.P1 and D.sub.P3, accumulate holes, not electrons. Holes generated by incident light are drifted to and collected in the anode of the diode. In a pixel structure 23, D.sub.P1 forms a 3T pixel with M.sub.P1, M.sub.P2 and reset transistor (M.sub.P3), accumulating photocurrent in VPDI during integration time. D.sub.P2 continuously harvests energy from impinging light without any interruption, producing the photovoltage at V.sub.EH1. In the pixel structure 25, D.sub.P3 forms a 3T pixel with M.sub.P4, M.sub.N2 and reset transistor (M.sub.N1), which collect the generated photocurrent in V.sub.PD2 during integration time. D.sub.P4 continuously collects electrons to harvest energy without any interruption, and thus with impinging light will continually produce the negative photovoltage at V.sub.EH2. Column-parallel 8-b singleslope (SS) ADCs 18 operate in the delta-reset sampling mode with a bi-directional ramp signal generator and an 8-b counter 34 for image capturing at low power. FIG. 1D depicts the relative functions of the photodiode and photovoltaic diode in the pixel structures 24.

(14) FIGS. 2 and 3 show the pixel cross-section and the readout circuitry for the two different pixel structures 23 and 25, respectively. Both pixel structures include a P+/N.sub.WELL/P.sub.SUB junction forming a first, photodiode (D.sub.P1 and D.sub.P3) overlying a second, photovoltaic diode (D.sub.P2 and D.sub.P4). The stacked vertical junction structure of P+/N.sub.WELL/P.sub.SUB forms these diodes as a pair of cathode-connected diodes with the photodiodes DPI and DPS having a P+ layer forming an anode located at an upper portion of the pixel structure and an N.sub.WELL layer forming a cathode underlying the P+ layer. The photovoltaic diodes D.sub.P2 and D.sub.P4 have the N.sub.WELL, layer forming a cathode of the photovoltaic diode and a P.sub.SUB layer forming an anode of the photovoltaic diode that is is located at a lower portion of the pixel structure underlying the N.sub.WELL layer. In both pixel structures 23 and 25, the N.sub.WELL layer is formed in (surrounded by) the P.sub.SUB layer which extends from the lower portion of the pixel structure to the upper portion of the pixel structure about the periphery of the N.sub.WELL layer. This provides for an electrical path from the photovoltaic diode D.sub.P2 and D.sub.P4 to the upper portion of the pixel structure where holes generated in the P.sub.SUB layer can migrate and be used for supplying the harvested energy from the pixel structure.

(15) In the pixel structure 23 of FIG. 2, the semiconductor includes an N+ region formed at the upper portion of the pixel structure in the N.sub.WELL layer, and further includes a P+ region formed in the Mint layer at the upper portion. As shown, the P+ region provides a ground reference while the N+ region provides an external connection to the diodes' cathodes that permits application of a positive voltage V.sub.DC that reverse biases the photovoltaic diode D.sub.P2, thereby increasing the width of the depletion region and improving energy harvesting efficiency. The pixel structure 23 also includes a P+ region formed at the upper portion of the pixel structure in a portion of the P.sub.SUB layer that forms a P.sub.WELL at a location laterally adjacent the N.sub.WELL layer. This provides an anode connection for the photovoltaic diode D.sub.P2 to which the holes generated in the P.sub.SUB layer can migrate so as to supply harvested energy from the pixel structure. There are thus four patterned regions at the upper portion of the pixel structure: the P+ anode of the photodiode D.sub.P1, the N+ cathode of the diodes D.sub.P1 and D.sub.P2, the P+ anode of the photovoltaic diode layer D.sub.P2 that supplies harvested charge, and the P+ ground connection, Each of these four regions may include a metal layer electrode (47-50) overlying the region for external connection via patterned traces on the semiconductor. The electrode 48 for the photodiode anode may be, for example, a ring electrode that provides an open region of the P+ layer to receive impinging light, or an overlying transparent electrode such as may be formed from indium tin oxide (ITO).

(16) In the pixel structure 25 of FIG. 3, the semiconductor includes an N+ region formed at the upper portion of the pixel structure in the N.sub.WELL layer, and further includes a P+ region formed at the upper portion of the pixel structure in a P.sub.WELL, portion of the P.sub.SUB layer at a location laterally adjacent the N.sub.WELL layer. With this P+ region connection to ground, the common-cathode connection provided by the N+ region permits conduction of the harvested energy. Each of these doped regions at the upper portion of the pixel is structure 25 may include an electrode (51-53) for low resistance connection to the remainder of the imaging sensor circuitry, as noted above in connection with the pixel structure 23 of FIG. 2.

(17) Regardless of which one (or both) of the pixel structures 23 and 25 are used in the imaging sensor 10 of FIG. 1, the electrodes supplying the harvested energy V.sub.EH1 and V.sub.EH2 shown in FIGS. 2 and 3 are electrically coupled to the V.sub.EH output 18, and this can be done in various ways such as by a direct electrical connection of the electrodes V.sub.EH1, V.sub.EH2 to that output terminal 18 or by OR-tying the electrodes to the output terminal using steering diodes. The harvested energy supplied to output terminal 18 may then be used by the external power management circuit 12 which stores the charge, boosts the voltage level if needed, and provides a regulated and filtered supply of operating power to the imaging sensor 10 for running its circuitry, including V.sub.DD as well as the bias voltage V.sub.DC used in the pixel structure 23.

(18) Each pixel structure 23 and 25 includes readout circuitry 40 and 42, respectively, as well as a reset circuit 44 and 46, respectively. The readout circuitry is connected to the electrode of the P+ anode region of the photodiode D.sub.P1 and D.sub.P3 to accumulate photon-induced charge (holes) generated in the N.sub.WELL depletion region. That electrode is connected to the gate of an input transistor (M.sub.P1 and M.sub.P4), which is a part of the comparator circuit for the singleslope ADC 30. During readout, the level of accumulated charge is sensed when the pixel is selected by the row scanner 26 and column scanner 28, and this readout is done by the column readout circuitry that comprises the ADC 30 and its signal generator 32, counter 34, and the latch 36 which is connected to the 8-b image DATA output terminal 20. For resetting the photodetector signal at the pixel structure 23, 25, the P+ diffusion layer (anode of the D.sub.P1 and D.sub.P3) is connected to the reset transistor (M.sub.P3 and M.sub.N1) that comprises the reset circuitry 44, 46, respectively.

(19) In the pixel structure 23, the peripheral transistors of the readout and reset circuitry 40, 44 (M.sub.P1, M.sub.P2 and M.sub.P3) are implemented as PMOS transistors inside the N.sub.WELL. This results in a high till factor of 47% for D.sub.P1. Moreover, the energy harvesting efficiency can be greatly enhanced by using the entire N-well area realized by the N.sub.WELL/P.sub.SUB diode (D.sub.P2). D.sub.P2 can achieve a near perfect fill factor (>94%) in a small pixel of 5 um×5 um. In the pixel structure 25, D.sub.P4 collects the electrons to harvest the energy. Comparing the pixel structure 23, the harvested electrons drift through N.sub.WELL, which can show relatively low series resistance to V.sub.EH2 node due to the higher doping concentration than the P.sub.SUB layer in the pixel structure 23. In addition, it should be noted that the amount of photo-generated charges are not only determined by the area of the diode but also the depletion width. The P.sub.SUB and N.sub.WELL areas are lightly doped as compared to P+ or N+ regions. Therefore, a larger depletion width can be formed in D.sub.P2 and D.sub.P4, resulting in a higher energy harvesting efficiency. When the incident light reaches the depletion regions of D.sub.P1 and D.sub.P3, the holes are generated and drifted to the anode. The accumulated holes in D.sub.P1 and D.sub.P3 during the integration time will be read out for image captures, using the two transistors in the each pixel structure with other two transistors in the column (M.sub.C1, M.sub.C2) as a differential pair in the comparator for SS ADC 18 and sharing the COM node and SIG1 node in the same column. A the same time, the accumulated holes in D.sub.P2 are used for energy harvesting, supplying the photovoltage at V.sub.EH1. The generated electrons in D.sub.P4 are supplying negative photovoltage at V.sub.EH2.

(20) It will this be understood that the imaging sensor 10, using either of the energy harvesting pixel imaging structures described above, can be used to carry out a method of simultaneous imaging and energy harvesting. This method includes the steps of generating charge in a photodiode (e.g., D.sub.P1 or D.sub.P3) indicative of light impinging on the photodiode and simultaneously generating charge from the light in a photovoltaic diode (e.g., D.sub.P2 or D.sub.P4) located underneath the photodiode. And, more specifically, that this photodetection and energy harvesting charge can be generated using a P+/N.sub.WELL/P.sub.SUB junction, Where this pixel structure is one of a multitude of such structures integrated as a semiconductor array with readout circuitry, then the method may further comprise the steps of: accumulating the charge from the photodiodes at each pixel structure in the array, providing the charge from the photovoltaic diodes of each of the pixel structures to a power management circuit; receiving operating power from the power management circuit that was generated using the charge from the photovoltaic devices, and reading out the accumulated charge at each of the pixel structures using the readout circuit that is powered using the operating power received from the power management circuit.

(21) A timing diagram for imaging and energy harvesting is shown in FIG. 4. Impinging (incident) light on the photodiode starts generating electron/hole pairs. In the pixel structure 23, the voltage of energy harvesting node (V.sub.EH1) increases during the start-up phase, and the combined output from the V.sub.EH1 pixel nodes is supplied to the external is energy harvest (EH) power management circuit 12 via V.sub.EH output terminal 18. When this combined output at terminal 18 reaches a trigger voltage, the power management circuit 12 starts supplying power back to the imaging sensor 10 via terminal 16 and thus, to the individual pixel structures 24 in the array 22. The image capture and readout may then start. In the pixel structure 25, the voltage of energy harvesting node (V.sub.EH2) decreases due to the harvested electrons flowing to V.sub.EH output terminal 18 during the start-up phase. The harvested voltage is inverted to positive voltage using the power management circuit 12 which can generate supply voltage by boosting up from the inverted harvesting voltage, as is known.

(22) The image capture operation of both pixel structures is conducted as follows: (1) CNT.sub.RST signal resets the code of the counter to 2.56; (2) V.sub.RAMP starts decreasing to capture the D.sub.P1 and D.sub.P3 signal level (V.sub.PD1, V.sub.PD2); (3) when V.sub.RAMP reaches the D.sub.P1 and D.sub.P3 signal level; the counter latched the code corresponding to V.sub.PD1 and V.sub.PD2; (4) after resetting the photodiode (D.sub.P1, D.sub.P3), V.sub.RAMP starts increasing to detect the reset signal level of D.sub.P1 and D.sub.P3; (5) when V.sub.RAMP reach the D.sub.P1 reset signal level, the counter latch the code equivalent to (V.sub.SIG−V.sub.RST). By employing the bi-directional ramp signal for delta-reset sampling operation, any fixed pattern noise (FPN) induced by variations and mismatches of M.sub.P3 and M.sub.P4 may be suppressed.

(23) A prototype imaging sensor was constructed using each of the pixel structures 23 and 25, and performance was measured with LSH-7320 LED Solar Simulator (Oriel Instrument). FIGS. 5 and 6 show the measured harvested power, and power dissipation of the sensor as a function of illumination levels for each pixel structure 23 and 25, respectively. When the illumination is higher than 1 klux, the harvested supply voltage can reach higher than 0.33V, which is sufficient to start up and operate the external EH power management circuit. The Voc of the two devices are saturated at about 0.45 V and the ISC is proportional to the illumination levels. In the pixel structure 23, the harvested energy is sufficient to continuously supply the required power of 3.9 uW at 7.5 fps of image capture to under 20 klux (normal daylight) and 10.08 uW at 15 fps under 50 klux (sunny daylight), respectively. In the pixel structure 25, the harvested energy can provide continuously required power of 4.0 uW at 7.5 fps under 70 klux (normal daylight).

(24) The performance comparison of imaging sensors using the two pixel structures relative to the devices of Cevik and Chiou is summarized in FIG. 7. The fabricated pixel structures disclosed herein accomplished a figure of merit (FOM) of 57.78 pJ/pixel and 74.67 pJ/pixel at 7.5 fps and 1.5 fps in the image capturing circuits for the pixel structure 23 and 59.2 pJ/pixel and 81.6 pJ/pixel at 7.5 fps and 15 fps for pixel structure 25. Thus, harvest a power level of 998 pW/klux/mm.sup.2 can be harvested from the pixel structure 23 and 217 pW/klux/mm.sup.2 from the pixel structure 25, respectively. This result indicates the CMOS image sensor with the proposed pixel structures show the self-sustainable image-capture operation without requiring a battery or other external source of electrical power.

(25) It is to be understood that the foregoing is a description of one or more embodiments of the invention. The invention is not limited to the particular embodiment(s) disclosed herein, but rather is defined solely by the claims below. Furthermore, the statements contained in the foregoing description relate to particular embodiments and are not to be construed as limitations on the scope of the invention or on the definition of terms used in the claims, except where a term or phrase is expressly defined above. Various other embodiments and various changes and modifications to the disclosed embodiment(s) will become apparent to those skilled in the art. For example, instead of the P+/N.sub.WELL/P.sub.SUB junction, an N+/P.sub.WELL/DN.sub.WELL junction could be used with the N+/P.sub.WELL diode used for capturing the image and the P.sub.WELL/DN.sub.WELL photovoltaic diode used for energy harvesting. The construction and use of the N+/P.sub.WELL/DN.sub.WELL junction will be apparent to those skilled in the art. All such other embodiments, changes, and modifications are intended to come within the scope of the appended claims.

(26) As used in this specification and claims, the terms “e.g.,” “for example,” “for instance,” “such as,” and “like,” and the verbs “comprising,” “having,” “including,” and their other verb forms, when used in conjunction with a listing of one or more components or other items, are each to be construed as open-ended, meaning that the listing is not to be considered as excluding other, additional components or items. Other terms are to be construed using their broadest reasonable meaning unless they are used in a context that requires a different interpretation. In addition, the term “and/or” is to be construed as an inclusive OR. Therefore, for example, the phrase “A, B, and/or C” is to be interpreted as covering all of the following: “A” “B”; “C” “A and B”; “A and C”; “B and C”; and “A, B, and C.”