Lighting system with power factor correction control data determined from a phase modulated signal

Abstract

A light emitting diode (LED) lighting system includes a power factor correction (PFC) controller that determines at least one power factor correction control parameter from phase delays of a phase modulated signal. In at least one embodiment, a peak voltage of the phase modulated signal is a PFC control parameter used by the PFC controller to control power factor correction and generation of a link voltage by a PFC LED driver circuit. The phase delays are related to a peak voltage of the phase modulated signal. Thus, in at least one embodiment, detecting the phase delay in one or more cycles of the phase modulated signal allows the PFC controller to determine the peak voltage of the phase modulated signal.

Claims

1. A light emitting diode (LED) lighting system comprising: a controller comprising: an input to receive a phase delay signal indicating a phase delay of a phase modulated dimmer signal; and a signal processor, coupled to the input, to receive the phase delay signal and determine a control operating parameter from the phase delay signal and to generate a switch control signal using the determined operating parameter to vary an input current to a switching power converter with a phase modulated voltage and to maintain a regulated link voltage at an approximately constant value until a duty cycle of the control signal decreases to a predetermined threshold value and to decrease the regulated link voltage of the switching power converter when the duty cycle of the control signal decreases to the predetermined duty cycle threshold value.

2. The LED lighting system of claim 1 further comprising: the switching power converter coupled to the controller; and a load coupled to the switching power converter, wherein the load includes one or more light emitting diodes.

3. The LED lighting system of claim 2 further comprising a time-based phase delay detector to detect the phase delay of the phase modulated signal and generate the phase delay signal as a digital signal.

4. The LED lighting system of claim 2 wherein the operating parameter is a peak voltage of the phase modulated dimmer signal.

5. The LED lighting system of claim 2 wherein the phase delay signal indicates a dimming level and the controller is further configured to generate a switch control signal to cause the switching power converter to respond to the dimming level indicated by the signal without decreasing an effective resistance of the switching power converter, as perceived by a voltage source of the switching power converter, as the dimming level indicated by the signal increases.

6. The LED lighting system of claim 2 wherein the controller is further configured to generate approximately constant pulse widths for the switch control signal during each cycle of phase modulated signal when a duty cycle of switch control signal is below the predetermined duty cycle threshold value.

7. The LED lighting system of claim 2 wherein the controller is further configured to generate pulses for the switch control signal during the phase delays of the phase modulated signal, wherein the pulse widths and duty cycles of the pulses of the switch control signal generated during the phase delays are sufficient to attenuate ripple of the phase modulated signal during the phase delays of phase modulated signal.

8. The LED lighting system of claim 7 wherein the pulses of switch control signal generated during the phase delays have a period significantly greater than a period of the pulses of the switch control signal during an active period of phase modulated signal.

9. A method of controlling a light emitting diode (LED) lighting system, the method comprising: receiving a phase delay signal indicating a phase delay of a phase modulated dimmer signal; determining a control operating parameter from the phase delay signal using a signal processor; and generating a duty cycle modulated switch control signal using the determined operating parameter to vary an input current to a switching power converter with a phase modulated voltage and to maintain a regulated link voltage at an approximately constant value until a duty cycle of the switch control signal decreases to a predetermined threshold value and to decrease the regulated link voltage of the switching power converter when the duty cycle of the switch control signal decreases to the predetermined duty cycle threshold value.

10. The method of claim 9 further comprising: receiving the switch control signal at a terminal of a switch in the switching power converter; converting the phase modulated dimmer signal into the regulated link voltage; and providing power to a load coupled to the switching power converter, wherein the load includes one or more light emitting diodes.

11. The method of claim 10 further comprising: detecting the phase delay of the phase modulated signal using a time-based phase delay detector; and generating the phase delay signal as a digital signal.

12. The method of claim 10 wherein the operating parameter is a peak voltage of the phase modulated dimmer signal.

13. The method of claim 10 wherein the phase delay signal indicates a dimming level, the method further comprising: generating the switch control signal to cause the switching power converter to respond to the dimming level indicated by the signal without decreasing an effective resistance of the switching power converter, as perceived by a voltage source of the switching power converter, as the dimming level indicated by the signal increases.

14. The method of claim 10 further comprising: generating approximately constant pulse widths for the switch control signal during each cycle of phase modulated signal when a duty cycle of switch control signal is below a predetermined threshold.

15. The method of claim 10 further comprising: generating pulses for the switch control signal during the phase delays of the phase modulated signal, wherein the pulse widths and duty cycles of the pulses of the switch control signal generated during the phase delays are sufficient to attenuate ripple of the phase modulated signal during the phase delays of phase modulated signal.

16. The method of claim 15 wherein the pulses of switch control signal generated during the phase delays have a period significantly greater than a period of the pulses of the switch control signal during an active period of phase modulated signal.

17. A light emitting diode (LED) lighting system comprising: a controller comprising: an input to receive a phase delay signal indicating a phase delay of a phase modulated dimmer signal; and a signal processor, coupled to the input, to receive the phase delay signal and determine a control operating parameter from the phase delay signal and to generate a switch control signal using the determined operating parameter to control an input current in response to one or more values of the phase delay signal; and wherein the controller is further configured to decrease a duty cycle of the switch control signal as the dimming level decreases until the dimming level reaches a dimming level threshold and to keep the duty cycle of the switch control signal approximately constant for dimming levels below the dimming level threshold.

18. The lighting system of claim 17 further comprising a time-based phase delay detector to detect the phase delay of the phase modulated signal and generate the phase delay signal as a digital signal.

19. A light emitting diode (LED) lighting system comprising: a controller comprising: an input to receive a phase delay signal indicating a phase delay of a phase modulated dimmer signal; and a signal processor, coupled to the input, to receive the phase delay signal and determine a control operating parameter from the phase delay signal and to generate a switch control signal using the determined operating parameter to control an input current in response to one or more values of the phase delay signal; wherein the controller is further configured to increase an effective resistance of the switching power converter as the dimming level indicated by the dimming signal decreases.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the several figures designates a like or similar element.

(2) FIG. 1 (labeled prior art) depicts a lighting system with a power factor correction driver circuit and controller.

(3) FIG. 2A (labeled prior art) depicts various waveforms present in the lighting system of FIG. 1.

(4) FIG. 2B (labeled prior art) depicts an LED driver circuit with dimmer switch compatibility circuits.

(5) FIG. 2C (labeled prior art) depicts another LED driver circuit with dimmer switch compatibility circuitry.

(6) FIG. 3 depicts a light emitting diode lighting system with a power factor correction controller that derives one or more power factor correction control parameters from a phase modulated signal.

(7) FIGS. 4 and 5 depict phase modulated signals having various leading and trailing edge phase delays.

(8) FIG. 6 depicts a phase delay detector.

(9) FIG. 7 depicts exemplary phase modulated signal and associated PFC switch control signal waveforms.

(10) FIG. 8 depicts an effective resistance model of a PFC LED driver circuit.

(11) FIG. 9 depicts relationships between a phase modulated signal and an inductor current with and without dimming.

(12) FIG. 10 depicts a relationship between duty cycles of a PFC switch control signal and a link voltage.

(13) FIGS. 11 and 12 depict LED apparatuses.

DETAILED DESCRIPTION

(14) A light emitting diode (LED) lighting system includes a power factor correction (PFC) controller that determines at least one power factor correction control parameter from phase delays of a phase modulated signal. In at least one embodiment, a peak voltage of the phase modulated signal is a PFC control parameter used by the PFC controller to control power factor correction and generation of a link voltage by a PFC LED driver circuit. The phase delays are related to a peak voltage of the phase modulated signal. Thus, in at least one embodiment, detecting the phase delay in one or more cycles of the phase modulated signal allows the PFC controller to determine the peak voltage of the phase modulated signal.

(15) The PFC LED driver circuit supplies an output current to drive LED(s) of an LED apparatus. As the dimming level decreases, the PFC controller decreases a duty cycle of a PFC switch in the PFC LED driver circuit to cause the PFC LED driver circuit to decrease the output current supplied to the LEDs. When the phase modulated signal indicates a dimming level below a threshold value, the PFC controller maintains an approximately constant duty cycle of the PFC switch to, for example, maintain switching efficiency without significantly sacrificing power factor correction.

(16) In at least one embodiment, PFC controller generates a PFC switch control signal to cause the PFC LED driver circuit to respond to decreasing dimming levels as indicated by a dimming signal, such as the phase modulated signal, without decreasing an effective resistance of the PFC LED driver circuit, as perceived by a voltage source of the PFC LED driver circuit, as the dimming level indicated by the dimming signal increases. The phase modulated signal represents one embodiment of the dimming signal.

(17) In at least one embodiment, the PFC controller generates a duty cycle modulated control signal to control a regulated link voltage of the PFC LED driver circuit and decreases the link voltage when a duty cycle of the control signal decreases to a value between zero and a duty cycle threshold value.

(18) In at least one embodiment, the PFC controller generates approximately constant pulse widths for the PFC switch control signal during each cycle of phase modulated signal when a duty cycle of PFC switch control signal is below a predetermined threshold.

(19) In at least one embodiment, the PFC controller generates pulses for the PFC switch control signal during the phase delays of phase modulated signal, wherein the pulses of PFC switch control signal generated during the phase delays have a period significantly greater than a period of the pulses of PFC switch control signal during an active period of phase modulated signal.

(20) FIG. 3 depicts a lighting system 300 having a PFC controller 302 and a PFC LED driver circuit 304. The PFC controller 302 generates a duty cycle modulated PFC switch control signal CS.sub.1 to control the conductivity of switch 306. Switch 306 can be any switch, and, in at least one embodiment, switch 306 is an n-channel field effect transistor (FET). The PFC LED driver circuit 304 is a switching power converter that boosts the phase modulated signal V.sub. to a link voltage V.sub.C1 across hold-up capacitor 308. In at least one embodiment, the link voltage V.sub.C1 has a peak voltage in the range of 200V-400 V. When switch 306 is OFF (i.e. non-conductive), diode 310 is forward biased, and inductor 312 drives inductor current i.sub.L1 through diode 310. The inductor current i.sub.L1 through diode 310 charges capacitor 308 to maintain an approximately constant link voltage V.sub.C1. When switch 306 is ON (i.e. conductive), the voltage across inductor 312 reverses, diode 310 is reverse biased, and the inductor 312 energizes with the current i.sub.L1. PFC controller 302 controls the duty cycles of PFC switch control signal CS.sub.1 and switch 306 so that current i.sub.L1 is proportional to phase modulated signal V.sub.. Capacitor 314 provides filtering to smooth drive current i.sub.L1 so that the average drive current i.sub.L1 is sinusoidal and in phase with phase modulated signal V.sub..

(21) The PFC controller 302 includes a digital signal processor 316 to perform various operations including determining the pulse width and duty cycle of PFC switch control signal CS.sub.1. Digital signal processor 316 is, for example, a digital signal processor. In at least one embodiment, the PFC controller 302 determines the pulse width and duty cycle of PFC switch control signal CS.sub.1 utilizing the algorithms disclosed in Melanson V and Melanson VI.

(22) In at least one embodiment, the pulse width T1 of PFC switch control signal CS.sub.1 is determined by digital signal processor 316 by executing a control signal state algorithm represented by Equation [1]:

(23) $\begin{array}{cc}T{1}^2=\frac{2.Math.L}{V_{{\_\mathrm{pk}}^2}}.Math.P.Math.\mathrm{TT}.Math.\left(1-\frac{V_{}}{V_{C1}}\right).& \left[1\right]\end{array}$
T1 is the pulse width of the PFC switch control signal CS.sub.1. L represents an inductance value of inductor 312. V.sub..sub._.sub.pk is a peak voltage of phase modulated signal V.sub. without phase delays. P represents a power demand variable related to the power demand of LED apparatus 322. In at least one embodiment, P is a proportional integrator output value as described in Melanson V and Melanson VI. TT is the period of PFC switch control signal CS.sub.1 and, in at least one embodiment, is also determined as described in Melanson V and Melanson VI. V.sub. is a sampled value of phase modulated signal V.sub.. V.sub.C1 is a sampled value of the link voltage V.sub.C1.

(24) In at least one embodiment, all of the PFC control parameters of Equation [1] are known, can be reliably determined directly, or can be reliably determined from the feedback signals V.sub. and V.sub.C1 except V.sub..sub._.sub.pk. Because phase modulated signal V.sub. includes phase delays when dimming the LEDs of LED apparatus 322, the peak voltage V.sub..sub._.sub.pk of phase modulated signal V.sub. cannot always be directly measured. However, as described in conjunction with FIGS. 4 and 5, the phase delays of phase modulated signal V.sub. can be used by digital signal processor 316 to estimate V.sub..sub._.sub.pk.

(25) In at least one embodiment, PFC controller 302 also controls the output current i.sub.OUT in accordance with the exemplary systems and methods described in Melanson IV.

(26) FIGS. 4 and 5 depict cycles of phase modulated signal V.sub. having various leading and trailing edge phase delays. Waveforms 400 represent two cycles 402 and 404 having a peak voltage of V.sub..sub._.sub.pk. Cycle 402 includes two phase delays 0 and 1, and cycle 404 includes two phase delays 2 and 3. The peak voltage V.sub..sub._.sub.pk can be measured directly from cycle 402 because the phase delays 0 and 1 are less than T/4, where T is the period of phase modulated signal V.sub.. However, the peak voltage V.sub..sub._.sub.pk cannot be measured directly from cycle 404 because the phase delays 2 and 3 are greater than T/4. Although the peak voltage V.sub..sub._.sub.pk can be measured directly from cycle 402, in at least one embodiment, the digital signal processor 316 determines the peak voltage V.sub..sub._.sub.pk for all cycles of phase modulated signal V.sub.. In at least one embodiment, the digital signal processor 316 periodically or intermittently determines the peak voltage V.sub..sub._.sub.pk. In at least one embodiment, the digital signal processor 316 measures each peak voltage V.sub..sub._.sub.pk from each cycle that can be measured.

(27) Referring to FIGS. 3, 4, and 5, phase delay detector 318 receives phase modulated signal V.sub. and, in at least one embodiment, determines a digital value of each phase delay X and X in each cycle of phase modulated signal V.sub., where X is an index value. To determine the peak voltage V.sub..sub._.sub.pk from the phase delays of phase modulated signal V.sub., phase delay detector 318 detects the phase delays of each cycle of phase modulated signal V.sub.. In at least one embodiment, phase delay detector 318 generates a digital value of phase delay signal for each phase delay detected in phase modulated signal V.sub.. Each digital value of phase delay signal represents a phase delay, and each phase delay indicates a dimming level. For example, a 50 Hz phase modulated signal V.sub. has a period of 1/50 or 0.02 seconds. A dimming level of 25% is represented by a phase delay of (0.5.Math.0.02).Math.0.25 seconds. Where (0.5.Math.0.02) represents the duration of each half cycle of phase modulated signal V.sub. and 0.25 represents the dimming level. Thus, each phase delay signal can also be referred to as a dimmer signal.

(28) Digital signal processor 316 determines the peak voltage V.sub..sub._.sub.pk from the phase delay signal . Each half cycle of phase modulated signal V.sub. represents 180 degrees. Each phase delay can be converted into an equivalent phase angle in accordance with Equation [2]:
phase angle=(2.Math.phase delay)/(T)180[2]
where T is the period of phase modulated signal V.sub..

(29) In at least one embodiment, digital signal processor 316 determines the peak voltage V.sub..sub._.sub.pk in accordance with Equation [3]:
V.sub..sub._.sub.pk=abs{V.sub.Ax/[sin(phase angle)]}[3],
where abs represents the absolute value function of the quantity enclosed by the brackets and V.sub.Ax represents a peak voltage of the leading or trailing edge associated with the phase delay, and x is an index.

(30) For example, if phase modulated signal V.sub. is a 50 Hz signal and 0=1, from Equations [2] and [3] the peak voltage V.sub..sub._.sub.pk for the first half of cycle 402 equals abs{V.sub.A0/[sin((2.Math.0)/0.02).Math.180)]. If 2=3, from Equations [2] and [3], the peak voltage V.sub..sub._.sub.pk for the second half of cycle 402 equals abs{V.sub.A1/[sin((2.Math.2)/0.02).Math.180)].

(31) In at least one embodiment, phase delays 0 and 1 are independently generated as, for example, described in Melanson H and Melanson III. When phase delays in a cycle are independently generated, the peak voltage V.sub..sub._.sub.pk can be updated for each independently generated phase delay.

(32) FIG. 5 depicts a leading edge phase delay 0 and a trailing edge phase delay 0. In at least one embodiment, digital signal processor 316 determines the peak voltage V.sub..sub._.sub.pk in accordance with Equations [2] and [3] for independently generated leading and trailing edge phase delays. When detecting independently generated leading and trailing edge phase delays, in at least one embodiment, digital signal processor 316 receives the raw phase modulated signal V.sub..sub._.sub.RAW to determine start and stop times of each half cycle of a cycle by, for example, sensing the polarity of each half cycle.

(33) FIG. 6 depicts a time-based phase delay detector 600 that represents one embodiment of phase delay detector 318. Comparator 602 compares phase modulated signal V.sub. to a known reference Vref. The reference V.sub.ref is generally the cycle cross-over point voltage of phase modulated signal V.sub., such as a neutral potential of a building AC voltage. In at least one embodiment, the reference V.sub.ref is a voltage value just greater than any expected voltage ripples of the neutral potential. The counter 604 counts the number of cycles of clock signal f.sub.clk that occur until the comparator 602 indicates that an edge of phase modulated signal V.sub. has been reached. Since the frequency of phase modulated signal V.sub. and the frequency of clock signal f.sub.clk is known, the phase delay indicated by phase delay signal can be determined from the count of cycles of clock signal f.sub.clk that occur until the comparator 602 indicates that the edge of phase modulated signal V.sub. has been reached. Thus, phase delay detector 600 is a time-based phase delay detector that detects the phase delays phase delay indicated by phase delay signal using a time-based process.

(34) FIG. 7 depicts exemplary waveforms 700 representing one cycle 702 of phase modulated signal V.sub. and pulse waveforms of PFC switch control signal CS.sub.1. In at least one embodiment, the PFC controller 302 continues to pulse the PFC switch 306, i.e. turn the PFC switch 306 ON and OFF, during phase delays of phase modulated signal V.sub. to increase the effective resistance R.sub.EFF.sub._.sub.1 of PFC LED driver circuit 304 without additional external components and without additional loss of efficiency.

(35) The phase delays 2 of cycle 702 of phase modulated signal V.sub. indicate dimming levels for the LEDs. Increasing phase delays indicate increasing dimming levels and decreasing power demand from PFC LED driver circuit. Referring to FIGS. 3 and 7, half cycles 704 and 706 of phase modulated signal V.sub. each include respective active (uncut) regions 708 and 710 having an active time period T.sub.A (referred to as active period T.sub.A). The active period T.sub.A plus the phase delay 2 equals the half cycle period T/2 of cycle 702. Referring to FIG. 1, conventional PFC driver circuit and controllers, such as light source driver circuit 106, cut off the output current i.sub.OUT during the phase delay 2. The phase modulated signal V.sub. of FIG. 1 often has ripples during the phase delay 2 that can cause problems, such as making the edges of phase modulated signal V.sub. difficult to detect.

(36) Referring to FIGS. 3 and 7, in at least one embodiment, during the phase delay 2, PFC controller 302 generates pulses 712 that decrease the effective resistance R.sub.EFF.sub._.sub.1 of PFC switch control signal CS.sub.1 and attenuates ripples of phase modulated signal V.sub. during phase delay 2. By attenuating the ripples of phase modulated signal V.sub. during 2, phase modulated signal V.sub. is approximately 0 V during phase delay 2 as shown in cycle 702. Attenuating the ripples facilitates more accurate edge detection by phase delay detector 318. A more accurate edge detection facilitates a more accurate determination of the dimming level indicated by phase modulated signal V.sub. and a more accurate determination of peak voltage V.sub..sub._.sub.pk. The periods and duty cycles of PFC switch control signal CS.sub.1 during phase delay 2 are not drawn to scale. In at least one embodiment, the periods and duty cycles of PFC switch control signal CS.sub.1 are sufficient enough to attenuate the ripples of phase modulated signal V.sub.. In at least one embodiment, the period of PFC switch control signal CS.sub.1 during phase delay 2 is 0.0001 seconds to 0.0002 seconds, which equates to a switching frequency ranging from 10 kHz to 20 kHz. Keeping a dimmer, such as dimmer 104 (FIG. 1) loaded during phase delays improves dimmer performance, thus, removing the need for the additional damping circuitry 282 of LED lamp driver 280 (FIG. 2).

(37) Generally, during the active period T.sub.A of phase modulated signal V.sub., PFC controller 302 determines the pulse widths of PFC switch control signal CS.sub.1 in accordance with Equation [1]. However, as the phase delay 2 increases, the duty cycle of PFC switch control signal CS.sub.1 also decreases. In at least one embodiment, once the duty cycle of PFC switch control signal CS.sub.1 is below a duty cycle threshold, the [1(V.sub./V.sub.C1)] term of Equation [1] becomes approximately 1. Accordingly, in at least one embodiment, once the duty cycle of PFC controller 302 is below the duty cycle threshold, PFC controller 302 generates pulses 714 of PFC switch control signal CS.sub.1 with a constant pulse width and constant duty cycle. In at least one embodiment, the PFC controller 302 generates pulses 714 within a frequency range of 25 kHz to 150 kHz to avoid audio frequencies at the low frequency end and avoid switching inefficiencies on the high frequency end. Additionally, in lighting applications, frequencies associated with commercial electronic devices, such as infrared remote controls, are avoided. In at least one embodiment, the particular duty cycle threshold is a matter of design choice and is, for example, chosen to be a duty cycle when [1(V.sub./V.sub.C1)] term of Equation [1] becomes approximately 1 so that the decreasing the duty cycle does not have an unacceptable effect on the performance of lighting system 300. In at least one embodiment, the duty cycle threshold is 0.4.

(38) Pulses 716 of control signal CS.sub.1 represent a time expanded window 718 of pulses 714 to illustrate the constant pulse widths of pulses 714. The pulses 716 are exemplary and not necessarily to scale. The duration of window 718 is T.sub.A/X, and X is a factor equal to 5/(frequency of PFC switch control signal CS.sub.1).

(39) FIG. 8 depicts an effective resistance model of PFC LED driver circuit 304. PFC LED driver circuit 304 has an effective resistance R.sub.EFF.sub._.sub.1 from the perspective of a mains voltage source such as the AC voltage source 101 (FIG. 1). In at least one embodiment, PFC controller 302 generates a PFC switch control signal CS.sub.1 to cause PFC LED driver circuit 304 to respond to the dimming level indicated by the phase delay signal without decreasing an effective resistance R.sub.EFF.sub._.sub.1 of the PFC LED driver circuit 304, as perceived by a voltage source of the PFC LED driver circuit 304, as the dimming level indicated by the signal increases. Keeping the effective resistance R.sub.EFF.sub._.sub.1 of the PFC LED driver circuit 304 from decreasing as dimming levels increase conserves power.

(40) In at least one embodiment, digital signal processor 316 monitors power demand of the LED apparatus 322 by monitoring the value of power demand variable P in Equation [1]. As power demand of the LED apparatus 322 decreases due to, for example, increased dimming, the value of power demand variable P decreases. By determining the pulse width of PFC switch control signal CS.sub.1 in accordance with Equation [1], digital signal processor 316 decreases the pulse width and, thus, the duty cycle of PFC switch control signal CS.sub.1. Decreasing the duty cycle of PFC switch control signal CS.sub.1 keeps the effective resistance R.sub.EFF.sub._.sub.1 from increasing with increasing dimming levels.

(41) FIG. 9 depicts exemplary relationships between phase modulated signal V.sub. and the inductor current i.sub.L1 without dimming in view 902 and with dimming in view 904. Referring to FIGS. 3 and 9, the effective resistance R.sub.EFF.sub._.sub.1 of PFC load driver circuit 304 equals V.sub./i.sub.L1. In view 902, phase modulated signal V.sub. has no phase delays, which indicates no dimming. Because PFC load driver circuit 304 is power factor corrected, the inductor current i.sub.L1 tracks and is in phase with the phase modulated signal V.sub.. In view 904, phase modulated signal V.sub. includes phase delays 1 and 2, which indicates dimming. The dashed lined waveforms 906 and 908 represent the values of the inductor current i.sub.L1 if the inductor current i.sub.L1 had not decreased with dimming. The solid lined waveforms 910 and 912 indicate the actual value of inductor current i.sub.L1 as controlled by PFC controller 302. Thus, the effective resistance R.sub.EFF.sub._.sub.1 of PFC load driver circuit 304 does not decrease as dimming levels increase and, in at least one embodiment actually increases as dimming levels increase.

(42) FIG. 10 depicts an exemplary, graphical relationship 1000 between duty cycles of PFC switch control signal CS.sub.1 and the link voltage V.sub.C1. Referring to FIGS. 3 and 10, PFC load driver circuit 304 boosts the phase modulated signal V.sub. to different link voltages V.sub.C1 depending upon the duty cycle of PFC switch control signal CS.sub.1. Decreasing the power demand of LED apparatus 322 results in a decreasing value of the power demand variable P in Equation [1]. In accordance with Equation [1], PFC controller 302 responds to decreasing power demand by LED apparatus 322 by decreasing the duty cycle of PFC switch control signal CS.sub.1. The decreasing power demand by LED apparatus 322 is, for example, caused by dimming the LEDs of LED apparatus 322. In at least one embodiment, boosting the phase modulated signal V.sub. to the high link voltage V.sub.C1.sub._.sub.H results in a boost of 120 VAC to an approximately 400 V direct current voltage. As the duty cycle of PFC switch control signal CS.sub.1 decreases with decreased power demand by LED apparatus 322, PFC load driver circuit 304 loses efficiency via, for example, switching losses associated with switch 306.

(43) Accordingly, in at least one embodiment, PFC controller 302 generates the duty cycle modulated PFC switch control signal CS.sub.1 to control the regulated link voltage V.sub.C1 of the PFC LED driver circuit 304. PFC controller 302 decreases the link voltage V.sub.C1 from a high link voltage value V.sub.C1.sub._.sub.H to a low link voltage value V.sub.C1.sub._.sub.L when the duty cycle of the PFC switch control signal CS.sub.1 decreases to a value between zero and a duty cycle threshold DC.sub.TH. The particular value of the duty cycle threshold DC.sub.TH is a matter of design choice and is, for example, chosen to increase the efficiency of PFC load driver circuit 304 while providing an adequate link voltage V.sub.C1 to provide the power demand needs of LED apparatus 322. In at least one embodiment, the duty cycle threshold DC.sub.TH is set at 0.5. In at least one embodiment, for phase modulated signal V.sub. having a voltage peak V.sub..sub._.sub.pk of 120V, the high link voltage V.sub.C1.sub._.sub.H is any value within a range of approximately 200V to 400V for a low link voltage W.sub.C1.sub._.sub.L having a respective value within a range of approximately 120V to 175V.

(44) The slope and shape of the transition 1002 from the high link voltage V.sub.C1.sub._.sub.H to the low link voltage are matters of design choice and depend upon, for example, a desired transition between high link voltage V.sub.C1.sub._.sub.H and the low link voltage V.sub.C1.sub._.sub.L. In at least one embodiment, the slope is 90 degrees, which indicates two possible values, V.sub.C1.sub._.sub.H and V.sub.C1.sub._.sub.L, for link voltage V.sub.C1. In other embodiments, the slope is less than 90 degrees and indicates multiple values of link voltage V.sub.C1 between high link voltage V.sub.C1.sub._.sub.H and the low link voltage V.sub.C1.sub._.sub.L. The shape of transition 1002 can be linear or nonlinear.

(45) FIGS. 11 and 12 depict exemplary embodiments of LED apparatus 322. LED apparatus 1100 includes one or more LED(s) 1102. The LED(s) 1102 can be any type of LED including white, amber, other colors, or any combination of LED colors. Additionally, the LED(s) 1102 can be configured into any type of physical arrangement, such as linearly, circular, spiral, or any other physical arrangement. In at least one embodiment, each of LED(s) 1102 is serially connected. Capacitor 1104 is connected in parallel with LED(s) 1102 and provides filtering to protect the LED(s) 1102 from AC signals. Inductor 1106 smoothes energy from LED current i.sub.OUT to maintain an approximately constant current i.sub.OUT when PFC switch 306 is ON. Diode 1108 allows continuing current flow when switch PFC 306 is OFF.

(46) In switching LED system 1210, inductor 1212 is connected in series with LED(s) 1102 to provide energy storage and filtering. Inductor 1212 smoothes energy from LED current i.sub.OUT to maintain an approximately constant current i.sub.OUT when PFC switch 306 is ON. Diode 1214 allows continuing current flow when PFC switch 306 is OFF. Although two specific embodiments of LED apparatus 322 have been described, LED apparatus 322 can be any LED, array of LED(s), or any switching LED system.

(47) Thus, a PFC controller 302 determines at least one power factor correction control parameter from phase delays of phase modulated signal V.sub..

(48) In at least one embodiment, as a dimming level decreases, the PFC controller 302 decreases a duty cycle of PFC switch 306 in the PFC LED driver circuit 304 to cause the PFC LED driver circuit 304 to decrease the output current supplied to the LEDs. When the phase modulated signal V.sub. indicates a dimming level below a threshold value .sub.TH, the PFC controller 302 maintains an approximately constant duty cycle of the PFC switch 306 to, for example, maintain switching efficiency without significantly sacrificing power factor correction.

(49) In at least one embodiment, PFC controller 302 generates a PFC switch control signal CS.sub.2 to cause the PFC LED driver circuit 304 to respond to decreasing dimming levels as indicated by a dimming signal, such as the phase modulated signal V.sub., without decreasing an effective resistance of the PFC LED driver circuit 304.

(50) In at least one embodiment, the PFC controller 302 generates a duty cycle modulated PFC switch control signal CS.sub.1 to control a regulated link voltage V.sub.C1 of the PFC LED driver circuit 304 and decreases the link voltage V.sub.C1 when a duty cycle of the PFC switch control signal CS.sub.1 decreases to a value between zero and a duty cycle threshold value DC.sub.TH.

(51) Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.