Method for fabricating a device comprising a PNP bipolar transistor and NPN bipolar transistor for radiofrequency applications

Abstract

A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

Claims

1. A method for fabricating a microelectronic device that includes a PNP transistor and an NPN transistor, comprising: forming an N+ doped isolating well of the PNP transistor in a semiconductor substrate that is P-type doped; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first epitaxial semiconductor layer on the semiconductor substrate; after epitaxially growing the first epitaxial semiconductor layer, forming an N+ doped well of the NPN transistor that at least partially extends into the first epitaxial semiconductor layer; after forming the N+ doped well, epitaxially growing a second epitaxial semiconductor layer on and in contact with both the first epitaxial semiconductor layer and the N+ doped well of the NPN transistor; forming a P doped region configured to form a collector of the PNP transistor in the second epitaxial semiconductor layer, wherein said P doped region is in electrical contact with the P+ doped region in the N+ doped isolating well; forming a base of the PNP transistor in contact with the P doped region forming the collector of the PNP transistor; forming an N doped region configured to form a collector of the NPN transistor in the second epitaxial semiconductor layer, wherein the N doped region is in electrical contact with the N+ doped well; and forming a base of the NPN transistor in contact with the N doped region forming the collector of the NPN transistor.

2. The method according to claim 1, wherein the first epitaxial semiconductor layer has a thickness of between 0.5 and 0.7 μm.

3. The method according to claim 1, wherein the first epitaxial semiconductor layer is lightly P doped.

4. The method according to claim 1, wherein the first epitaxial semiconductor layer is non-intentionally doped.

5. The method according to claim 1, wherein the second epitaxial semiconductor layer has a thickness of between 0.3 and 0.5 μm.

6. The method according to claim 1, wherein the second epitaxial semiconductor layer is lightly N-doped.

7. The method according to claim 1, wherein the second epitaxial semiconductor layer is non-intentionally doped.

8. The method according to claim 1, wherein a sum of thicknesses of the first and second epitaxial semiconductor layers is between 0.8 and 1.2 μm.

9. A method for fabricating a microelectronic device that includes a PNP transistor and an NPN transistor, comprising: forming an N+ doped isolating well of the PNP transistor in a semiconductor substrate that is P-type doped; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first epitaxial semiconductor layer on the P+ doped region, on the N+ doped isolating well, and on the semiconductor substrate; implanting and activating dopant at an upper surface of the first epitaxial semiconductor layer to form an N+ doped well of the NPN transistor in the first epitaxial semiconductor layer, wherein at least part of said N+ doped well extends from the upper surface and through the first epitaxial semiconductor layer to contact the semiconductor substrate; epitaxially growing a second epitaxial semiconductor layer on an upper surface of the N+ doped well and on the upper surface of the first epitaxial semiconductor layer; implanting and activating dopant at an upper surface of the second epitaxial semiconductor layer to form a P doped region configured to form a collector of the PNP transistor in the second epitaxial semiconductor layer, wherein at least part of said P doped region extends from the upper surface and through the second epitaxial semiconductor layer to contact the P+ doped region; forming a base of the PNP transistor in contact with the P doped region configured to form the collector of the PNP transistor; forming an N doped region configured to form a collector of the NPN transistor in the second epitaxial semiconductor layer, wherein at least a portion of the N doped region extends to contact the N+ doped well; and forming a base of the NPN transistor in contact with the N doped region configured to form the collector of the NPN transistor.

10. The method according to claim 9, wherein the first epitaxial semiconductor layer has a thickness of between 0.5 and 0.7 μm.

11. The method according to claim 9, wherein the first epitaxial semiconductor layer is lightly P doped.

12. The method according to claim 9, wherein the first epitaxial semiconductor layer is non-intentionally doped.

13. The method according to claim 9, wherein the second epitaxial semiconductor layer has a thickness of between 0.3 and 0.5 μm.

14. The method according to claim 9, wherein the second epitaxial semiconductor layer is lightly N-doped.

15. The method according to claim 9, wherein the second epitaxial semiconductor layer is non-intentionally doped.

16. The method according to claim 9, wherein a sum of thicknesses of the first and second epitaxial semiconductor layers is between 0.8 and 1.2 μm.

17. A method for fabricating a microelectronic device that includes a PNP transistor and an NPN transistor, comprising: forming an N+ doped isolating well of the PNP transistor in a semiconductor substrate that is P-type doped; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first epitaxial semiconductor layer on the semiconductor substrate; after epitaxially growing the first epitaxial semiconductor layer, implanting dopant in the first epitaxial semiconductor layer to form an N+ doped well of the NPN transistor extending into the first epitaxial semiconductor layer; then epitaxially growing a second epitaxial semiconductor layer on the first epitaxial semiconductor layer; forming a P doped region in the second epitaxial semiconductor layer, wherein said P doped region is in electrical contact with the P+ doped region in the N+ doped isolating well; forming a base of the PNP transistor in contact with the P doped region which forms a collector of the PNP transistor; forming an N doped region in the second epitaxial semiconductor layer, wherein the N doped region is in electrical contact with the N+ doped well; and forming a base of the NPN transistor in contact with the N doped region which forms a collector of the NPN transistor.

18. The method according to claim 17, wherein the first epitaxial semiconductor layer is lightly P doped.

19. The method according to claim 17, wherein the first epitaxial semiconductor layer is non-intentionally doped.

20. The method according to claim 17, wherein the second epitaxial semiconductor layer is lightly N-doped.

21. The method according to claim 17, wherein the second epitaxial semiconductor layer is non-intentionally doped.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other characteristics and advantages of these embodiments will become apparent in the following detailed description with reference to the appended drawings in which:

(2) FIG. 1 is a schematic cross-sectional view of a P-type substrate at the time of localized implanting of N-type dopants;

(3) FIG. 2 is a schematic view of the substrate in FIG. 1 after diffusion annealing of the implanted dopants to form a region isolating the collector of a PNP transistor from the substrate;

(4) FIG. 3 is a schematic cross-sectional view of the substrate in FIG. 2 at the time of localized implanting of P-type dopants in the isolating region;

(5) FIG. 4 is a schematic cross-sectional view of the substrate in FIG. 3 after diffusion annealing of the P-type dopants implanted to form the P+ well of the PNP transistor;

(6) FIG. 5 is a schematic cross-sectional view of the substrate in FIG. 4 after forming a first epitaxial layer on the substrate;

(7) FIG. 6 is a schematic cross-sectional view of the substrate in FIG. 5 at the time of implanting N-type dopants;

(8) FIG. 7 is a schematic cross-sectional view of the substrate in FIG. 6 after diffusion annealing of the N-type dopants implanted to form an N+ well of an NPN transistor;

(9) FIG. 8 is a schematic cross-sectional view of the substrate in FIG. 7 after forming a second epitaxial layer on the first epitaxial layer;

(10) FIG. 9 is a schematic cross-sectional view of the substrate in FIG. 8 at the time of implanting P-type dopants in the second epitaxial layer;

(11) FIG. 10 is a schematic cross-sectional view of the substrate in FIG. 9 after diffusion annealing of the P-type dopants implanted to form the collector of the PNP transistor; and

(12) FIG. 11 is a schematic cross-sectional view of a device comprising a PNP transistor and NPN transistor obtained with the above-described method.

(13) For reasons of legibility of the figures, they are not drawn to scale. Also, the drawings have been simplified so as only to show those elements that are useful for comprehension of the Figures.

DETAILED DESCRIPTION

(14) The successive steps of the method for fabricating a microelectronic device comprising a P-type doped semiconductor substrate and a PNP transistor and NPN transistor arranged vertically in said semiconductor substrate are schematically illustrated in FIGS. 1 to 10.

(15) With reference to FIG. 1, the semiconductor substrate 1 is a P-type doped semiconductor substrate. The material of the semiconductor substrate may be silicon, for example.

(16) A mask M is formed on the main surface of the substrate 1. The mask M comprises at least one opening allowing exposure of a determined portion of the surface of the semiconductor substrate 1, corresponding to the site of a PNP transistor. The mask M may be formed with a photolithography technique conventionally used in methods to fabricate microelectronics.

(17) Dopants are implanted (symbolized by the arrows) in the opening of the mask (the material and thickness of the mask M being selected to prevent any passing of dopants through the mask). The dopants are of N-type (e.g., phosphorus).

(18) A region 2a containing the implanted dopants therefore extends into part of the thickness of the substrate 1, from the portion of surface exposed by the opening of the mask M.

(19) With reference to FIG. 2, heat treatment is applied to the semiconductor substrate thus implanted and the mask M is removed.

(20) Said heat treatment is applied under conditions allowing diffusion and activation of the dopants in region 2a to form an N+ doped well 2. As will be seen below, said N+ doped well 2 is intended to form the isolating well of the PNP transistor.

(21) With reference to FIG. 3, a new mask M is formed on the main surface of semiconductor substrate 1. The mask M comprises at least one opening allowing exposure of a determined portion of the surface of the semiconductor substrate 1 opposite the well 2. Said opening is of smaller size than the well 2.

(22) Dopants are implanted (schematized by the arrows) in the opening of the mask (the material and thickness of the mask M being selected to prevent any passing of dopants through the mask). The dopants are of P-type (e.g., boron).

(23) A region 3a containing the implanted dopants therefore extends into part of the thickness of the well 2, from the portion of surface exposed by the opening of the mask M.

(24) With reference to FIG. 4, heat treatment is applied to the semiconductor substrate thus implanted, and the mask M is removed.

(25) Said heat treatment is applied under conditions allowing the diffusion and activation of the dopants in region 3a, to form a P+ doped region 3 in the well 2.

(26) With reference to FIG. 5, epitaxial growth of a first semiconductor layer 10 is performed on the main surface of substrate 1. Preferably, the material of the epitaxial layer is the same as that of the substrate 1 (homoepitaxy). Optionally, the material of the epitaxial layer may differ from that of the substrate 1 (heteroepitaxy) but with a lattice parameter as close as possible to that of the substrate 1 to minimize the formation of crystalline defects in the epitaxial layer.

(27) The first epitaxial layer 10 may be lightly P doped, or non-intentionally doped.

(28) One function of said first epitaxial layer 10 is to contribute towards burying the P+ doped region 3 within the structure.

(29) The thickness of the first epitaxial layer 10 may be between 0.5 and 0.7 μm.

(30) The dopants of the N+ doped region 3 may optionally diffuse into part of the first epitaxial layer 10 under the effect of the temperature of the epitaxy step.

(31) With reference to FIG. 6, a new mask M is formed on the main surface of the first epitaxial layer 10. The mask M comprises openings allowing exposure of determined portions of the first epitaxial layer 10 on either side of the well 2 (on the left side in the Figure) and the site of an NPN transistor (on the right side in the Figure).

(32) Implanting of dopants (schematized by the arrows) is performed in the opening of the mask (the material and thickness of the mask M being selected to prevent any passing of dopants through the mask). The dopants are of N-type (e.g., arsenic).

(33) Regions 4a and 5a containing the implanted dopants therefore extend into part of the thickness of the first epitaxial layer 10, in the part dedicated to the forming of the PNP transistor (either side of well 2) and into the part dedicated to the forming of the NPN transistor respectively, from the portion of surface exposed by the opening of the mask M.

(34) With reference to FIG. 7, heat treatment is applied to the semiconductor substrate thus implanted, and the mask M is removed.

(35) Said heat treatment is applied under conditions allowing diffusion and activation of the dopants in regions 4a and 5a, to form N+ doped regions 4 and 5 in the first epitaxial layer 10 and part of the semiconductor substrate 1.

(36) Regions 4 are intended to ensure electrical continuity between the well 2 and the surface of the device, so as to allow electrical polarization of the well 2 of the PNP transistor.

(37) Region 5 is intended to form a well of the NPN transistor.

(38) With reference to FIG. 8, epitaxial growth of a second semiconductor layer 11 is performed on the main surface of the first semiconductor layer 10. Preferably, the material of the second epitaxial layer is the same as that of the first epitaxial layer (homoepitaxy). Optionally, the material of the second epitaxial layer may differ from the material of the first epitaxial layer (heteroepitaxy) but with a lattice parameter as close as possible to that of the first epitaxial layer to minimize the formation of crystalline defects in the second epitaxial layer.

(39) The dopants of the N+ doped well 5 may possibly diffuse into part of the second epitaxial layer 11 under the effect of the temperature of the epitaxy step.

(40) The second epitaxial layer 11 may be lightly N-doped, or non-intentionally doped.

(41) The thickness of the second epitaxial layer 11 may be between 0.3 and 0.5 μm.

(42) One function of said second epitaxial layer 11 is to bury the N+ doped well 5 of the NPN transistor within the structure and, together with the previously formed first epitaxial layer 10, to contribute towards burying the P+ doped region 3 of the PNP transistor.

(43) It can therefore be seen in FIG. 8 that the well 2 and region 3 of the PNP transistor are buried deeper in the structure than the well 5 of the NPN transistor, the well 2 and region 3 being separated from the surface of the structure in FIG. 8 by the stack of layers 10 and 11, which has a thickness of between 0.8 and 1.2 μm, whilst well 5 is separated from said surface solely by layer 11 which, as indicated above, has a thickness of between 0.3 and 0.5 μm.

(44) The forming of the two epitaxial layers at different steps of the method therefore provides selectivity of implantation depth for the P+ doped region 3 of the PNP transistor and the N+ doped well 5 of the NPN transistor, while applying dopant implantation with moderate energy allowing minimization of implantation-related crystalline defects.

(45) The thickness of the epitaxial layers 10 and 11 may be adjusted as a function of the heat budget to which the structure is subjected throughout fabrication of the device, to optimize the performance of the PNP transistor and NPN transistor. The thickness of the first epitaxial layer 10 may result from a compromise between the withstand voltage of the NPN transistor (which requires a sufficiently large thickness of layer 10) and the speed of the PNP transistor (which requires a sufficiently narrow thickness of layer 10). The thickness of the second epitaxial layer 11 may be chosen as a function of the desired withstand voltage of both transistors.

(46) With reference to FIG. 9, a new mask M is formed on the main surface of the second epitaxial layer 11. The mask M comprises at least one opening allowing exposure of a determined portion of the surface of the second epitaxial layer opposite region 3 of the PNP transistor.

(47) Implanting of dopants (schematized by the arrows) is performed in the opening of the mask (the material and thickness of the mask M being selected to prevent any passing of dopants through the mask). The dopants are of P-type (e.g., boron).

(48) A region 6a containing the implanted dopants therefore extends into the second epitaxial layer 11 and possibly into part of the first epitaxial layer 10, from the portion of surface exposed by the opening of the mask M.

(49) With reference to FIG. 10, heat treatment is applied to the structure thus implanted and the mask M is removed.

(50) Said heat treatment is applied under conditions allowing the diffusion and activation of the dopants in region 6a, to form a P doped region 6 extending as far as the P+ doped region 3, to ensure electrical continuity with region 3. Region 6 is intended to form the collector of the PNP transistor.

(51) Similarly (not schematized), a new mask is formed on the main surface of the second epitaxial layer. The mask comprises at least one opening allowing exposure of a determined portion of the surface of the second epitaxial layer opposite the well 5 of the NPN transistor.

(52) Implanting of dopants is performed in the opening of the mask (the material and thickness of the mask M being selected to prevent any passing of dopants through the mask). The dopants are of N-type (e.g., arsenic).

(53) A region containing the implanted dopants therefore extends into the second epitaxial layer and possibly into the well 5, from the portion of surface exposed by the opening of the mask M.

(54) Heat treatment is then applied to the structure thus implanted and the mask is removed.

(55) Said heat treatment is applied under conditions allowing diffusion and activation of the dopants in the doped region to form a region (referenced 7 in FIG. 11) that is N doped extending as far as the N+ doped well 5, to ensure electrical continuity with the well 5. Region 7 is intended to form the collector of the NPN transistor.

(56) FIG. 11 is a cross-sectional view of the device after forming the emitter E and base B of the PNP transistor (on the left) and of the NPN transistor (on the right). The forming of these components is obtained with methods known per se and will therefore not be described herein.

(57) As indicated above, the P+ doped region 3 of the PNP transistor is further distant from the surface of the device than the N+ doped well 5 of the NPN transistor.

(58) This difference in depth arrangement of these regions/wells allows consideration to be given to the greater diffusion of the P dopants of the PNP transistor during the different heat treatments applied when fabricating the device, without penalizing the rapidity of the NPN transistor or requiring high-energy implantation which could generate crystalline defects. It therefore allows integration of these two types of transistors in one same semiconductor substrate of a microelectronic device without degrading the performance of either of these transistors.