Silicon epitaxial wafer and method of producing silicon epitaxial wafer

Abstract

A silicon epitaxial wafer including: a second intermediate epitaxial layer on a silicon substrate produced by being cut from a silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 310.sup.16 to 210.sup.17 atoms/cm.sup.3, a first intermediate epitaxial layer doped with a dopant, and an epitaxial layer of a device forming region stacked on the first intermediate epitaxial layer, and to a method of producing this wafer. Also providing an industrially excellent silicon epitaxial wafer that is produced with a silicon substrate doped with carbon and used as a semiconductor device substrate such as a memory, a logic, or a solid-state image sensor, and a method of producing this silicon epitaxial wafer.

Claims

1. A silicon epitaxial wafer comprising: a silicon substrate doped with carbon, the silicon substrate being produced by being cut from a silicon single crystal ingot grown by a Czochralski method so as to have a carbon concentration ranging from 310.sup.16 to 210.sup.17 atoms/cm.sup.3; a first intermediate epitaxial layer that is doped with a dopant and disposed on the silicon substrate; an epitaxial layer stacked on the first intermediate epitaxial layer, the epitaxial layer being a region at which a device is to be formed; and a second intermediate epitaxial layer disposed between the silicon substrate and the first intermediate epitaxial layer, wherein the second intermediate epitaxial layer has a thickness ranging from 0.5 m to 2 m, the silicon substrate is an n-type silicon substrate, the second intermediate epitaxial layer is an n.sup.-type second intermediate epitaxial layer, the first intermediate epitaxial layer is an n.sup.+-type first intermediate epitaxial layer, the epitaxial layer of the device forming region is an n.sup.-type epitaxial layer, and a p/n boundary is formed by ion implanting of p-type elements into the epitaxial layer of the device forming region.

2. The silicon epitaxial wafer according to claim 1, wherein a thickness of the second intermediate epitaxial layer is adjusted depending on an amount of the carbon with which the silicon substrate is doped, which thickness is decreased if the amount of carbon is too low or increased if the amount of carbon is too high.

3. The silicon epitaxial wafer according to claim 1, wherein a thickness of the second intermediate epitaxial layer is adjusted depending on a position at which the silicon substrate is cut from the silicon single crystal ingot, and, for a silicon substrate cut from the first half portion of the cone side in the single crystal growth direction, the second intermediate epitaxial layer has a first thickness, and for a silicon substrate cut from the second half portion of the tail side, the second intermediate epitaxial layer has a second thickness that is thicker than the first thickness.

4. A method of producing a silicon epitaxial wafer, comprising: preparing a silicon substrate that is doped with carbon and produced by cutting a silicon single crystal ingot grown by a Czochralski method so as to have a carbon concentration ranging from 310.sup.16 to 210.sup.17 atoms/cm.sup.3; forming a first intermediate epitaxial layer doped with a dopant over the silicon substrate; stacking an epitaxial layer on the first intermediate epitaxial layer, the epitaxial layer being a region at which a device is to be formed; and forming a second intermediate epitaxial layer on the silicon substrate before forming the first intermediate epitaxial layer, wherein the second intermediate epitaxial layer is formed so as to have a thickness ranging from 0.5 m to 2 m, the silicon substrate is an n-type silicon substrate, the second intermediate epitaxial layer is an n.sup.-type second intermediate epitaxial layer, the first intermediate epitaxial layer is an n.sup.+-type first intermediate epitaxial layer, the epitaxial layer of the device forming region is an n.sup.-type epitaxial layer, and a p/n boundary is formed by ion implanting of p-type elements into the epitaxial layer of the device forming region.

5. The method according to claim 4, wherein a thickness of the second intermediate epitaxial layer is adjusted depending on an amount of the carbon with which the silicon substrate is doped, which thickness is decreased if the amount of carbon is too low or increased if the amount of carbon is too high.

6. The method according to claim 4, wherein a thickness of the second intermediate epitaxial layer is adjusted depending on a position at which the silicon substrate is cut from the silicon single crystal ingot, and, for a silicon substrate cut from the first half portion of the cone side in the single crystal growth direction, the second intermediate epitaxial layer has a first thickness, and for a silicon substrate cut from the second half portion of the tail side, the second intermediate epitaxial layer has a second thickness that is thicker than the first thickness.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a schematic diagram of a silicon epitaxial wafer according to the present invention;

(2) FIG. 2 is a schematic diagram of an example of the inventive silicon epitaxial wafer in which a p-type conductive layer is formed;

(3) FIG. 3 is a schematic diagram of a conventional silicon epitaxial wafer;

(4) FIG. 4 is a schematic diagram of a conventional silicon epitaxial wafer in which a p-type conductive layer is formed;

(5) FIG. 5 is a schematic diagram of an apparatus for pulling a silicon single crystal ingot;

(6) FIG. 6A is an explanatory view of the relation of a carrier concentration and a carbon concentration to the depth from a surface of a silicon epitaxial wafer before a heat treatment in Example;

(7) FIG. 6B is an explanatory view of the relation of a carrier concentration and a carbon concentration to the depth from a surface of a silicon epitaxial wafer just after a p-type conductive layer was implanted in Example;

(8) FIG. 6C is an explanatory view of the relation of a carrier concentration and a carbon concentration to the depth from a surface of a silicon epitaxial wafer after a heat treatment in Example;

(9) FIG. 7A is an explanatory view of the relation of a carrier concentration and a carbon concentration to the depth from a surface of a silicon epitaxial wafer before a heat treatment in Comparative Example;

(10) FIG. 7B is an explanatory view of the relation of a carrier concentration and a carbon concentration to the depth from a surface of a silicon epitaxial wafer just after a p-type conductive layer was implanted in Comparative Example; and

(11) FIG. 7C is an explanatory view of the relation of a carrier concentration and a carbon concentration to the depth from a surface of a silicon epitaxial wafer after a heat treatment in Comparative Example;

DESCRIPTION OF EMBODIMENTS

(12) The present inventor found that when a silicon substrate doped with carbon is used, the amount of carbon dopant varies the diffusion distance of an intermediate epitaxial layer subjected to a thermal process, as described previously. The inventor also found that the diffusion of the carbon in the silicon substrate occurs at the same time as the elements in the intermediate epitaxial layer are diffused, and greatly affects the diffusion distance of the elements in the intermediate epitaxial layer.

(13) In view of these, the inventor discovered the following and thereby brought the invention to completion. An additional intermediate epitaxial layer (a second intermediate epitaxial layer) is formed between the intermediate epitaxial layer and the silicon substrate so that the concentration of the carbon distributed by the diffusion of carbon in the silicon substrate is adjusted; a first intermediate epitaxial layer is then formed on the second intermediate epitaxial layer; in this case, the position of the p/n boundary of an epitaxial layer, which is a device forming region, does not change even when a high temperature heat treatment is performed.

(14) An embodiment of the present invention will hereinafter be described in more detail with reference to the drawings, but the present invention is not limited to this embodiment.

(15) The inventive silicon epitaxial wafer and a method of producing this wafer will be first described below with reference to FIG. 1 and FIG. 2.

(16) In the inventive silicon epitaxial wafer, the second intermediate epitaxial layer 22, the first intermediate epitaxial layer 21, and the epitaxial layer 30 of the device forming region are stacked on a silicon substrate 10 produced by being cut from a silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 310.sup.16 to 210.sup.17 atoms/cm.sup.3 (FIG. 1). FIG. 2 shows a silicon epitaxial wafer in which a p-type conductive layer 30p is formed in the epitaxial layer 30 of the device forming region.

(17) When the silicon epitaxial wafer configured as shown in FIG. 1 is produced, the silicon substrate 10 is first prepared by slicing a silicon single crystal ingot. This silicon single crystal ingot is grown by the Czochralski method (CZ) method so as to have a carbon concentration ranging from 310.sup.16 to 210.sup.17 atoms/cm.sup.3 with an apparatus for pulling a silicon single crystal ingot as shown in FIG. 5.

(18) As shown in FIG. 5, the apparatus 50 for pulling a silicon single crystal ingot includes a main chamber 51a and a pull chamber 51b. In the interior of the main chamber 51a, a quartz crucible 53a configured to contain a raw material melt 52 and a graphite crucible 53b supporting the quartz crucible 53a are provided. Those crucibles are supported by a receiver 54b disposed on a supporting shaft 54a, which is called a pedestal. A main heater 55 is disposed outside the crucibles. A heat insulating material 56 is disposed outside this heater along an inner wall of the main chamber 51a. A cylindrical gas-flow guiding cylinder 57 made of graphite with a heat insulating plate provided at its lower end is disposed above the crucibles.

(19) The following description gives an instance of a method of obtaining a silicon single crystal ingot 59 doped with carbon by using the silicon-single-crystal-ingot pulling apparatus 50 shown in FIG. 5.

(20) Polycrystalline silicon with high purity is first introduced into the quartz crucible 53a. If the target conductivity type is n-type, then a dopant of, for example, phosphorus (P) is added.

(21) The conditions of the CZ method may be changed according to use: a magnetic field is applied or no magnetic field is applied. In addition, the elements determining the conductivity type and resistivity of the silicon substrate can be changed according to use. The elements such as phosphorus (P), boron (B), arsenic, antimony, gallium, germanium or aluminum can be added.

(22) After the raw material is charged into the quartz crucible 53a, an argon gas is introduced from a gas inlet provided in the pull chamber 51b while a vacuum pump is operated to ventilate the interior through a gas outlet so that the interior is displaced by an argon atmosphere.

(23) The main heater 55 disposed so as to surround the graphite crucible 53b then heats and melts the raw material contained in the quartz crucible 53a, thereby forming the raw material melt 52. After the raw material is melted, a seed crystal 58 is dipped into the raw material melt 52 and pulled up while being rotated so that the silicon single crystal ingot 59 is grown.

(24) The method of doping carbon of an additive raw material may be properly selected from the following methods: doping carbon by a gas during the pull of the silicon single crystal ingot 59; using a container made of polycrystalline silicon containing high purity carbon powder, a lump of carbon, or carbon powder; introducing polycrystalline silicon containing carbon in a prescribed amount into the crucible.

(25) The silicon single crystal ingot 59 thus obtained becomes a silicon substrate (sub.) through wafer processing operations. These processing operations for the silicon substrate are performed in accordance with conventional operations. Cutting with a cutting apparatus (not shown) such as an inner diameter slicer or a wire saw is followed by surface treatments such as polishing and cleaning on the obtained silicon substrate. Besides these processes, there are various processes such as chamfering and lapping. An annealing process may be performed according to use. The flatness of a mirror-polished wafer obtained by the above process is an important quality for production of an epitaxial wafer. The order and conditions of these processes are changed properly to achieve desired flatness.

(26) For a phosphorus (P) doped n-type, for example, the silicon substrate thus obtained usually contains phosphorus added so as to have a concentration of the order of 110.sup.14 to 110.sup.15 atoms/cm.sup.3 and carbon added so as to have a concentration of 310.sup.16 to 210.sup.17 atoms/cm.sup.3. The carbon contained in the silicon substrate makes oxide precipitates easy to appear at a high density in a device process, thereby providing sufficient gettering capability. The amount of carbon to be added may be changed properly according to the conditions of a thermal process of a device process.

(27) In the above manner, the silicon substrate can be prepared, which is produced by cutting the silicon single crystal ingot grown by the CZ method so as to have a carbon concentration ranging from 310.sup.16 to 210.sup.17 atoms/cm.sup.3.

(28) After the wafer processing operations of the silicon substrate 10, the second intermediate epitaxial layer 22 is formed on the silicon substrate 10.

(29) The reason why the second intermediate epitaxial layer 22 (n.sup.) is formed in the invention is as follows.

(30) The position of the p/n boundary (a boundary region between a p-type conductive layer and an intermediate epitaxial layer (n.sup.+)) depends on the ability of this intermediate epitaxial layer (n.sup.+) to diffuse by a thermal process. In order to prevent the occurrence of variation in position of the p/n boundary, the distance of the diffusion of the intermediate epitaxial layer (n.sup.+) needs to be uniform in a chip.

(31) If the silicon substrate contains carbon, the distance of the diffusion of the intermediate epitaxial layer (n.sup.+) may be affected by carbon diffusion from the silicon substrate. This is a factor in the nonuniform distance of the diffusion of the intermediate epitaxial layer (n.sup.+). This carbon diffusion changes the ability of the intermediate epitaxial layer (n.sup.+) to diffuse. The degree of this change greatly depends on the carbon concentration of the silicon substrate. The higher the carbon concentration of the silicon substrate, the longer the distance of the diffusion of the intermediate epitaxial layer (n.sup.+); the lower this carbon concentration, the shorter the distance of the diffusion of the intermediate epitaxial layer (n.sup.+).

(32) The position of the p/n boundary greatly varies in a narrow area within a chip size, particularly when the carbon concentration of the silicon substrate is nonuniformly distributed in its plane.

(33) The carbon concentration at the interface between the silicon substrate and the intermediate epitaxial layer (n.sup.+) is notable for prevention of the variations in position of the p/n boundary. A decrease in the carbon concentration at the p/n interface after the growth of the epitaxial layer enables a decrease in the concentration of carbon diffusion into the epitaxial layer of the device forming region, thereby preventing the variation in position of the p/n boundary during a thermal process in a device process after the growth of the epitaxial layer.

(34) The present invention accordingly grows the second intermediate epitaxial layer 22 on the silicon substrate 10 in a furnace for epitaxial growth by various CVD methods before the first intermediate epitaxial layer 21 is grown on the silicon substrate 10.

(35) In this way, the concentration of carbon contained in the second intermediate epitaxial layer 22 is reduced during the epitaxial growth of the second intermediate epitaxial layer 22. The carbon concentration at a boundary region between the second intermediate epitaxial layer 22 and the first intermediate epitaxial layer 21 is thereby reduced by an amount corresponding to one layer compared with the carbon concentration at a boundary region between the silicon substrate 10 and the second intermediate epitaxial layer 22. This makes the concentration of the carbon diffusion low to such an extent that the variation in position of the p/n boundary in the epitaxial layer 30 of the device forming region does not occur even when the carbon is diffused from a silicon substrate side to a wafer surface side by a thermal process in a device process.

(36) According to investigation of the behavior of diffusing carbon, the carbon is easier to diffuse to a silicon substrate bulk side than to the wafer surface side from a starting point of the surface of the silicon substrate 10. Since the degree of the diffusion to the wafer surface side, on the contrary, is smaller, the thickness of the second intermediate epitaxial layer 22 may be thin.

(37) This thickness of the second intermediate epitaxial layer 22 to be formed is preferably within a range of 0.5 mt2 m, where t is the thickness of the second intermediate epitaxial layer 22.

(38) Since the carbon in the silicon substrate diffuses to the silicon substrate bulk side more extensively than to the wafer surface side, the second intermediate epitaxial layer 22 is sufficiently effective even when its thickness is 2 m or less.

(39) In this case, the carbon concentration of the silicon substrate 10 is limited within the range from 310.sup.16 to 210.sup.17 atoms/cm.sup.3. If the carbon concentration of the silicon substrate 10 is 310.sup.16 atoms/cm.sup.3 or more, the position of the p/n boundary in the epitaxial layer 30 of the device forming region varies. The formation of the second intermediate epitaxial layer 22 is therefore essential to the prevention of this problem. If the carbon concentration of the silicon substrate 10 is 210.sup.17 atoms/cm.sup.3 or less, no large precipitates appear, and the electrical characteristics of a fabricated device is not adversely affected.

(40) The thickness of the second intermediate epitaxial layer 22 is preferably adjusted depending on the magnitude of the concentration of carbon dopant in the silicon substrate 10. This adjustment allows for the economy such as production cost of the epitaxial growth. If the carbon concentration of the silicon substrate 10 is low, for example, then the growth of the second intermediate epitaxial layer 22 can be adjusted such that its thickness becomes thin.

(41) When the thickness of the second intermediate epitaxial layer 22 is determined, it is also preferable to adjust the thickness depending on a position at which the silicon substrate 10 is cut from the silicon single crystal ingot 59.

(42) The segregation of the carbon varies its amount taken in the silicon single crystal ingot 59 pulled while being doped with carbon. Thus, the carbon concentration of the silicon single crystal ingot 59 on its cone side in the growth direction usually becomes smallest; the carbon concentration on its tail side becomes largest. The adjustment can accordingly be made as follows: for a silicon substrate cut from the first half portion of the cone side in the single crystal growth direction, the second intermediate epitaxial layer 22 is grown with a thin thickness; for a silicon substrate cut from the second half of the tail side, the second intermediate epitaxial layer 22 is grown with a thickness thicker than the thickness of the second intermediate epitaxial layer 22 of the silicon substrate cut from the first half portion.

(43) This adjustment enables the formation of the second intermediate epitaxial layer 22 with a proper thickness even when the carbon concentration of the first half portion of the cone side of the silicon single crystal ingot is less than the detection limit.

(44) The first intermediate epitaxial layer 21 is then formed on the second intermediate epitaxial layer 22. The epitaxial layer 30 of the device forming region is further stacked to obtain the inventive silicon epitaxial wafer (See FIG. 1). After that, as shown in FIG. 2, impurities such as p-type impurities to form the p-type conductive layer 30p may be implanted selectively into the epitaxial layer 30 of the device forming region, so that the p/n boundary can be formed at the boundary region between the p-type conductive layer 30p and the first intermediate epitaxial layer 21.

(45) The above description is summarized as follows. The inventor found the carbon concentration of an epitaxial layer, which is a region at which a device is to be formed, is determined by the carbon concentration of an intermediate epitaxial layer. The invention accordingly forms a second intermediate epitaxial layer before forming a first intermediate epitaxial layer, and thereby can restrain the carbon concentration of a boundary region between the first and second intermediate epitaxial layers when the first intermediate epitaxial layer has been formed. This leads to a reduction in carbon concentration of the first intermediate epitaxial layer before a thermal process, thereby enabling the inhibition of carbon diffusion into a device region in an epitaxial layer during the thermal process such that a p/n boundary is prevented from moving out of position.

(46) The invention can therefore provide an industrially excellent silicon epitaxial wafer produced with a silicon substrate doped with carbon, and a method of producing the silicon epitaxial wafer. This silicon epitaxial wafer can be used as a semiconductor device substrate such as a memory, a logic, or a solid-state image sensor.

Example

(47) The present invention will be more specifically described below with reference to an example, but the present invention is not limited to this example.

Example

(48) A silicon substrate 10 doped with carbon was first prepared.

(49) A phosphorus dopant for adjusting resistivity and 360 kg of silicon polycrystalline raw material were charged into a quartz crucible 53a having a diameter of 32 inches (800 mm) disposed in a main chamber 51a of a silicon single crystal ingot pulling apparatus 50 as shown in FIG. 5, and heated with a heater 55 to obtain a raw material melt 52.

(50) An n-type silicon single crystal ingot 59 having a diameter of 300 mm and a straight body length of 140 cm was grown while a horizontal magnetic field with a central magnetic field strength of 4000 G was applied by the magnetic field applied Czochralski (MCZ) method. In this growth, the resistivity of n-type was controlled to be 10 cm at the central portion of the straight body of the crystal. The amount of the carbon dopant was 510.sup.16 atoms/cm.sup.3 at the central portion of the crystal straight body. The n-type silicon single crystal ingot 59 was cut. A mirror polished wafer was produced through processing operations as the silicon substrate 10.

(51) An n.sup.-type second intermediate epitaxial layer 22 was then formed on the silicon substrate 10 by epitaxial growth with a phosphorus dopant in a doping amount of 4.510.sup.14 atoms/cm.sup.3. An n.sup.+-type first intermediate epitaxial layer 21 doped with phosphorus in an amount of 310.sup.17 atoms/cm.sup.3 was stacked on the second intermediate epitaxial layer 22, and then an epitaxial layer 30 of an n.sup.-type device forming region doped with phosphorus in an amount of 1.510.sup.14 atoms/cm.sup.3 was stacked thereon.

(52) Table 1 below shows the conditions of this epitaxial growth. The carrier concentration in cross section of the silicon epitaxial wafer at that time was measured by scanning spreading resistance microscopy (SSRM). The distribution of phosphorus diffusion and carbon diffusion in this cross section were evaluated by secondary ion mass spectrometry (SIMS). FIG. 6A shows the result of the relation between the carbon concentration and the carrier concentration with respect to the depth from the wafer surface.

(53) TABLE-US-00001 TABLE 1 Second intermediate First intermediate Epitaxial layer Silicon substrate epitaxial layer epitaxial layer (Device forming region) Target carbon Target Target Target concentration thickness thickness thickness Conductivity [atoms/cm.sup.3] Conductivity [m] Conductivity [m] Conductivity [m] n.sup. 5 10.sup.16 n.sup. 1.0 n.sup.+ 1.5 n.sup. 7.0

(54) Boron elements, p-type elements, were then implanted into the epitaxial layer 30 of the device forming region in an amount of 110.sup.16 atoms/cm.sup.3 to form a p-type conductive layer 30p. The carrier concentration in cross section of the silicon epitaxial wafer at that time was measured by SSRM. The p/n boundary was identified. The distribution of phosphorus diffusion and carbon diffusion in this cross section were evaluated by SIMS. FIG. 6B shows the result of the relation between the carbon concentration and the carrier concentration with respect to the depth from the wafer surface.

(55) Then, heat treatments were performed in three stages (accelerated heat treatments). The detailed conditions of the three stage heat treatments are as follows.

(56) (Conditions of Three Stage Heat Treatments)

(57) First stage: 650 C., a nitrogen atmosphere, 20 minutes

(58) Second stage: 800 C., four hours, dry oxidation

(59) Third stage: 1000 C., 14 hours, cooling after dry oxidation

(60) The carrier concentration in cross section of the silicon epitaxial wafer after the three stage heat treatments was measured by SSRM. The p/n boundary was identified. The distribution of phosphorus diffusion and carbon diffusion in this cross section were evaluated by SIMS. FIG. 6C shows the result of the relation between the carbon concentration and the carrier concentration with respect to the depth from the wafer surface. As shown in FIG. 6C, the actual position of the p/n boundary moved about 0.1 m from the designed position of the p/n boundary toward the wafer surface, where the designed position of the p/n boundary was converted to 0 m. A solid-state image sensor was then fabricated to evaluate the unevenness of an image. Consequently, no uneven image was seen.

Comparative Example

(61) A carbon-doped silicon substrate 10 having the same specifications as the above example was prepared in the same manner as the example.

(62) An n.sup.+-type first intermediate epitaxial layer 21 doped with phosphorus in an amount of 310.sup.17 atoms/cm.sup.3 was stacked on the silicon substrate 10, and then an epitaxial layer 30 of an n.sup.-type device forming region doped with phosphorus in an amount of 1.510.sup.14 atoms/cm.sup.3 was stacked thereon.

(63) Table 2 shows the conditions of this epitaxial growth. The carrier concentration and the distribution of carbon diffusion in cross section of the silicon epitaxial wafer at that time were evaluated. FIG. 7A shows the result of the relation between the carbon concentration and the carrier concentration with respect to the depth from the wafer surface.

(64) TABLE-US-00002 TABLE 2 First Epitaxial layer intermediate (Device forming Silicon substrate epitaxial layer region) Target carbon Target Con- Target Conduc- concentration Conduc- thickness duc- thickness tivity [atoms/cm.sup.3] tivity [m] tivity [m] n.sup. 5 10.sup.16 n.sup.+ 1.5 n.sup. 7.0

(65) A p-type conductive layer 30p was then formed in the epitaxial layer 30 of the device forming region as in the example. The carrier concentration in cross section of the silicon epitaxial wafer at that time was measured, and the p/n boundary was identified. The distribution of carbon diffusion was evaluated. FIG. 7B shows the result of the relation between the carbon concentration and the carrier concentration with respect to the depth from the wafer surface.

(66) Then, heat treatments were performed in three stages (accelerated heat treatments) in the same manner as the example.

(67) The carrier concentration in cross section of the silicon epitaxial wafer after the three stage heat treatments was measured, and the p/n boundary was identified. The distribution of carbon diffusion was evaluated. FIG. 7C shows the result of the relation between the carbon concentration and the carrier concentration with respect to the depth from the wafer surface. As shown in FIG. 7C, the actual position of the p/n boundary moved 0.9 m from the designed position of the p/n boundary toward the wafer surface, where the designed position of the p/n boundary was converted to 0 m. A solid-state image sensor was then fabricated to evaluate the unevenness of an image. Consequently, a strongly uneven image was seen.

(68) As seen from the results of the example and the comparative example, the present invention can produce a silicon epitaxial wafer that does not electrically impede device characteristics in operations of a semiconductor device, and stably provide a silicon epitaxial wafer that is greatly superior in electrical characteristics.

(69) It is to be noted that the present invention is not limited to the foregoing embodiment. The embodiment is just an exemplification, and any examples that have substantially the same feature and demonstrate the same functions and effects as those in the technical concept described in claims of the present invention are included in the technical scope of the present invention.

(70) For example, the present invention can be applied without being limited to the diameter, crystal orientation, conductivity, and resistivity of a silicon single crystal to be produced.