Abstract
A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
Claims
1. A transient voltage suppressing (TVS) device disposed on a semiconductor substrate comprising: a pair of steering diodes including a high side steering diode and a low side steering diode wherein the high side steering diode includes a PN junction disposed below a top surface of the semiconductor substrate in contact with a high side I/O pad that is connected to a low side I/O pad of the low side steering diode thus interconnecting the high side and low side steering diodes wherein the high side and low side steering diodes are further integrated with a main Zener diode for suppressing a transient voltage wherein the Zener diode constituting a PN junction as vertical diodes connected to a Vcc terminal through a top doped region under the top surface of the semiconductor substrate wherein the Zener diode is triggered for conducting a current along a vertical direction when an input voltage from the I/O pads is higher than a Vcc voltage; and the high side steering diode is overlapped with the Zener diode between two isolation trenches wherein the low side steering diode is disposed on an opposite side of one of the isolation trenches.
2. The transient voltage suppressing (TVS) device of claim 1 wherein: the high side steering diode further includes a P-epitaxial layer interfacing with a buried N dopant region and the Zener diode comprises the buried N-dopant region interfacing a deep buried body dopant region having a higher dopant concentration than the P-epitaxial layer.
3. The transient voltage suppressing (TVS) device of claim 1 wherein: the high side steering diodes further includes a lightly doped body dopant epitaxial layer disposed below the high side I/O pad and above a buried source dopant layer and the buried source dopant region is above a shallow body dopant region having a higher body dopant concentration than the lightly doped body region underneath that is functioning as part of the Zener diode and further for reducing a junction capacitance of the high side steering diodes.
4. The transient voltage suppressing (TVS) device of claim 1 wherein: the low side steering diodes comprises a lightly doped body dopant epitaxial layer disposed below the low side I/O pad and the lightly doped body dopant epitaxial layer is disposed above and interfaces a source region.
5. The transient voltage suppressing (TVS) device of claim 1 wherein: the semiconductor substrate further includes a bottom electrode disposed on a bottom surface of the semiconductor substrate for connecting to a ground voltage.
6. The transient voltage suppressing (TVS) device of claim 1 wherein: The isolation trenches extend vertically to a depth in the semiconductor substrate below the Zener diode.
7. The transient voltage suppressing (TVS) device of claim 1 wherein: a Vcc electrode disposed above the top doped region of the Zener diode and the Vcc electrode is insulated from the high side and low side I/O pad by a top insulation layer.
8. The transient voltage suppressing (TVS) device of claim 1 further comprising: the semiconductor substrate further includes a top P-type epitaxial layer and a buried N-type dopant region below the P-type epitaxial layer and the high side steering diode is a PN junction between the top P-type epitaxial layer and the N-type buried dopant region.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) FIG. 1A-1 shows the circuit of a conventional TVS circuit implemented with diode array commonly applied for electrostatic discharge (ESD) protection.
(2) FIGS. 1A-2 and 1A-3 are two diagrams to show the integration of the steering diodes with the Zener diode to achieve low capacitance in unidirectional and bi-directional blocking TVS diodes respectively.
(3) FIG. 1B shows a standard circuit diagram for a conventional TVS circuit and FIGS. 1B-1 is a cross sectional views for showing the actual implementation of the TVS circuit applying the CMOS processing technologies to provide the TVS circuit as integrated circuit (IC) chips.
(4) FIG. 1C shows a TVS circuit implemented with diodes formed as vertical diodes to reduce the size of the TVS circuit.
(5) FIGS. 2 to 4 are cross sectional views for the integrated Zener diode with the high side and low side steering diodes illustrated with equivalent circuits of TVS devices implemented with N+ buried layer and isolation trenches to form vertical TVS diode arrays of this invention to reduce the areas occupied by the diode array.
(6) FIGS. 5A to 5B are top views of the layout of the TVS devices to show the reduced areas required by implementing the vertical diode array of this invention.
(7) FIG. 6 is a cross sectional view for illustrating the capacitance components of a TVS circuit configured with N-buried layer (NBL) TVS Zener.
(8) FIG. 7 is a diagram for illustrating the low capacitance designs for the steering diode as implemented for optimizing the design parameters in this invention.
(9) FIG. 8 is a diagram for showing the variation of the junction capacitance versus the doping concentration N.sub.D for an abrupt N+P junction.
(10) FIG. 9 is a diagram for showing the variation of the depletion width W.sub.D versus the doping concentration N.sub.D for an abrupt N+P junction.
(11) FIGS. 10A-10D are cross sectional views illustrating the forming of the NBL and the trigger implant layer.
DETAILED DESCRIPTION OF THE EMBODIMENTS
(12) Refer to FIG. 2 for a side cross sectional view illustrated with equivalent circuit of a transient voltage suppressor (TVS) 100 of this invention. The TVS 100 is formed on a heavily doped P+ semiconductor substrate 105 which supports a P two-layer epitaxial layer 110 that includes a bottom P epitaxial 110-1 and a top P epitaxial layer 110-2 with a backside metal 101 disposed below the bottom surface to function as a ground terminal. The TVS 100 includes a P+ region high-side steering diode and Zener diode overlapping zone with a deep voltage breakdown (VBD) trigger implant layer 115 implanted with P+ dopant ions disposed between the bottom epitaxial layer 110-1 and a N+ buried layer 120 disposed below a top N+ source region 125. The Zener diode is formed from the buried layer 120 to the bottom epitaxial layer 110-1. A shallow P+ implant region 130 is formed near the top surface of the top P epitaxial layer 110-2 to enhance the electrical contact with an I/O metal pad 135. An oxide insulation layer 145 covering the top surface has openings to allow a Vcc pad 140 to contact the N+ source regions 125 above the high-side diode and Zener diode overlapping zone and an I/O pad 135 contacting the source region 125 of the low side diode shown on the right side of the TVS 100, and for the I/O pad 135 to contact the shallow P+implant region 130. The I/O pad 135 and the I/O pad 135 may be connected in the third dimension. The N+ source regions 125 has a gap in which the high-side diode is located from the top P-epitaxial layer 110-2 to the N+ buried layer 120. The low side diode is located from the source region 125 to the two-layer epitaxial layer 110. The TVS 100 further includes isolation trenches 150 to isolate the low-side steering diode with the high-side diode integrated with the overlapping Zener diode. A parasitic vertical PNP transistor is exists, from the shallow P+ implant region and the portions of the P-epitaxial region 110-2 below it, to the N+ buried layer 120, to N-epitaxial layer 110-1 below. By having a highly doped N+ buried layer 120, the transistor action is avoided. The parasitic vertical PNP transistor is part of a parasitic PNPN thysistor formed in the semiconductor regions between I/O metal pads 135 and 135. A weaker PNP transistor will ensure that the parasitic thyristor does not turn on in applications that require the Vcc and Gnd terminals to be left floating. It is desired to not allow the steering diodes to breakdown, so the breakdown voltage of the Zener diode is made to be much lower than that of the steering diodes. The VBD trigger layer sets the breakdown voltage of the Zener diode at a desired low value.
(13) FIG. 3 is a cross sectional view for showing an alternate TVS 100 of this invention. The TVS 100 has a similar configuration as the TVS 100 shown in FIG. 2 except that the deep voltage breakdown (VBD) trigger layer 115 is formed with a patterned implant to form a gap under the high side steering diode in order to avoid a high doping layer directly under the high-side steering diode. This may avoid inadvertently raising the doping concentration of the portion of P-epitaxial layer 110-2 beneath the P+ implant region 130. This region should be kept at a low doping concentration to achieve low capacitance as explained below. FIG. 4 is a cross sectional view for showing another alternate TVS 100 of this invention. The TVS 100 has a similar configuration as the TVS 100 and 100 shown in FIGS. 2 and 3 respectively except that the N+ buried layer 120 is patterned with a gap in it and the deep voltage breakdown trigger layer 115 is formed adjacent and in between instead of under the N+ buried layer 120.
(14) FIGS. 5A and 5B are top views for showing the layouts of a TVS according to a configuration shown in FIGS. 1B-1 and 2 respectively. As shown in FIG. 5A, the main Zener diode is formed on a separate area from the high side diode. In comparison, in FIG. 5B, the high side diode is overlapped with the Zener diode and therefore the TVS is formed with much reduced area compared with the TVS as that shown in FIG. 5A.
(15) FIG. 6 is a cross sectional view shown with capacitance equivalent circuit to illustrate the total capacitance of the Zener diode C.sub.Z in combination with the high-side and the low-side diodes C.sub.HS and C.sub.LS respectively. Assuming that C.sub.Z is much greater than C.sub.HS or C.sub.LS, the total capacitance C.sub.Total can be expressed as:
C.sub.Total=.sub.PNP*(C.sub.HS)+C.sub.LS+C.sub.(Pad)
(16) Where .sub.PNP is the emitter to collector gain of the vertical PNP transistor formed by P-epitaxial layer 110-2, N+ buried layer 120 and P epitaxial layer 110-1, and C (Pad) is the pad capacitance. According to the above equation, it is necessary to reduce the capacitance of the high-side and low-side steering diodes C.sub.HB and C.sub.LS in order to achieve a low capacitance for the TVS; since C.sub.Z is much greater than and in series with C.sub.HS, C.sub.Z has a negligible effect on CTotal. FIG. 7 illustrates the depletion width W.sub.D for an abrupt N+/P junction. For a vertical diode the depletion width is in the vertical direction, so the depth of the P-layer should be at least as large as the depletion width W.sub.D. However, the P-layer depth should not be much larger than W.sub.D or it will needlessly increase the forward resistance of the diode. For an abrupt N+ and P junction, the junction capacitance Cj and breakdown voltage V.sub.BD are:
Cj(N.sub.A).sup.1/2
V.sub.BD(NA).sup.3/4*(NPT)
(17) Where N.sub.A represents the doping concentration of the P region and NPT represents the Non-Punch Through breakdown voltage. The capacitance of the steering diodes decreases with a higher breakdown voltage when the dopant concentration is reduced as that shown in FIG. 8 for showing the junction capacitance Cj as a function of the dopant concentration and FIG. 9 for showing the depletion width W.sub.D in the epitaxial layer as function of the dopant concentration. FIG. 8 shows the junction capacitance Cj rising with the P dopant concentration. Therefore, optimal performance of the TVS is achievable by determining a lower epitaxial layer dopant concentration for the P-epitaxial layers 110-2 and then using that dopant concentration to determine an optimal thickness of the P-epitaxial layer 110-2 according to a width of the depletion layer thickness as shown in FIG. 9. For the high side diode, the capacitance is formed between the P+ implant region 130 and the NBL 120, so the vertical distance of the region of P-epitaxial layer 110-2 between P+ implant region 130 and N+ buried layer 120 should match the depletion width to achieve low capacitance. That vertical distance should be kept close to the depletion width to avoid needlessly increasing the forward resistance of the diode. For the low side diode, the vertical distance from source region 125 to substrate 105 should approximately match the depletion width (taking into account the doping concentrations of epitaxial layers 110-1 and 110-2). The thickness of the first epitaxial layer 110-1 should also take into account both the depletion width of the low side diode and also the distance from the high side diode; if the substrate 105 is too close to the high side diode, some of the dopants from the substrate 105 may diffuse into the region of the second epitaxial layer 110-2 under the contact implant 130 and increase the doping there and thus increase the capacitance of the high side diode. In a preferred embodiment, the dopant concentration of the P-epitaxial layers 110-1 and 110-2 will be as kept low as possible, to ensure a low capacitance in the steering diodes. The N+ buried layer 120 under the source region 125 is implanted with a highest dose with minimum diffusion by applying an automatic doping process while satisfying the breakdown voltage requirements of the vertical Zener diode.
(18) FIGS. 10A-D demonstrate a method for forming the NBL for a device similar to device 100 in FIG. 3. FIG. 10A shows a heavily doped P+ substrate 105 with a lightly doped first P-epi layer 110-1 grown over it. In FIG. 10B, a masked implant (mask not shown) is performed to form the N+ implant region 121. In FIG. 10C, a drive-in is performed to diffuse the N+ implant region 121 to form NBL 120. In FIG. 10C, another masked implant (mask not shown) is performed to form the P+ VBD trigger implant layer 115 underneath the NBL 120. In FIG. 10D, the second P-epi layer 110-2 is grown over the first P-epi layer 110-1. The NBL 120 may diffuse slightly into the second epitaxial layer 110-2.
(19) Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. For example, the conductivity types of the semiconductor regions could be reversed so that the P-type regions are now N-type regions and vice versa. In this case the high side diode and the low side diode would swap positions; also the topside of semiconductor would have the lower voltage and the bottom side would have the higher voltage. Various alterations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.
