Ripple pre-amplification based fully integrated low dropout regulator

Abstract

A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage V.sub.fb. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor M.sub.P is connected to the output terminal of the error amplifier, the source terminal of the power transistor M.sub.P is connected to an input voltage V.sub.IN, and the drain terminal of the power transistor M.sub.P is grounded.

Claims

1. A ripple pre-amplification based fully integrated low dropout regulator, comprising: an error amplifier, a power transistor, a miller capacitance, a first voltage dividing resistor, a second voltage dividing resistor, a compensation circuit, a transconductance amplifier, and a transimpedance amplifier, wherein a gate terminal of the power transistor is connected to an output terminal of the error amplifier, a source terminal of the power transistor is connected to an input voltage, and a drain terminal of the power transistor is connected to ground through a series connection structure of the first voltage dividing resistor and the second voltage dividing resistor; a series connection point of the first voltage dividing resistor and the second voltage dividing resistor outputs a feedback voltage; the Miller capacitance is connected between the drain terminal of the power transistor and the ground; the compensation circuit is connected between the drain terminal of the power transistor and the series connection point of the first voltage dividing resistor and the second voltage dividing resistor; wherein a positive input terminal of the transconductance amplifier is connected to a reference voltage, a negative input terminal of the transconductance amplifier is connected to the feedback voltage, an output terminal of the transconductance amplifier is connected to a negative input terminal of the transimpedance amplifier and a negative input terminal of the error amplifier; and a positive input terminal of the transimpedance amplifier is connected to the ground, and an output terminal of the transimpedance amplifier is connected to a positive input terminal of the error amplifier wherein the transconductance amplifier comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a fifth PMOS transistor; wherein a gate terminal of the second PMOS transistor serve as the negative input terminal of the transconductance amplifier, and a gate terminal of the third PMOS transistor serve as the positive input terminal of the transconductance amplifier; a drain terminal of the first PMOS transistor is connected to source terminals of the second PMOS transistor and the third PMOS transistor, and a gate terminal of the first PMOS transistor is connected to a bias voltage; the first NMOS transistor and the third NMOS transistor constitute a first current mirror, a first mirror ratio is 1:K.sub.1, where K.sub.1 is any real number; the second NMOS transistor and the fourth NMOS transistor constitute a second current mirror, and a second mirror ratio is 1:K.sub.1, where K.sub.1 is any real number; a gate terminal and a drain terminal of the first NMOS transistor are short-circuited and connected to a drain terminal of the second PMOS transistor and a gate terminal of the third NMOS transistor; a gate terminal and a drain terminal of the second NMOS transistor are short-circuited and connected to a drain terminal of the third PMOS transistor and a gate terminal of the fourth NMOS transistor; a gate terminal and a drain terminal of the fifth PMOS transistor are short-circuited and connected to a drain terminal of the third NMOS transistor and a gate terminal of the fourth PMOS transistor; a drain terminal of the fourth NMOS transistor and a drain terminal of the fourth PMOS transistor are connected to each other and serve as the output terminal of the transconductance amplifier; source terminals of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected to the ground; and source terminals of the first PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are connected to the input voltage.

2. The ripple pre-amplification based fully integrated low dropout regulator according to claim 1, wherein the transimpedance amplifier comprises a resistor, a fifth NMOS transistor and a sixth PMOS transistor, a gate terminal of the fifth NMOS transistor and a gate terminal of the sixth PMOS transistor are connected to each other and serve as the negative input terminal of the transimpedance amplifier; a drain terminal of the fifth NMOS transistor and a drain terminal of the sixth PMOS transistor are connected to each other and serve as the output terminal of the transimpedance amplifier; a source terminal of the fifth NMOS transistor serve as the positive input terminal of the transimpedance amplifier; a source terminal of the sixth PMOS transistor is connected to the input voltage; and the resistor is connected between the negative input terminal and the output terminal of the transimpedance amplifier.

3. The ripple pre-amplification based fully integrated low dropout regulator according to claim 2, wherein the error amplifier comprises a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; wherein a gate terminal of the seventh NMOS transistor and a gate terminal of the eighth NMOS transistor are connected to each other and serve as the negative input terminal of the error amplifier; a width to length ratio of the seventh NMOS transistor and the eighth NMOS transistor is K.sub.2, where K.sub.2 is any real number; a gate terminal of the sixth NMOS transistor and a gate terminal of the ninth NMOS transistor are connected to each other and serve as a positive input terminal of the error amplifier; a width to length ratio of the sixth NMOS transistor and the ninth NMOS transistor is K.sub.2, where K.sub.2 is any real number; a gate terminal and a drain terminal of the tenth PMOS transistor are short-circuited and connected to a gate terminal of the seventh PMOS transistor and a drain terminal of the eleventh NMOS transistor; a gate terminal of the tenth NMOS transistor is connected to a gate terminal of the eleventh NMOS transistor and drain terminals of the seventh NMOS transistor and the eighth PMOS transistor; a drain terminal of the tenth NMOS transistor is connected to source terminals of the seventh NMOS transistor and the ninth NMOS transistor; a gate terminal of the twelfth NMOS transistor is connected to a gate terminal of the thirteenth NMOS transistor and drain terminals of the sixth NMOS transistor and the ninth PMOS transistor; a drain terminal of the twelfth NMOS transistor is connected to source terminals of the sixth NMOS transistor and the eighth NMOS transistor; a gate terminal of the eighth PMOS transistor and a gate terminal of the ninth PMOS transistor are connected to a bias voltage; a drain terminal of the seventh PMOS transistor and a drain terminal of the thirteenth NMOS transistor are connected to each other and serve as the output terminal of the error amplifier; source terminals of the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are connected to the ground; and source terminals of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor and drain terminals of the eighth NMOS transistor and the ninth NMOS transistor are connected to the input voltage.

4. The ripple pre-amplification based fully integrated low dropout regulator according to claim 3, wherein the compensation circuit comprises a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a capacitance; wherein a drain terminal of the twelfth PMOS transistor and a drain terminal of the sixteenth NMOS transistor are connected to each other and connected to the series connection point of the first voltage dividing resistor and the second voltage dividing resistor; the eleventh PMOS transistor and the twelfth PMOS transistor constitute a third current mirror and a third mirror ratio is 1:K.sub.4, where K.sub.4 is any real number; a gate terminal and a drain terminal of the eleventh PMOS transistor are short-circuited and connected to a gate terminal of the twelfth PMOS transistor and a drain terminal of the fifteenth NMOS transistor; a gate terminal and a drain terminal of the fourteenth NMOS transistor are short-circuited and connected to a drain terminal of the thirteenth PMOS transistor and a gate terminal of the fifteenth NMOS transistor; the capacitance is connected between a drain terminal of the power transistor and a drain terminal of the fourteenth NMOS transistor; a gate terminal of the thirteenth PMOS transistor and a gate terminal of the sixteenth NMOS transistor are connected to the bias voltage; source terminals of the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor are connected to the input voltage; and source terminals of the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the sixteenth NMOS transistor are connected to the ground.

5. The ripple pre-amplification based fully integrated low dropout regulator according to claim 1, wherein each of the first voltage dividing resistor and the second voltage dividing resistor is a PMOS transistor with short-circuited gate terminal and drain terminal.

6. A ripple pre-amplification based fully integrated low dropout regulator, comprising: an error amplifier, a power transistor, a miller capacitance, a first voltage dividing resistor, a second voltage dividing resistor, a compensation circuit, a transconductance amplifier, and a transimpedance amplifier, wherein a gate terminal of the power transistor is connected to an output terminal of the error amplifier, a source terminal of the power transistor is connected to an input voltage, and a drain terminal of the power transistor is connected to ground through a series connection structure of the first voltage dividing resistor and the second voltage dividing resistor; a series connection point of the first voltage dividing resistor and the second voltage dividing resistor outputs a feedback voltage; the Miller capacitance is connected between the drain terminal of the power transistor and the ground; the compensation circuit is connected between the drain terminal of the power transistor and the series connection point of the first voltage dividing resistor and the second voltage dividing resistor; wherein a positive input terminal of the transconductance amplifier is connected to a reference voltage, a negative input terminal of the transconductance amplifier is connected to the feedback voltage, an output terminal of the transconductance amplifier is connected to a negative input terminal of the transimpedance amplifier and a negative input terminal of the error amplifier; and a positive input terminal of the transimpedance amplifier is connected to the ground, and an output terminal of the transimpedance amplifier is connected to a positive input terminal of the error amplifier wherein the error amplifier comprises a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor; wherein a gate terminal of the seventh NMOS transistor and a gate terminal of the eighth NMOS transistor are connected to each other and serve as the negative input terminal of the error amplifier; a width to length ratio of the seventh NMOS transistor and the eighth NMOS transistor is K.sub.2, where K.sub.2 is any real number; a gate terminal of the sixth NMOS transistor and a gate terminal of the ninth NMOS transistor are connected to each other and serve as a positive input terminal of the error amplifier; a width to length ratio of the sixth NMOS transistor and the ninth NMOS transistor is K.sub.2, where K.sub.2 is any real number; a gate terminal and a drain terminal of the tenth PMOS transistor are short-circuited and connected to a gate terminal of the seventh PMOS transistor and a drain terminal of the eleventh NMOS transistor; a gate terminal of the tenth NMOS transistor is connected to a gate terminal of the eleventh NMOS transistor and drain terminals of the seventh NMOS transistor and the eighth PMOS transistor; a drain terminal of the tenth NMOS transistor is connected to source terminals of the seventh NMOS transistor and the ninth NMOS transistor; a gate terminal of the twelfth NMOS transistor is connected to a gate terminal of the thirteenth NMOS transistor and drain terminals of the sixth NMOS transistor and the ninth PMOS transistor; a drain terminal of the twelfth NMOS transistor is connected to source terminals of the sixth NMOS transistor and the eighth NMOS transistor; a gate terminal of the eighth PMOS transistor and a gate terminal of the ninth PMOS transistor are connected to a bias voltage; a drain terminal of the seventh PMOS transistor and a drain terminal of the thirteenth NMOS transistor are connected to each other and serve as the output terminal of the error amplifier; source terminals of the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, and the thirteenth NMOS transistor are connected to the ground; and source terminals of the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor and drain terminals of the eighth NMOS transistor and the ninth NMOS transistor are connected to the input voltage.

7. The ripple pre-amplification based fully integrated low dropout regulator according to claim 6, wherein the compensation circuit comprises a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a capacitance; wherein a drain terminal of the twelfth PMOS transistor and a drain terminal of the sixteenth NMOS transistor are connected to each other and connected to the series connection point of the first voltage dividing resistor and the second voltage dividing resistor; the eleventh PMOS transistor and the twelfth PMOS transistor constitute a third current mirror and a third mirror ratio is 1:K.sub.4, where K.sub.4 is any real number; a gate terminal and a drain terminal of the eleventh PMOS transistor are short-circuited and connected to a gate terminal of the twelfth PMOS transistor and a drain terminal of the fifteenth NMOS transistor; a gate terminal and a drain terminal of the fourteenth NMOS transistor are short-circuited and connected to a drain terminal of the thirteenth PMOS transistor and a gate terminal of the fifteenth NMOS transistor; the capacitance is connected between a drain terminal of the power transistor and a drain terminal of the fourteenth NMOS transistor; a gate terminal of the thirteenth PMOS transistor and a gate terminal of the sixteenth NMOS transistor are connected to the bias voltage; source terminals of the eleventh PMOS transistor, the twelfth PMOS transistor, and the thirteenth PMOS transistor are connected to the input voltage; and source terminals of the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the sixteenth NMOS transistor are connected to the ground.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a topology structural diagram of a traditional Cap-less LDO circuit.

(2) FIG. 2 is a configuration diagram of the ripple pre-amplification based fully integrated low dropout regulator provided by the present invention.

(3) FIG. 3 is a schematic diagram showing transistor-level circuit implementation of the ripple pre-amplification based fully integrated low dropout regulator provided by the present invention.

(4) FIG. 4 is a schematic diagram showing a design of the distribution of the zero poles of the loop of the ripple pre-amplification based fully integrated low dropout regulator provided by the present invention.

(5) FIG. 5 is a schematic diagram showing an AC simulation curve of the ripple pre-amplification based fully integrated low dropout regulator provided by the present invention.

(6) FIG. 6 is a schematic diagram showing the transient response curve of the ripple pre-amplification based fully integrated low dropout regulator provided by the present invention.

DETAILED DESCRIPTION

(7) The present invention will be described in detail with reference to the drawings and the embodiments.

(8) FIG. 2 shows a configuration diagram of the ripple pre-amplification based fully integrated low dropout regulator provided by the present invention which includes an error amplifier, a power transistor M.sub.P, a Miller capacitance C.sub.L, a first voltage dividing resistor R.sub.f1, a second voltage dividing resistor R.sub.f2, and a compensation circuit. The gate terminal of the power transistor M.sub.P is connected to the output terminal of the error amplifier, the source terminal of the power transistor M.sub.P is connected to the input voltage V.sub.IN, and the drain terminal of the power transistor M.sub.P is connected to the ground GND through the series connection structure of the first voltage dividing resistor R.sub.f1 and the second voltage dividing resistor R.sub.f1. The series connection point of the first voltage dividing resistor R.sub.f1 and the second voltage dividing resistor R.sub.f1 outputs the feedback voltage V.sub.fb. The Miller capacitance C.sub.L is connected between the drain terminal of the power transistor M.sub.P and the ground GND. The compensation circuit is connected between the drain terminal of the power transistor M.sub.P and the series connection point of the first voltage dividing resistor R.sub.f1 and the second voltage dividing resistor R.sub.f1. The ripple pre-amplification based fully integrated low dropout regulator also includes a transconductance amplifier and a transimpedance amplifier. The positive input terminal of the transconductance amplifier is connected to the reference voltage V.sub.ref, the negative input terminal of the transconductance amplifier is connected to the feedback voltage V.sub.fb, the output terminal of the transconductance amplifier is connected to the negative input terminal of the transimpedance amplifier and the negative input terminal of the error amplifier, the positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier.

(9) In this embodiment, the transconductance amplifier OTA uses a classical push-pull transconductance amplifier structure shown in FIG. 3, which includes first NMOS transistor M.sub.N1, second NMOS transistor M.sub.N2, third NMOS transistor M.sub.N3, fourth NMOS transistor M.sub.N4, first PMOS transistor M.sub.P1, second PMOS transistor M.sub.P2, third PMOS transistor M.sub.P3, fourth PMOS transistor M.sub.P4, and fifth PMOS transistor M.sub.P5. The gate terminal of the second PMOS transistor M.sub.P2 serve as the negative input terminal of the transconductance amplifier. The gate terminal of the third PMOS transistor M.sub.P3 serve as the positive input terminal of the transconductance amplifier. The drain terminal of the first PMOS transistor M.sub.P1 is connected to the source terminals of the second PMOS transistor M.sub.P2 and the third PMOS transistor M.sub.P3, and the gate terminal of the first PMOS transistor M.sub.P1 is connected to the bias voltage V.sub.bias. The first NMOS transistor M.sub.N1 and the third NMOS transistor M.sub.N3 constitute a first current mirror, and the mirror ratio is 1:K.sub.1. The second NMOS transistor M.sub.N2 and the fourth NMOS transistor M.sub.N4 constitute a second current mirror, and the mirror ratio is 1:K.sub.1. The gate terminal and drain terminal of the first NMOS transistor M.sub.N1 are short-circuited and connected to the drain terminal of the second PMOS transistor M.sub.P2 and the gate terminal of the third NMOS transistor M.sub.N3. The gate terminal and drain terminal of the second NMOS transistor M.sub.N2 are short-circuited and connected to the drain terminal of the third PMOS transistor M.sub.P3 and the gate terminal of the fourth NMOS transistor M.sub.N4. The gate terminal and drain terminal of the fifth PMOS transistor M.sub.P5 are short-circuited and connected to the drain terminal of the third NMOS transistor M.sub.N3 and the gate terminal of the fourth PMOS transistor M.sub.P4. The drain terminals of the fourth NMOS transistor M.sub.N4 and the fourth PMOS transistor M.sub.P4 are connected to each other and serve as the output terminal of the transconductance amplifier. The source terminals of the first NMOS transistor M.sub.N1, the second NMOS transistor M.sub.N2, the third NMOS transistor M.sub.N3, and the fourth NMOS transistor M.sub.N4 are connected to the ground GND. The source terminals of the first PMOS transistor M.sub.P1, the fourth PMOS transistors M.sub.P4, and the fifth PMOS transistors M.sub.P5 are connected to the input voltage V.sub.IN.

(10) In this embodiment, the transimpedance amplifier TIA includes the resistor R.sub.f, fifth NMOS transistor M.sub.N5, and the sixth PMOS transistor M.sub.N5. The gate terminals of the fifth NMOS transistor M.sub.N5 and the sixth PMOS transistor MS are connected to each other and serve as the negative input terminal of the transimpedance amplifier. The drain terminals of the fifth NMOS transistor M.sub.N5 and the sixth PMOS transistor M.sub.P6 are connected to each other and serve as the output terminal of the transimpedance amplifier. The source terminal of the fifth NMOS transistor M.sub.N5 serve as the positive input terminal of the transimpedance amplifier. The source terminal of the sixth PMOS transistor M.sub.P6 is connected to the input voltage V.sub.IN. The resistor R.sub.f is connected between the negative input terminal and output terminal of the transimpedance amplifier.

(11) In this embodiment, the error amplifier includes sixth NMOS transistor M.sub.N6, seventh NMOS transistor M.sub.N7, eighth NMOS transistor M.sub.N5, ninth NMOS transistor M.sub.N9, tenth NMOS transistor M.sub.N10, eleventh NMOS transistor M.sub.N11, twelfth NMOS transistor M.sub.N12, thirteenth NMOS transistor M.sub.N13, seventh PMOS transistor M.sub.P7, eighth PMOS transistor M.sub.P8, ninth PMOS transistor M.sub.P9, and tenth PMOS transistor M.sub.P10. The gate terminals of the seventh NMOS transistor M.sub.N7 and the eighth NMOS transistor M.sub.N8 are connected to each other and serve as the negative input terminal of the error amplifier. The width to length ratio of the seventh NMOS transistor M.sub.N7 and the eighth NMOS transistor M.sub.N8 is K.sub.2. The gate terminals of the sixth NMOS transistor M.sub.N6 and the ninth NMOS transistor M.sub.N9 are connected to each other and serve as the positive input terminal of the error amplifier. The gate terminal and drain terminal of the tenth PMOS transistor M.sub.P10 are short-circuited and connected to the gate terminal of the seventh PMOS M.sub.P7 and the drain terminal of the eleventh NMOS M.sub.N11. The gate terminal of the tenth NMOS transistor M.sub.N10 is connected to the gate terminal of the eleventh NMOS transistor M.sub.N11 and the drain terminals of the seventh NMOS transistor M.sub.N7 and the eighth PMOS transistor M.sub.P5. The drain terminal of the tenth NMOS M.sub.N10 is connected to the source terminals of the seventh NMOS transistor M.sub.N7 and the ninth NMOS transistor M.sub.N9. The gate terminal of the twelfth NMOS transistor M.sub.N12 is connected to the gate terminal of the thirteenth NMOS transistor M.sub.N13 and the drain terminals of the sixth NMOS transistor M.sub.N6 and the ninth PMOS transistor M.sub.P9. The drain terminal of the twelfth NMOS transistor M.sub.N12 is connected to the source terminals of the sixth NMOS transistor M.sub.N6 and the eighth NMOS transistor M.sub.N8. The gate terminals of the eighth PMOS transistor M.sub.P8 and the ninth PMOS transistor M.sub.P9 are connected to the bias voltage V.sub.bias. The drain terminals of the seventh PMOS transistor M.sub.P7 and the thirteenth NMOS transistor M.sub.N13 are connected to each other and serve as the output terminal of the error amplifier. The source terminals of the tenth NMOS transistor M.sub.N10, the eleventh NMOS transistor M.sub.N11, the twelfth NMOS transistor M.sub.N12 and the thirteenth NMOS transistor M.sub.N13 are connected to the ground GND. The source terminals of the seventh PMOS transistor M.sub.P7, the eighth PMOS transistor M.sub.P5, the ninth PMOS transistor M.sub.P9, and the tenth PMOS M.sub.P10 and the drain terminals of the eighth NMOS transistor M.sub.N8 and the ninth NMOS transistor M.sub.N9 are connected to the input voltage V.sub.IN.

(12) The transconductance amplifier (e.g. operational transconductance amplifier OTA) detects the difference between the feedback voltage V.sub.fb divided by the output terminal of the LDO and the reference voltage V.sub.ref, and draws/feeds a current to the resistor R.sub.f of the transconductance amplifier (TIA), so that a large differential voltage is formed at the input terminal of the error amplifier (EA). The differential voltage is amplified by the error amplifier (EA), then a large current is drawn out from the input power supply V.sub.IN and mirrored to the output stage to determine the gate terminal potential of the power transistor M.sub.P and provide a corresponding load current I.sub.L. Since a dynamic bias structure is used in the error amplifier (EA) in this embodiment, the larger the differential input voltage, the larger is the output current. As a result, with the use of the ripple pre-amplification function, the present invention can better benefit from the advantages to achieve better dynamic adjustment performance.

(13) The loop low frequency gain can be calculated as according to the following equation:
A.sub.LG=K.sub.1g.sub.mP2R.sub.fK.sub.2g.sub.miK.sub.3(r.sub.oN13r.sub.oP7)G.sub.MPR.sub.OUT(1)

(14) where G.sub.MP, R.sub.OUT represent the transconductance and output impedance of the power transistor M.sub.P, respectively. K.sub.1-K.sub.3 are the mirror ratios in FIG. 3, g.sub.mP2, g.sub.mi are the transconductance relative to the transistor of the inputs of the operational transconductance amplifier (OTA) and the error amplifier (EA), respectively, r.sub.oN13, r.sub.oP7 are the small-signal equivalent impedances of the thirteenth NMOS transistor M.sub.N13 and the seventh PMOS transistor M.sub.P7 of the output stage of the error amplifier (EA), respectively.

(15) The present invention provides a loop compensation solution. The compensation circuit in this embodiment includes fourteenth NMOS transistor M.sub.N14, fifteenth NMOS transistor M.sub.N15, sixteenth NMOS transistor M.sub.N16, eleventh PMOS transistor M.sub.P11, twelfth PMOS transistor M.sub.P12, thirteenth PMOS transistor M.sub.P13, and the capacitance C.sub.Z. The drain terminals of the twelfth PMOS transistor M.sub.P12 and the sixteenth NMOS transistor M.sub.N16 are connected to each other and connected to the series connection point of the first voltage dividing resistor R.sub.f1 and the second voltage dividing resistor R.sub.f2. The eleventh PMOS transistor M.sub.P11 and the twelfth PMOS transistor M.sub.P12 constitute a third current mirror, and the mirror ratio is 1:K.sub.4. The gate terminal and drain terminal of the eleventh PMOS transistor M.sub.P11 are short circuited and connected to the gate terminal of the twelfth PMOS transistor M.sub.P12 and the drain terminal of the fifteenth NMOS transistor M.sub.N15. The gate terminal and drain terminal of the fourteenth NMOS transistor M.sub.N14 are short circuited and connected to the drain terminal of the thirteenth PMOS transistor M.sub.13 and the gate terminal of the fifteenth NMOS transistor M.sub.N15. The capacitance C.sub.Z is connected between the drain terminal of the power transistor M.sub.P and the drain terminal of the fourteenth NMOS transistor M.sub.N14. The gate terminals of the thirteenth PMOS transistor M.sub.P13 and the sixteenth NMOS transistor M.sub.N16 are connected to the bias voltage V.sub.bias. The source terminals of the eleventh PMOS transistor M.sub.P11, the twelfth PMOS transistor M.sub.P12, and the thirteenth PMOS transistor M.sub.P13 are connected to the input voltage V.sub.IN. The source terminals of the fourteenth NMOS transistor M.sub.N14, the fifteenth NMOS transistor M.sub.N15, and the sixteenth NMOS transistor M.sub.N16 are connected to the ground GND. In this embodiment, the first voltage dividing resistor R.sub.f1 and the second voltage dividing resistor R.sub.f1 are PMOS transistors with gate terminals and drain terminals short circuited, i.e. M.sub.PL1 and M.sub.PL2 in FIG. 3.

(16) The compensation circuit does not change V.sub.fb in the case of direct current (DC), and a current is fed into the voltage dividing point of the LDO through the capacitance C.sub.Z in the case of alternating current (AC), thereby producing a pair of zero poles .sub.ZC, which are respectively expressed as below:

(17) $\begin{array}{cc}{}_{\mathrm{ZC}}=-\frac{g_{\mathrm{mP}10}{g}_{\mathrm{mL}}}{C_Z\left(K_4{g}_{\mathrm{mP}10}+g_{\mathrm{mL}}\right)}& \left(2\right)\\ {}_{\mathrm{pl}}=-\frac{g_{\mathrm{mP}10}}{C_Z}& \left(3\right)\end{array}$
where g.sub.mL represents the transconductance of M.sub.PL1 and M.sub.PL2 in FIG. 3, with the compensation circuit, the output pole does not need to be completely outside the gain bandwidth product GBW. If the parameters are set properly, the zero point can be slightly higher than the gain bandwidth product GBW to compensate a part of the phase margin caused by appearance of the output pole in the gain bandwidth product GBW and at the same time the parasitic pole is pushed to high frequency to be offset with zero points of left half plane formed by Miller compensation. In this way, the Miller capacitance does not need to be excessively increased, and the compulsory output pole is outside the gain bandwidth product GBW, as a result, not only the area of the chip is reduced, but also the gain bandwidth product GBW is increased.

(18) FIG. 4 shows a loop stability design of the LDO of the present invention. The zero poles with position changes under light and heavy loads condition are represented by .sub.pD in light load condition and .sub.pD in heavy load condition. The zero poles in the medium and high frequency are ignored, only the main pole .sub.pD at the gate terminal of the power transistor M.sub.P, the output pole .sub.pO of the LDO, the Miller zero pole .sub.zm, and the pair of zero poles .sub.zc, .sub.pl at the medium and low frequency generated after the compensation circuit is introduced are considered. As shown in FIG. 4, the 0-dB bandwidth and phase margin are improved after the compensation circuit is added.

(19) FIG. 5 shows the ac response curves of light load 100 uA with solid line and heavy load 100 mA with dashed line, respectively. The loop gains are 78.8 dB and 44.5 dB, respectively. The 0 dB bandwidths are 1.81 MHz and 500 kHz respectively. The phase margins are 48.2 and 97.7 respectively. The LDO provided by the present invention has a good loop stability under the light load. The loop gain bandwidth product GBW and the gain are both decreased under the heavy load since the power transistor enters the linear region.

(20) FIG. 6 shows the transient response curve of the LDO provided by the present invention, the load is switched between 100 uA and 100 mA within 0.5 us. The undershoot of the structure provided by the present invention is within 330 mV, thereby achieving a fast transient response.

(21) Various specific variations and combinations can be derived by those of ordinary skill in the art according to the teachings of the present disclosure without departing from the essence of the present invention. These variations and combinations, however, should still be considered as falling within the scope of the present invention.