Wideband receiver architecture tolerant to in-band interference

Abstract

A wideband receiver circuit is disclosed that includes a signal input configured to receive a spectrum signal of bandwidth B that contains an RF signal and an interference signal. A down conversion module is connected to the signal input and has N down conversion channels, wherein each of the N down conversion channels is configured to down convert the spectrum signal to one of N decimated baseband signals by processing the spectrum signal with one distinct phase of a sequence of length N and period N/fclk=N/2B to generate a baseband output signal. An amplifier circuit is connected to each of the N down conversion channels, and is configured to amplify the baseband output signal. A digital signal processing module including an analog to digital conversion circuit is connected to each amplifier circuit and is configured to convert the amplified baseband output signal to N digital signals. The digital signal processing module also having a digital reconstruction processor to combine each of the N digital signals and generate a reconstructed RF signal.

Claims

1. A wideband receiver circuit comprising: a signal input configured to receive a spectrum signal of bandwidth B that contains an RF signal and an interference signal; a down conversion module connected to the signal input and having N down conversion channels, wherein each of the N down conversion channels is configured to down convert the spectrum signal to one of N decimated baseband signals by processing the spectrum signal with one distinct phase of a sequence of length N and period N/f.sub.clk=N/2B to generate a baseband output signal, wherein f.sub.clk is a clock period for the wideband receiver circuit; an amplifier circuit connected to each of the N down conversion channels, wherein the amplifier circuit is configured to amplify the baseband output signal; and a digital signal processing module having an analog to digital conversion circuit connected to each amplifier circuit and configured to convert the amplified baseband output signal to N digital signals, and a digital reconstruction processor to combine each of the N digital signals and generate a reconstructed RF signal.

2. The wideband receiver circuit of claim 1, wherein each of the N down conversion channels includes a mixer circuit, wherein each mixer circuit is configured to process the spectrum signal with a local oscillator signal and generate a baseband signal, and wherein the local oscillator signal is one distinct phase of the sequence of length N and period N/f.sub.clk=N/2B.

3. The wideband receiver circuit of claim 2, wherein each of the N down conversion channels includes an integration circuit, and wherein each integration circuit receives the baseband signal from the mixer circuit and further processes the baseband signal by performing an averaging function over a sequence period, T.sub.s=N/2B, and then sampling the baseband signal at the end of each sequence period to generate a sampled baseband output signal.

4. The wideband receiver circuit of claim 3, wherein the integration circuit is a switched capacitor circuit that performs the averaging function.

5. The wideband receiver circuit of claim 1, wherein the sequence is a 2.sup.N1 pseudo-random bit sequence (PRBS).

6. The wideband receiver circuit of claim 1, wherein signal swings of the baseband output signal have been suppressed.

7. The wideband receiver circuit of claim 1, wherein the down conversion module further comprises a discrete-time signal processing module.

8. A wideband receiver circuit comprising: a signal input configured to receive a spectrum signal of bandwidth B that contains one or more desired RF signal components and undesired noise and/or interference components, wherein the undesired components may be stronger than the RF signal components; a down conversion module connected to the signal input and having N down conversion channels, wherein each of the N down conversion channels is configured to down convert the spectrum signal to one of N decimated baseband signals, wherein each of the N down conversion channels includes a mixer circuit configured to process the spectrum signal with a local oscillator signal and generate a baseband signal, wherein the local oscillator signal is one distinct phase of a sequence of length N and period N/f.sub.clk=N/2B and wherein f.sub.clk is a clock period for the wideband receiver circuit, wherein each of the N down conversion channels further includes an integration circuit, wherein each integration circuit receives the baseband signal from the mixer circuit and further processes the baseband signal by performing an averaging function over a sequence period, T.sub.s=N/2B, and then sampling the baseband signal at the end of each sequence period to generate a sampled baseband output signal; a baseband amplifier circuit connected to each of the N down conversion channels wherein the baseband amplifier is configured to amplify the sampled baseband output signal from the integration circuit; and a digital signal processing module having an analog to digital conversion circuit connected to each baseband amplifier circuit and configured to convert the amplified baseband output signal to N digital signals, and a digital reconstruction processor to combine each of the N digital signals and generate a reconstructed RF signal.

9. The wideband receiver circuit of claim 8, wherein the integration circuit is a switched capacitor circuit that performs the averaging function.

10. The wideband receiver circuit of claim 8, wherein the sequence is a 2.sup.N1 pseudo-random bit sequence (PRBS).

11. The wideband receiver circuit of claim 8, wherein signal swings of the sampled baseband output signal have been suppressed.

12. The wideband receiver circuit of claim 8, wherein the down conversion module further comprises a discrete-time signal processing module.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A illustrates a schematic diagram of the architecture for the wideband circuit.

(2) FIGS. 1B-1D illustrate example waveforms at different points of the wideband receiver circuit.

(3) FIGS. 2A-B illustrate a circuit and timing diagram used for analysis of equivalent input impedance.

(4) FIGS. 3A-D illustrate a baseline block diagram of the wideband receiver circuit and system level simulation results.

(5) FIGS. 4A-4B illustrate a schematic diagram of the N-channel signal processing circuit shown with a timing diagram for the switched capacitor averaging circuit.

(6) FIGS. 4C-4F illustrate graphs of time domain and frequency domain signals processed by the wideband receiver circuit.

DETAILED DESCRIPTION

(7) A new wideband receiver architecture is described that is able to achieve high dynamic range while covering a large instantaneous bandwidth. FIG. 1A shows the basic architecture of the wideband receiver circuit 100 that includes an N-channel signal processor. In one exemplary implementation, the N-channel signal processor is an N-channel discrete-time switched-capacitor (DTSC) signal processor 110. However, it should be understood that the invention is not limited to a DTSC signal processor, and that the wideband receiver may be implemented with other types of signal processing circuits such as a continuous time integrator circuit. The N-channel DTSC signal processor 110 is connected to a baseband amplifier block 120 having N amplifiers 122, and then a digital signal processor block 130 having N analog to digital converter (ADC) circuits 132. Once the sampled signal is in the digital domain, a recovery procedure requiring minimal digital resources is employed within a digital signal reconstruction processor 134 to reconstruct the full bandwidth input signal. Each of the N channels in the DTSC signal processor 110 includes a mixer circuit 112, an integrator circuit 114, and a sample and hold circuit 116. The output from the sample and hold circuit 116 is provided at node 118 which is also connected to the input of a corresponding amplifier 122 within the amplifier block 120. The output from each of the N amplifiers 122 is provided at node 124 which is also connected to the input of a corresponding analog to digital converter (ADC) circuit 132 within the digital signal processor block 130.

(8) For simplicity of explanation purposes, and without limiting the scope of the invention, N is chosen to be 15, and each of the blocks 110, 120, 130 of the wideband receiver circuit 100 will be described as having N=15 channels. It should be understood that the wideband receiver circuit 100 may have more or less channels, for example, N=7, N=15, N=31. Thus, the DTSC signal processor 110, the baseband amplifier block 120, and the digital signal processing block 130 are also understood to include fifteen channels based on the selection of N=15 for explanation purposes. Each channel within the DTSC signal processor 110 also includes its own local oscillator generator circuit (not specifically shown) that provides a local oscillator signal to the corresponding mixer circuit 112. One exemplary implementation of a local oscillator generator employs an N-bit circular shift register. This approach has the advantage of minimizing the effects of timing skew and mismatch.

(9) With reference to FIG. 1A, as a high level operation, the N channel DTSC signal processor 110 projects N distinct sequences onto the RF input signal and provides an integrated output (118) every N clock cycles. Prior to amplification, the RF input signal (FIG. 1B) passes through the DTSC signal processor 110. The RF input signal is first mixed with a set of N different phases of an N bit psuedo-random bit sequence (PRBS) by the corresponding mixer circuits 112. The bit sequence provided as the local oscillator signal to the mixer circuit 112 is generated by a shift register based PRBS generator (not specifically shown) that may be built into the CMOS architecture of the receiver chip. The output of each mixer circuit 112 is then averaged by the integrator circuit 114 over the sequence period, T.sub.s=NT.sub.s, and the output of each integrator circuit 114 is sampled at the end of each sequence period (FIG. 1C) by the sample and hold circuit 116. Thus, at any given time, the output of each sample and hold circuit 116 is the inner product of the RF input signal and the corresponding normalized PRBS, p.sub.i/N, over the preceding sequence period. The sampled outputs are then amplified by the amplifier 122 and digitized by the ADC 132 at a rate of f.sub.s/N. Finally, a discretized version of the RF input signal is reconstructed from the N digitized baseband signals (FIG. 1D) within the digital signal reconstruction processor 134.

(10) To further understand the operating principles of the wideband receiver circuit 100, consider a single sequence period from t=0 to t=T.sub.s. Assuming an input signal that is band-limited to f.sub.s/2, the sampled voltages may be related to the input signal as
y=Px,(1)
where y is a vector containing the N sampled voltages, x is a vector of length N containing time domain values of the input signal, sampled at 1/f.sub.s, and P is an NN matrix, in which row j contains switching sequence p.sub.j, normalized to its length. It is apparent the vector x may be determined from y, since P (the NN matrix) is invertible. It should also be pointed out that, since P is a deterministic matrix, once it is known, the inverse of this matrix yields a simple mapping through linear superposition from the measured baseband vectors (y) back to the full-rate input signal (x).

(11) FIGS. 1B-1D show example waveforms at different points of the wideband receiver circuit 100. The voltage signal swings are greatly suppressed prior to analog amplification in such a way that the signal can be recovered in the digital domain. More specifically, FIG. 1B shows an example of a RF input signal waveform x(t) provided as an input to the N channel DTSC signal processor 110. FIG. 1C shows all fifteen of the baseband waveforms y[i] (where i=1 to 15) superimposed on one graph where each waveform represents the output of one of the N=15 channels of the DTSC signal processor 110 at node 118. FIG. 1D shows the reconstructed waveform x[n] as the output from the digital signal reconstruction processor 134. A comparison of FIG. 1D with FIG. 1B illustrates that the reconstructed waveform x[n] (136) generated by the digital signal reconstruction processor 134 matches the RF input signal waveform x(t) provided as input to the DTSC signal processor 110.

(12) One function of the N-channel DTSC signal processor 110 is to reduce signal swings and decimate the bandwidth of the RF input signal by a factor of N prior to amplification. Since the linearity of active circuits is ultimately limited by voltage swings, this smoothing of the signal swings greatly reduces the signal handling requirements of the subsequent active electronics. Moreover, since the DTSC signal processor 110 also serves to decimate the bandwidth by a factor of N, baseband design techniques can be used for the active circuitry, thus making it possible to implement amplification blocks, such as baseband amplifier block 120, that achieve low-noise and high linearity simultaneously.

(13) The N-channel DTSC signal processor 110 is low-loss, and is able to suppress signal swings and arbitrary frequency components while enabling efficient and complete signal recovery. In one implementation, a 15-channel DTSC signal processor 110 based upon an orthogonal pseudo-random basis set is demonstrated. For the purpose of this disclosure, circuits covering the DC-1 GHz frequency range using a mature CMOS circuit components and processes were designed. However, it should be noted that the general techniques are scalable to larger instantaneous bandwidths and can also be applied to bandpass systems.

(14) As a basic demonstration of the topology described herein, a wideband receiver circuit 100 based upon DTSC signal processor 110 is implemented that projects a broadband RF input signal onto N pseudo-random bit sequences (PRBS), thereby reducing the peak signal swings by approximately sqrt(N) prior to amplification. With reference to FIG. 1A, p.sub.1(t) to p.sub.N(t) shown as input signals to each mixer circuit 112 are the N different phases of the N-bit PRBS. It should also be noted that for discussion purposes it is assumed that the RF input signal is uncorrelated with the PRBS signals. Mathematically, the effect of the PRBS-based DTSC pre-processor for the case of N=15 can be described through the matrix relationship

(15) $\begin{array}{cc}y=\frac{1}{15}\underset{\underset{P}{}}{\left[\begin{array}{ccccccccccccccc}1& 1& 1& 1& -1& -1& -1& 1& -1& -1& 1& 1& -1& 1& -1\\ -1& 1& 1& 1& 1& -1& -1& -1& 1& -1& -1& 1& 1& -1& 1\\ 1& -1& 1& 1& 1& 1& -1& -1& -1& 1& -1& -1& 1& 1& -1\\ -1& 1& -1& 1& 1& 1& 1& -1& -1& -1& 1& -1& -1& 1& 1\\ 1& -1& 1& -1& 1& 1& 1& 1& -1& -1& -1& 1& -1& -1& 1\\ & & & & & & & \mathrm{.Math.}& & & & & & & \\ 1& 1& 1& -1& -1& -1& 1& -1& -1& 1& 1& -1& 1& -1& 1\end{array}\right]}x,& \left(1\right)\end{array}$
where P is a matrix containing the N PRBS signals, x is a vector of time-domain samples, and y is a vector containing the N decimated output samples. Since the matrix P is invertible, the discrete time-domain signal x can be reconstructed at full bandwidth in the digital domain from the amplified and digitized version of y.

(16) An analysis of the key performance metrics of the wideband receiver circuit 100 is described below. The overall equivalent noise of the system may be determined by input referring the independent noise contribution from each of the chains to the input of the wideband receiver 100. Assuming the total noise of each baseband chain at the input 118 of the baseband amplifier 122 to be band-limited to f.sub.s/N, have a normal distribution with zero mean and a standard deviation of .sub.N the effect of matrix multiplication can be analyzed. It can be shown that the power spectral density (PSD) of p^.sub.j in the digital signal reconstruction processor 134 can be written as,

(17) $\begin{array}{cc}{S}_{\hat{p}}=\left(f\right)+\underset{k=1}{\overset{\left(N-1\right)/2}{.Math.}}\frac{1}{N+1}\left(fk\frac{f_S}{N}\right).& \left(10\right)\end{array}$
Each channel in the digital signal reconstruction processor 134 may use a zero-order hold (ZOH) block that upconverts the noise of each baseband output and modulates it with a sinc.sup.2 function. By convolving this noise at the output of each ZOH block with the PSD in eq. (10) the effect of each individual channel at the output is found. The total voltage noise spectrum at the output after reconstruction is N times that of each individual channel and can be written as,

(18) $\begin{array}{cc}{S}_N=N{}_N^2\left[\sin c^2\left({\mathrm{fNT}}_s\right)+\underset{k=1}{\overset{\left(N-1\right)/2}{.Math.}}\frac{\sin c^2\left(\left(f{\mathrm{kf}}_s\right){\mathrm{NT}}_s\right)}{N+1}\right]& \left(11\right)\end{array}$
Eq. (11) shows that the output noise will have N+1 times higher noise at DC. However over the frequency band from f.sub.s/N to f.sub.s/2 output voltage noise spectral density is close to the baseband noise level of each channel.

(19) The overall noise figure of the system can be derived in terms of W.sub.0 (V/sqrt (Hz) which is the voltage noise spectrum density of each channel referred to the input 118 of the baseband amplifier 122. Using results from eq. (11) and assuming the wideband receiver 100 operates in the frequency range between f.sub.s/N and (N+1)f.sub.s/N the noise figure can be written as

(20) $\begin{array}{cc}\mathrm{NF}10{\log }_{10}\left(1+\frac{1-}{}\frac{T_a}{T_0}+\frac{W_0^2}{{\mathrm{kT}}_0{R}_S}\right),& \left(12\right)\end{array}$
where is the loss factor in the sampling circuit, k is the Boltzmann constant, T.sub.0=290 K is the reference temperature, T.sub.a is the physical temperature, and R.sub.s is the generator impedance.

(21) Linearity: As discussed above, the spreading and integration operations have the effect of reducing signal swings by a factor of N, where N is the length of the spreading sequence. Therefore, the linearity can be improved by a factor of 10 log 10 {N} from that of each baseband amplifier. Assuming a base-band gain of 20 dB, and an output swing of 3 V.sub.pk-pk differential from each amplifier 5 at the 1 dB compression point, then the input-referred third-order intermodulation intercept of each amplifier is approximately 470 mV peak differential, or 0 dBm referred to 100. Thus, the in-band I IP3 of the system in this case would be 11.7 dBm. It should be noted that the output swing of 3 V.sub.pk-pk differential from each amplifier was selected to ensure linearity is maintained when driving a typical ADC chip.

(22) Impedance Match: The analysis of impedance in switched capacitor circuits is generally well known. The input impedance to the DTSC signal processors 110 described herein can be determined by analyzing the circuit of FIG. 2A and also the circuit of FIG. 4A. FIG. 2B shows a timing diagram associated with FIG. 2A. It can be shown that, for frequencies well below the clock frequency, R.sub.IN is approximately given as R.sub.INR.sub.GEN [1/f.sub.clk R.sub.GENC (1exp {T.sub.SAMP/T})1], where f.sub.clk is the clock period, R.sub.GEN is the generator resistance, =(R.sub.SW+R.sub.GEN) C, R.sub.SW is the switch on-resistance, and T.sub.SAMP is the sampling pulse width. Thus, at low frequencies, the input impedance is weakly dependent upon the switch resistance and can be set by the total sampling capacitance C. At higher frequencies the analysis becomes a bit more complicated as a reactive component appears in the input impedance. However, based upon realistic periodic steady-state simulations carried out in a design environment such as the Cadence Virtuoso design environment, it appears realistic to achieve better than 15 dB return loss from DC-1 GHz using a simple L-C matching network.

(23) Harmonic and Local Oscillator Re-radiation: A concern when connecting a switched-capacitor circuit to an antenna is harmonic and local oscillator re-radiation. In the context of the wideband receiver circuit 100, reflected power can also lead to coupling between the channels. To prevent channel-channel coupling, switched capacitor circuits of the form shown in FIG. 2A are implemented, where all sampling capacitors are discharged before the relevant sampling switch is enabled. Simulations indicate that harmonic or local oscillator re-radiation is not expected to be a problem for the case when the fundamental frequency is impedance matched.

(24) Matlab System Simulations: A numerical simulation of the wide band receiver circuit 100 was carried out in Matlab and the performance was compared to that of a typical amplifier-first approach. Block diagrams of the simulated reference and orthogonal projection based receiver configurations appear in FIGS. 3A and 3B. A 60 dBm QAM-64 signal with a carrier frequency of 200 MHz was combined with a 7 dBm CW signal at 402 MHz to create the input stimulus. The symbol rate for the QAM 64 signal was 13.3 Msymbols/second, corresponding to an overall data rate of 80 Mbps. Both phase and thermal noise were incorporated into the simulation, with the phase noise spectrum corresponding to a 200 MHz crystal oscillator that has been frequency multiplied to f.sub.clk=2 GHz. The amplifier non-linearity was modelled as a simple third-order non-linearity corresponding to an input-referred 1 dB compression point of 13 dBm in a 100 system (100 mV peak differential). The same non-linearity was employed in both the baseband amplifiers and the reference path. The simulation was carried out for 60 s and the constellation was recovered for each case. FIG. 3D shows the output constellation for the demodulated QAM signals corresponding to a baseline system (cluster 340) and the wideband receiver circuit 100 (constellation 350). For the amplifier-first approach (tight cluster of blue symbols) 340, the amplifier non-linearity due to the 7 dBm blocker signal renders the constellation distorted to the extent that the data cannot be recovered. However, when employing the approach implemented by the wideband receiver circuit 100 described herein, the constellation (evenly spaced constellation of red symbols) 350 remains clean despite the presence of the large blocking signal.

(25) Cadence Transistor Level Simulations: Using a 130 nm CMOS PDK, a preliminary transistor-level simulation of one implementation of the passive front-end pre-processor, such as DTSC signal processor 110, was carried out to demonstrate the feasibility of the wideband receiver design. FIG. 4A shows the simulated hardware configuration for the DTSC signal processor 410. Fifteen channels were operated in parallel, with the mixer circuit 412 of each channel driven by its own 15-bit PRBS signal. Generation of the local oscillator PRBS signals was accomplished using a single 15-bit shift register implemented using CMOS logic. The clocking frequency was set to 1 GHz, corresponding to a 0-0.5 GHz acquisition bandwidth. Integration of the output of each mixer circuit 412 was implemented using a pair of switched-capacitor FIR averaging circuits 413, with one of the two circuits sampling at all times (see the timing diagram in FIG. 4B). .sub.A and .sub.B switch between integration channels to permit continuous sampling of the modulated RF input. The two circuits are operated in parallel such that one capacitor is always sampling. A fully differential configuration was employed to minimize the effect of charge injection.

(26) In one experiment, the circuit was driven by a closely spaced pair of 200 mV peak-differential signals at f.sub.clk30/90 and f.sub.clk31/90, respectively. These frequencies were selected to fall into unique and adjacent frequency bins when taking an FFT over 90 ns worth of data (i.e., 90 samples). Using Cadence Virtuoso, a transient simulation of 100 ns duration was carried out and the results were sent to Matlab for further processing. The RF input appears in FIG. 4C along with each of the fifteen sampled differential outputs, v.sub.out (1:15). The projection of the fifteen PRBS sequences on the time domain data along with the integration operation results in suppression of the peak voltage swings by a factor of 15, thereby easing the linearity requirement on subsequent active electronics. Output vectors of length fifteencorresponding to the y vectors in FIG. 1Awere generated by sampling the differential outputs shown in FIG. 4C at f.sub.clk/15. For each y vector, reconstruction of the full Nyquist data rate was accomplished through multiplication of y by the inverse PRBS matrix. With no hardware optimization, this transform requires fifteen eight-input addition operations, and is suitable for implementation in digital hardware. The FFT spectrum of the 90 ns reconstruction appears in FIG. 4D which shows the spectrum of the recovered two-tone signal. The dynamic range of the reconstructed signal is approximately 50 dB, which is limited by charge injection in the un-optimized switched capacitor circuit as well as inter-channel coupling related to stray capacitance between the mixers and the sampling capacitors.

(27) In another experiment, the circuit was stimulated with a 44-tone excitation, such that for a 90 ns simulation interval, all but one available frequency was occupied. The magnitude of every fifth tone was set to half of that of the other tones and each tone had an initial phase of 0 (zero) degrees. The resulting waveform is the dispersed wide-band pulse shown in FIG. 4E which shows the input (blue dashed lines 415) and reconstruction (red dotted lines 417) signals for the 44-tone simulation. Again, the data were ported to Matlab, sampled, and multiplied by the inverse PRBS matrix to generate the reconstructed signal. The time and frequency domain results appear in FIGS. 4E and 4F, respectively. The results of this wideband simulation demonstrate excellent agreement between input and recovered signals in both the time and frequency domains. With reference to FIG. 4E, the reconstructed signal represented by the dotted lines 417 closely matches the waveform of the RF input signal represented by dashed lines 415.

(28) Mismatch: Systematic errors will result from unavoidable random mismatch such as the effective weighting of each sampling capacitor and DC offset/gain errors in each baseband amplifier 122. Taking these errors into account, the vector of voltage amplitudes at the output of the baseband amplifiers 122 can be written as y=gBB (AEx+o), where E is a matrix describing mismatch and o is a vector of DC offsets. For the proposed system to work, it is critical that E and o are systematically determined. This can be accomplished through a calibration procedure in which the system is excited by an attenuated version of each phase of the PRBS and its complement. Defining, YA=gBB (AEA+diag (o) U) and YB=gBB (AEAdiag (o) U), where U is a matrix with each element equal to unity, the product of the ideal baseband gain and the DC offset vector is given as gBBdiag (o) U=(YA+YB)/2, whereas the normalized error matrix is given as E=A1 (YA/2YB/2) A1. Such a calibration scheme can be carried out with low overhead.

(29) Clock and RF Skew: A related problem is relative skew between the clock signals around the chip, resulting in a distribution of sampling times. Ultimately, such deterministic jitter will limit the dynamic range as the noise floor will increase in the presence of large signals. To minimize this effect, h-tree distribution networks or other delay matching approaches can be employed for both the RF and the clock.

(30) From a review of this disclosure, it might appear that the system architecture of the wideband receiver circuit 100 described herein is essentially a code-division multiple-access (CDMA) system. In particular, on a given branch, the received signal is multiplied by a wideband sequence, hence spreading the interferer, and then integrated. There have been numerous variants of CDMA systems considered over the last twenty years, ranging from standard CDMA systems to those that spread in the frequency domain, and various combinations. Some of these employ multi-code approaches, which have multiple de-spreading arms for a given user. However, the system architecture of the wideband receiver circuit 100 described herein is vastly different. First, from a systems perspective, CDMA receivers are paired with a very specific transmission technique, rather than providing full-band recovery of any wideband signal. To make this contrast stark, the wideband receiver circuit 100 can be employed in applications such as radio astronomy in the presence of strong adjacent band interferers, whereas CDMA receivers could not. Because of this difference in application, the key challenges in sequence and circuit design, in particular the co-design of effective filtering sequences that support full-band recovery and matched circuit architectures, are absent from the CDMA literature. The circuit architecture of the wideband receiver circuit 100 is also quite different than that generally employed for CDMA. Upon reception, a CDMA signal is generally filtered, amplified, downconverted, digitized, despread and detected, because CDMA is narrowband relative to the solution implemented by the wideband receiver circuit 100. The despreading in the disclosed wideband receiver 100 spreads a narrowband blocker, and this helps reduce dynamic range; however, despreading typically happens after downconversion and usually after digitization. Thus, RF amplification is necessary, and unless pre-filtering occurs, blockers can interact with the nonlinearities in the amplifier/downconverter to increase in-band interference. In current multiband commercial receivers, pre-filtering involves tens of filters and a complex switching system, increasing the noise and complexity of the system.

(31) Compressive Sampling RF Receivers: An expert in the area in RF circuits may also note a resemblance between the architecture of the wideband receiver circuit 100 other known compressive sampling RF receiver architectures. However, such compressive sampling architectures suffer from two key limitations. Firstly, since compression is obtained by under-sampling, noise folding causes the signal-to-noise of such systems to be inherently worse than what can be achieved using a more standard architecture. Secondly, reconstruction of the RF signal requires the minimization of an I.sub.1 norm, which is hardware intensive. Finally, an underlying assumption of signal sparsity (usually in the spectral domain) is required. On the contrary, the disclosed wideband receiver circuit 100 does not exploit sub-sampling and is therefore not subject to noise folding effects, and signal reconstruction can be accomplished for arbitrary (e.g., non-sparse) signals through a linear superposition operation, which is easily implemented in hardware.

(32) The topology for the wideband receiver circuit 100 shown in FIG. 1A can be thought of as a bank of N sequence-defined FIR filters, each followed by a 1/N sampling-rate decimation. The sequences defining the effective FIR filter tap weights, pn, are selected to be delayed pseudo-random bit sequences. As such sequences are white in the frequency domain, the equivalent FIR filters will have all-pass characteristics within the Nyquist bandwidth and each frequency component folds to baseband during the decimation process. Since each of the N sequences is sampling a different aspect of the wideband RF input, the information contained in the decimated outputs of the N channels is sufficient to recover the full Nyquist-bandwidth input signal.

(33) Although a few implementations have been described in detail above, other modifications are possible. For example, the signal processing block could be implemented with continuous time integrators rather than a switched capacitor circuit. In other alternate implementations a different basis set may be used (e.g., Hadamard Sequences or Gold Codes) in place of pseudo random bit sequences. Accordingly, other implementations are within the scope of the following claims.