Power MOSFETs with superior high frequency figure-of-merit

Abstract

An insulated-gate field effect transistor includes a substrate having a drift region and a source region of first conductivity type, and a base region and shielding region of second conductivity type therein. The base region forms a first P-N junction with the source region and the shielding region extends between the drift region and the base region. A transition region of first conductivity type is provided, which is electrically coupled to the drift region. The transition region extends between a first surface of the substrate and the shielding region, and forms a second P-N junction with the base region. An insulated gate electrode is provided on a first surface of the substrate. The insulated gate electrode has an electrically conductive gate therein with a drain-side sidewall extending intermediate the second P-N junction and an end of the shielding region when viewed in transverse cross-section.

Claims

1. An insulated-gate field effect transistor, comprising: a substrate having a semiconductor drift region of first conductivity type therein; a semiconductor source region of first conductivity type in said substrate; a semiconductor base region of second conductivity type in said substrate, said base region forming a first P-N junction with said source region; a semiconductor shielding region of second conductivity type in said substrate, said shielding region extending between said drift region and said base region; a semiconductor transition region of first conductivity type electrically coupled to said drift region, said transition region extending between a first surface of said substrate and said shielding region and forming a second P-N junction with said base region; and an insulated gate electrode on the first surface of said substrate, said insulated gate electrode having an electrically conductive gate therein with a drain-side sidewall extending intermediate the second P-N junction and an end of said shielding region when viewed in transverse cross-section.

2. The transistor of claim 1, further comprising a JFET region of first conductivity type extending between said drift region and the first surface.

3. The transistor of claim 2, wherein said transition region forms a non-rectifying semiconductor junction with a first portion of said JFET region; and wherein a net first conductivity type doping concentration in said transition region is greater than a net first conductivity type doping concentration in the first portion of said JFET region.

4. The transistor of claim 3, wherein the first portion of said JFET region extends to the first surface; and wherein the non-rectifying semiconductor junction between said transition region and the first portion of said JFET region extends to the first surface.

5. The transistor of claim 4, wherein said transition region extends between said shielding region and the first surface, but the first portion of said JFET region does not.

6. The transistor of claim 5, wherein said JFET region forms a fourth P-N junction with said shielding region; and wherein said transition region extends between the fourth P-N junction and the first surface.

7. The transistor of claim 1, wherein the net first conductivity type doping concentration in a first portion of said transition region extending between the first surface and said shielding region is sufficiently high to prevent full depletion of the first portion of said transition region when the transistor is turned-off.

8. The transistor of claim 7, wherein the first portion of said transition region forms a third P-N junction with said shielding region; and wherein a thickness (t.sub.T) of the first portion of said transition region, as measured between the first surface and said shielding region is greater than 0.75(2V.sub.bi.sub.s/qN.sub.T).sup.1/2, where V.sub.bi is the built-in potential of the third P-N junction, .sub.s is the dielectric constant of said transition region, q is the electron charge and N.sub.T is the net first conductivity type doping concentration in said transition region.

9. The transistor of claim 8, wherein t.sub.T is less than E.sub.c.sub.s/qN.sub.T, where E.sub.c is the critical electric field for breakdown in said transition region.

10. The transistor of claim 1, further comprising a source electrode extension disposed adjacent a drain-side end of the gate and opposite said transition region; and a source electrode electrically coupled to said source region and the source electrode extension.

11. The transistor of claim 10, wherein the source electrode extension and the gate comprise the same material.

12. The transistor of claim 11, wherein a separation distance between the gate and the base region is equivalent to a separation distance between the source electrode extension and said transition region.

13. The transistor of claim 12, wherein a portion of the source electrode extension extends opposite an end of said shielding region.

14. The transistor of claim 10, wherein a portion of the source electrode extension extends opposite an end of said shielding region.

15. The transistor of claim 1, wherein the drain-side sidewall of said insulated gate electrode extends intermediate the second P-N junction and an end of said shielding region when: (i) the drain-side sidewall, (ii) the second P-N junction, and (iii) the end of said shielding region are viewed in transverse cross-section and their lateral dimensions are compared on a common lateral scale extending parallel to the first surface of said substrate.

16. An insulated-gate field effect transistor, comprising: a substrate having a semiconductor drift region of first conductivity type therein; a semiconductor source region of first conductivity type in said substrate; a semiconductor base region of second conductivity type in said substrate, said base region forming a first P-N junction with said source region; a semiconductor shielding region of second conductivity type in said substrate, said shielding region extending between said drift region and said base region; a semiconductor transition region of first conductivity type electrically coupled to said drift region, said transition region extending between a first surface of said substrate and said shielding region and forming a second P-N junction with said base region; and an insulated gate electrode on the first surface of said substrate, said insulated gate electrode having an electrically conductive gate therein with a drain-side sidewall extending closer to the second P-N junction relative to a laterally extending distal end of said shielding region, when viewed in transverse cross-section.

17. The transistor of claim 16, further comprising a JFET region of first conductivity type extending between said drift region and the first surface.

18. The transistor of claim 17, wherein said transition region forms a non-rectifying semiconductor junction with a first portion of said JFET region; and wherein a net first conductivity type doping concentration in said transition region is greater than a net first conductivity type doping concentration in the first portion of said JFET region.

19. The transistor of claim 18, wherein the net first conductivity type doping concentration in a first portion of said transition region extending between the first surface and said shielding region is sufficiently high to prevent full depletion of the first portion of said transition region when the transistor is turned-off.

20. The transistor of claim 19, wherein the first portion of said transition region forms a third P-N junction with said shielding region; and wherein a thickness (t.sub.T) of the first portion of said transition region, as measured between the first surface and said shielding region is greater than about 0.75(2V.sub.bi.sub.s/qN.sub.T).sup.1/2, where V.sub.bi is the built-in potential of the third P-N junction, .sub.s is the dielectric constant of said transition region, q is the electron charge and N.sub.T is the net first conductivity type doping concentration in said transition region.

21. The transistor of claim 20, wherein t.sub.T is less than E.sub.c.sub.s/qN.sub.T, where E.sub.c is the critical electric field for breakdown in said transition region.

22. The transistor of claim 16, wherein the drain-side sidewall of said insulated gate electrode extends closer to the second P-N junction in a lateral dimension relative to a laterally extending distal end of said shielding region, when viewed in transverse cross-section and when the lateral dimensions of: (i) the drain-side sidewall, (ii) the second P-N junction, and (iii) the distal end of said shielding region are compared on a common lateral scale extending parallel to the first surface of said substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a cross-sectional view of an insulated-gate field effect transistor (e.g., half-cell) according to the prior art.

(2) FIG. 2A is a cross-sectional view of an insulated-gate field effect transistor (e.g., half-cell) according to an embodiment of the invention.

(3) FIG. 2B is a cross-sectional view of an insulated-gate field effect transistor (e.g., half-cell) according to an embodiment of the invention.

(4) FIG. 2C is a cross-sectional view of an insulated-gate field effect transistor (e.g., half-cell) according to an embodiment of the invention.

(5) FIGS. 3A-3E are cross-sectional views of intermediate structures that illustrate methods of forming insulated-gate field effect transistors according to the prior art (left side) and according to embodiments of the invention (right side).

(6) FIG. 4 includes cross-sectional views of insulated-gate field effect transistors (e.g., half-cells) according to the prior art (left, middle) and according to embodiments of the invention (right).

(7) FIG. 5 is a graph illustrating a range of acceptable transition region thicknesses versus transition region doping for SiC and GaN insulated-gate field effect transistors according to embodiments of the invention.

(8) FIG. 6A is a cross-sectional view of an insulated-gate field effect transistor (e.g., half-cell) according to an embodiment of the invention.

(9) FIG. 6B is a graph of simulated breakdown voltage versus gate width extension (X) for the device of FIG. 6A.

(10) FIG. 6C is a graph of specific Qgd versus gate width extension (X) for the device of FIG. 6A.

(11) FIG. 6D is a graph of specific Cgd versus gate width extension (X) for the device of FIG. 6A.

(12) FIG. 6E is a graph of specific on-state resistance (Ron) versus gate width extension (X) for the device of FIG. 6A.

(13) FIG. 6F is a graph of figure-of-merit (RxC) versus gate width extension (X) for the device of FIG. 6A.

(14) FIG. 6G is a graph of figure-of-merit (RxQ) versus gate width extension (X) for the device of FIG. 6A.

DETAILED DESCRIPTION OF EMBODIMENTS

(15) The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

(16) It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

(17) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms a, an and the are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprising, including, having and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. In contrast, the term consisting of when used in this specification, specifies the stated features, steps, operations, elements, and/or components, and precludes additional features, steps, operations, elements and/or components.

(18) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(19) Referring now to FIG. 1, a silicon carbide (SiC) power MOSFET 10 according to the prior art is illustrated as including a semiconductor substrate 15 (e.g., SiC) having a substrate region 2 of first conductivity type (e.g., N-type) therein. This substrate region 2 (N+ substrate) is shown as a relatively highly doped region that may be derived from a relatively highly doped SiC material (e.g., SiC wafer/chip, SiC epitaxial layer). The semiconductor substrate 15 includes a relatively lightly doped N-type drift region 3 (N-Drift) that extends between the substrate region 2 and a first/primary surface 13 of the substrate 15, which has a source electrode 6 (Source) and a relatively wide and large area gate electrode 4 (Gate) thereon. This gate electrode 4 is insulated from surrounding regions by an electrically insulating region 5 (e.g., silicon dioxide).

(20) A relatively highly doped shielding region 7 of second conductivity type (e.g., P-type) is provided in the drift region 3. This shielding region 7 is electrically coupled to the source electrode 6 by a contact region 11 of second conductivity type, which extends between the shielding region 7 and the first surface 13 of the substrate 15, as shown. The shielding region 7 and the contact region 11 are both shown as relatively highly doped P+ regions. A source region 9 of first conductivity type (N+ Source), which forms an ohmic contact with the source electrode 6, and a base region 8 of second conductivity type (P-base) are provided in the substrate 15. As shown, the N-type source region 9 and the P-type base region 8 extend between the shielding region 7 and the first surface 13 of the substrate 15. Furthermore, the P-type base region 8 and the P-type shielding region 7 are shown as having the same lateral extent in the drift region 3, when the MOSFET 10 is viewed in transverse cross-section, as shown.

(21) As will be understood by those skilled in the art, the application of a sufficiently positive bias to the gate electrode 4 will turn-on the MOSFET 10 by inducing the formation of an N-type inversion layer channel in the P-type base region 8. This inversion layer channel, which forms adjacent the first surface 13 of the substrate 15, operates to electrically connect the source region 9 to the N-type drift region 3 so that forward on-state current may flow (laterally and vertically) between the source electrode 6 and drain electrode 1 of the MOSFET 10. In particular, during forward on-state conduction, majority carriers (i.e., electrons) may be provided laterally from the source region 9 to a neck region (a/k/a JFET region) within the drift region 3 and then vertically downward across the voltage-supporting drift region 3 to the substrate region 2 and drain electrode 1, which is provided on a second surface 12 of the substrate 15.

(22) The lateral extent of the JFET neck region may be defined as the lateral width of the upper drift region 3, as measured between two adjacent P-type shielding regions 7. One of these P-type shielding regions 7 is illustrated by the half-cell MOSFET configuration of FIG. 1, which typically includes another mirror-image half-cell MOSFET that is responsive to the same gate electrode 4. Moreover, because of the gate electrode 4 is relatively wide and extends opposite the JFET neck region, the application of a sufficiently positive bias to the gate electrode 4 will operate to modulate (i.e., enhance) the conductivity of the JFET neck region to thereby advantageously lower an on-state resistance (Ron) of the MOSFET 10 at a cost of higher gate capacitance (Cgd) and slower switching speed. In particular, the relatively large overlap between the gate electrode 4 and the underlying drift region 3 causes an increase in gate transfer capacitance and gate transfer charge and a corresponding increase in a high-frequency figure-of-merit (HFFOM) for the MOSFET 10. This higher HFFOM results in a higher switching power loss, which inhibits high frequency operation.

(23) Referring now to FIG. 2A, a silicon carbide (SiC) power MOSFET 20a according to an embodiment of the invention is illustrated as including a semiconductor substrate 15 (e.g., SiC) having a substrate region 2 of first conductivity type (e.g., N-type) therein. This substrate region 2 (N+ substrate) is shown as a relatively highly doped region that may be derived from a relatively highly doped SiC material (e.g., SiC wafer/chip, SiC epitaxial layer). The semiconductor substrate 15 further includes a relatively lightly doped N-type drift region 3 (N-Drift) that extends between the substrate region 2 and a first/primary surface 13 of the substrate 15, which has a source electrode 6 (Source) and an advantageously short gate electrode 4 (Gate) thereon. This gate electrode 4 is insulated from surrounding regions by an electrically insulating region 5 (e.g., silicon dioxide).

(24) A relatively highly doped shielding region 7 of second conductivity type (e.g., P-type) is provided in the drift region 3. This shielding region 7 is electrically coupled to the source electrode 6 by a contact region 11 of second conductivity type, which extends between the shielding region 7 and the first surface 13 of the substrate 15, as shown. The shielding region 7 and the contact region 11 are both shown as relatively highly doped P+ regions. A source region 9 of first conductivity type (N+ Source), which forms an ohmic contact with the source electrode 6, a base region 8 of second conductivity type (P-base) and an N-type transition region/layer 17 are provided in the substrate 15. As shown, the N-type source region 9 and the P-type base region 8 extend between the first surface 13 of the substrate 15 and the shielding region 7, which has a greater lateral extent relative to the base region 8.

(25) However, as illustrated and explained more fully hereinbelow (see, e.g., FIGS. 4 and 6A-6G), only a portion of the N-type transition region/layer 17 extends between the shielding region 7 and the first surface 13 of the substrate 15. Moreover, the P-N junction between the N-type transition region/layer 17 and the P-type base region 8 extends underneath the shortened gate electrode 4, which is electrically shielded from the underlying drift region 3 by the laterally extending shielding region 7. This novel shielding benefit is achieved because the lateral extent (i.e., width) of the shielding region 7 is greater than the lateral extent of the gate electrode 4 (and base region 8), when the MOSFET 20a is viewed in transverse cross-section, as shown.

(26) As will be understood by those skilled in the art, the application of a sufficiently positive bias to the gate electrode 4 will turn-on the MOSFET 20a by inducing the formation of an N-type inversion layer channel in the P-type base region 8 and accumulating majority carriers in the transition region/layer 17. This inversion layer channel, which forms adjacent the first surface 13 of the substrate 15, operates to electrically connect the source region 9 to the N-type drift region 3 (via the transition region/layer 17) so that forward on-state current may flow (laterally and vertically) between the source electrode 6 and drain electrode 1 of the MOSFET 20a. In particular, during forward on-state conduction, majority carriers (i.e., electrons) may be provided laterally from the source region 9 to the transition region/layer 17 and the neck region (JFET region) within the drift region 3 and then vertically across the voltage-supporting drift region 3 to the substrate region 2 and drain electrode 1, which is provided on a second surface 12 of the substrate 15.

(27) Referring now to FIG. 2B, a silicon carbide (SiC) power MOSFET 20b according to another embodiment of the invention is illustrated as including a semiconductor substrate 15 (e.g., SiC) having a substrate region 2 of first conductivity type (e.g., N-type) therein. This substrate region 2 (N+ substrate) is shown as a relatively highly doped region that may be derived from relatively highly doped SiC material (e.g., SiC wafer/chip, SiC epitaxial layer). The semiconductor substrate 15 further includes a relatively lightly doped N-type drift region 3 (N-Drift) that extends between the substrate region 2 and a first/primary surface 13 of the substrate 15, which has a source electrode 6 (Source) and an advantageously short gate electrode 4 (Gate) thereon. This gate electrode 4 is insulated from surrounding regions by an electrically insulating region 5 (e.g., silicon dioxide).

(28) A relatively highly doped shielding region 7 of second conductivity type (e.g., P-type) is provided in the drift region 3. This shielding region 7 is electrically coupled to the source electrode 6 by a contact region 11 of second conductivity type, which extends between the shielding region 7 and the first surface 13 of the substrate 15, as shown. The shielding region 7 and the contact region 11 are both shown as relatively highly doped P+ regions. A source region 9 of first conductivity type (N+ Source), which forms an ohmic contact with the source electrode 6, a base region 8 of second conductivity type (P-base), an N-type transition region 17 and a JFET neck region 19 are provided in the substrate 15. As shown, the N-type source region 9, the P-type base region 8 and a portion of the N-type transition region 17 extend between the shielding region 7 and the first surface 13 of the substrate 15. In addition, the JFET neck region 19, which is more highly doped relative to the drift region 3, but more lightly doped relative to the transition region 17, extends to the first surface 13 of the substrate 15, as illustrated, thereby truncating a lateral extent of the transition region 17 (relative to the transition region 17 of FIG. 2A).

(29) As illustrated and explained more fully hereinbelow (see, e.g., FIGS. 5 and 7A-7G), only a portion of the N-type transition region 17 extends between the shielding region 7 and the first surface 13 of the substrate 15. Moreover, the P-N junction between the N-type transition region 17 and the P-type base region 8 extends underneath the shortened gate electrode 4, which is electrically shielded from the underlying drift region 3 by the laterally extending shielding region 7.

(30) As will be understood by those skilled in the art, the application of a sufficiently positive bias to the gate electrode 4 will turn-on the MOSFET 20b by inducing the formation of an N-type inversion layer channel in the P-type base region 8 and accumulating majority carriers in the transition region 17. This inversion layer channel, which forms adjacent the first surface 13 of the substrate 15, operates to electrically connect the source region 9 to the N-type drift region 3 (via the transition region 17 and JFET region 19) so that forward on-state current may flow (laterally and vertically) between the source electrode 6 and drain electrode 1 of the MOSFET 20b. In particular, during forward on-state conduction, majority carriers (i.e., electrons) may be provided laterally from the source region 9 to the transition region 17 and the JFET neck region 19 and then vertically across the voltage-supporting drift region 3 to the substrate region 2 and drain electrode 1, which is provided on a second surface 12 of the substrate 15.

(31) Referring now to FIG. 2C, a silicon carbide (SiC) power MOSFET 20c according to another embodiment of the invention is illustrated as including a semiconductor substrate 15 (e.g., SiC) having a substrate region 2 of first conductivity type (e.g., N-type) therein. This substrate region 2 (N+ substrate) is shown as a relatively highly doped region that may be derived from relatively highly doped SiC material (e.g., SiC wafer/chip, SiC epitaxial layer). The semiconductor substrate 15 further includes a relatively lightly doped N-type drift region 3 (N-Drift) that extends between the substrate region 2 and a first/primary surface 13 of the substrate 15, which has a source electrode 6 (Source), a source electrode extension 6a and an advantageously short gate electrode 4 (Gate) thereon. This gate electrode 4 is insulated from surrounding regions by an electrically insulating region 5 (e.g., silicon dioxide), which also separates and electrically isolates the source electrode extension 6a from the first surface 13, as shown.

(32) A relatively highly doped shielding region 7 of second conductivity type (e.g., P-type) is provided in the drift region 3. This shielding region 7 is electrically coupled to the source electrode 6 (and source electrode extension 6a) by a contact region 11 of second conductivity type, which extends between the shielding region 7 and the first surface 13 of the substrate 15, as shown. The shielding region 7 and the contact region 11 are both shown as relatively highly doped P+ regions. A source region 9 of first conductivity type (N+ Source), which forms an ohmic contact with the source electrode 6, a base region 8 of second conductivity type (P-base), an N-type transition region 17 and a JFET neck region 19 (underneath the transition region 17) are provided in the substrate 15. As shown, the N-type source region 9, the P-type base region 8 and a first portion of the N-type transition region 17 extend between the shielding region 7 and the first surface 13 of the substrate 15, and a second portion of the N-type transition region 17 extends between the JFET neck region 19 and the first surface 13. The JFET neck region 19 is more highly doped relative to the drift region 3, but more lightly doped relative to the transition region 17.

(33) As illustrated and explained more fully hereinbelow (see, e.g., FIGS. 5 and 7A-7G), only a portion of the N-type transition region 17 extends between the shielding region 7 and the first surface 13 of the substrate 15. Moreover, the P-N junction between the N-type transition region 17 and the P-type base region 8 extends underneath the shortened gate electrode 4, which is electrically shielded from the underlying drift region 3 by the laterally extending shielding region 7. In addition, a drain-side end of the gate electrode 4 is at least partially shielded from the transition region (and underlying JFET region 19) by the laterally adjacent source electrode extension 6a, which may be formed of the same material as the gate electrode 4. In this manner, the source electrode extension 6a, which can be defined at the same time as the gate electrode 4 (without requiring any additional process mask) operates to reduce the gate transfer capacitance (Cgd) and the gate transfer charge (Qgd).

(34) As will be understood by those skilled in the art, the application of a sufficiently positive bias to the gate electrode 4 will turn-on the MOSFET 20c by inducing the formation of an N-type inversion layer channel in the P-type base region 8 and accumulating majority carriers in the transition region 17. This inversion layer channel, which forms adjacent the first surface 13 of the substrate 15, operates to electrically connect the source region 9 to the N-type drift region 3 (via the transition region 17 and JFET region 19) so that forward on-state current may flow (laterally and vertically) between the source electrode 6 and drain electrode 1 of the MOSFET 20c. In particular, during forward on-state conduction, majority carriers (i.e., electrons) may be provided laterally from the source region 9 to the transition region 17 and then vertically across the JFET neck region 19 and voltage-supporting drift region 3 to the substrate region 2 and drain electrode 1, which is provided on a second surface 12 of the substrate 15.

(35) Referring now to FIGS. 3A-3E, a comparison of methods of forming the conventional MOSFET of FIG. 1 (with added N-type JFET neck region) and the novel MOSFET of FIG. 2B will be provided. In FIG. 3A, both methods include the use of Mask 1 and Mask 2 (or 2A) to define an edge termination implant (N-type) and an N-type JFET region implant (within a device active area) within a semiconductor substrate (e.g., SiC substrate) having an N-type drift region and N+ substrate region therein. However, as shown at the bottom and right side of FIG. 3A, an additional ion implant Mask 2B (e.g., oxide mask) is used to define a more highly doped and relatively shallow N-type transition region within a surface portion of the more lightly doped JFET region.

(36) Thereafter, as shown by FIG. 3B, a Mask 3 is used to support the formation of conventional P-type base and P+ shielding regions, having the same lateral dimensions, using respective P-type (e.g., aluminum (Al)) implants. In contrast, the right side of FIG. 3B shows the use of separate masks (Mask 3A and 3B) to define the P-base region and the P+ shielding region, respectively. As shown at the bottom and right side of FIG. 3B, a lateral extent of the P+ shielding region is greater than a lateral extent of the P-base region. Next, in FIG. 3C, a Mask 4 is used to support the formation of N+ source regions during the implantation of N-type ions (e.g., nitrogen (N)) and a Mask 5 is used to support the formation of P+ contact regions during the implantation of P-type ions (e.g., aluminum (Al)).

(37) FIG. 3D illustrates the formation of gate electrodes (Gate) having long (left side) and short (right side) dimensions using respective masks (Mask 6). A Mask 7 is then used in both devices to define a source contact area (for source metal) to the P+ contact regions and the N+ source regions. Finally, as shown by FIG. 3E, a Mask 8 is used in both devices to define the source metal and gate contact metal (not shown).

(38) FIG. 4 illustrates cross-sectional views of MOSFET half-cells according to the prior art (left, middle) and according to embodiments of the invention (right). As shown on the left side of FIG. 4, a conventional MOSFET (Cut Gate, Shallow Channel) includes a relatively short gate electrode having a drain-side sidewall that extends 0.0-0.4 m beyond the lateral extent of the base and shielding regions, which are aligned. A thickness of the gate insulating layer extending between the gate electrode and the source electrode (i.e., t.sub.IEOX) is shown as 3000 Angstroms. As shown in the middle of FIG. 4, a conventional MOSFET (Stepped Gate, Shallow Channel) includes a stepped-up gate electrode having a drain-side sidewall that extends 0.0-0.4 m beyond the lateral extent of the base and shielding regions, which are aligned. A thickness of the gate insulating layer extending between the gate electrode and the source electrode (i.e., t.sub.IEOX) is shown as 2000 Angstroms and a thickness of the gate insulating layer extending between a stepped-up portion of the gate electrode and the underlying substrate (i.e., t.sub.OX2) is shown as 3000 Angstroms. As shown on the right side of FIG. 4, a MOSFET (Advanced Cut Gate) according to an embodiment of the invention includes a relatively wide P+ shielding region that extends 0.1-1.0 m beyond the lateral extent of the base region (i.e., 0.1 mL.sub.P.sub._.sub.edge1.0 m), with a gate electrode having a drain-side sidewall that extends 0.0-0.5 m beyond the lateral extent of the base region (i.e., 0.0 mc0.5 m) and a JFET neck region (half-cell) having a width, L.sub.A, equal to 0.5 m.

(39) FIG. 5 is a graph illustrating a range of acceptable transition region thicknesses (between minimum and maximum thicknesses) versus transition region doping for SiC and GaN insulated-gate field effect transistors, according to embodiments of the invention, where the transition region is illustrated as a layer 17 in FIG. 2A. According to preferred aspects of embodiments of the invention, a thickness (t.sub.T) of the transition region, as measured between the first surface 13 of the substrate 15 and the P+ shielding region 7 should be: (i) greater than 0.75(2V.sub.bi.sub.s/qN.sub.T).sup.1/2, where V.sub.bi is the built-in potential of the P-N junction between the N-type transition region 17 and the P+ shielding region 7, .sub.s is the dielectric constant of the transition region 17, q is the electron charge and N.sub.T is the net first conductivity type doping concentration in the transition region 17, and (ii) less than E.sub.c.sub.s/qN.sub.T, where E.sub.c is the critical electric field for breakdown in the transition region 17.

(40) Referring now to FIG. 6A, a half-cell of an insulated-gate field effect transistor (e.g., half-cell) according to an embodiment of the invention (see, e.g., FIG. 2B) is illustrated as including a gate electrode having a drain-side sidewall that exceeds a drain-side end of an underlying P-base region by an amount x, where 0.0 mx1.2 m. A thickness of the P-base region is illustrated as y=0.15 m and a lateral width of an underlying P+ shielding region exceeds a length of the P-base region (i.e., L.sub.cH) by an amount equal to L.sub.P.sub._.sub.edge, where L.sub.P.sub._.sub.edge=0.7 m and L.sub.CH equals 0.5 m. A half-cell width of the JFET neck region is illustrated as L.sub.A, where L.sub.A equals 0.5 m. An N-type doping in the JFET neck region is equal to 410.sup.16 cm.sup.3 and an N-type doping in the transition region (N.sub.JFET,top) is equal to 410.sup.17 cm.sup.3.

(41) Based on this configuration of FIG. 6A, the graph of FIG. 6B illustrates a significant fall-off in breakdown voltage as the dimension x exceeds 0.6 m, for the case where L.sub.P.sub._.sub.edge=0.7 m. Furthermore, as illustrated by FIGS. 6C-6D, Qgd (gate-to-drain charge, specific) and Cgd (gate-to-drain capacitance, specific) increase significantly as x exceeds 0.6 m, whereas the specific on-resistance (Ron, sp) remains relatively constant, as shown by FIG. 6E. The deterioration in performance as x exceeds 0.6 m is also illustrated by FIGS. 6F-6G, where figures-of-merit (FOM) as a function of capacitance C (nano-farads nF) and charge Q (nano-coulombs nC) increase dramatically.

(42) In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.