Cryogenic operation, radiation tolerant, low quiescent current, low drop out voltage regulator

Abstract

A voltage regulator that includes an input voltage; a first JFET transistor, the input voltage being applied to a drain of the first JFET transistor; a second JFET transistor, the input voltage being applied to a drain of the second JFET transistor; and a resistor string, the resistor string including a first resistor, a second resistor and a third resistor, the resistor string and the second JFET transistor forming a voltage reference circuit having a reference voltage.

Claims

1. A voltage regulator comprising: an input voltage; a first JFET transistor, the input voltage being applied to a drain of the first JFET transistor; a second JFET transistor, the second JFET transistor being in series with the first JFET transistor; a third JFET transistor; a resistor string, the resistor string including a first resistor, a second resistor and a third resistor, the resistor string and the third JFET transistor forming a voltage reference circuit having a reference voltage; and a voltage divider, the voltage divider including a fourth resistor and a fifth resistor, the fourth resistor and the fifth resistor dividing a difference between the input voltage and an output voltage, wherein the reference voltage generated from the voltage reference circuit is powered from a mid-point connection between the first JFET transistor and the second JFET transistor.

2. The voltage regulator of claim 1 wherein the first JFET transistor, the second JFET transistor and the third JFET transistor are N-channel JFET transistors.

3. The voltage regulator of claim 1 wherein the first JFET transistor, the second JFET transistor and the third JFET transistor are P-channel JFET transistors.

4. A voltage regulator comprising: an input voltage; a first JFET transistor series, the first JFET transistor series including a first JFET transistor and a second JFET transistor connected in series; a second JFET transistor series, the second JFET transistor series including a third JFET transistor and a fourth JFET transistor connected in series, the first JFET transistor series being in parallel with the second JFET transistor series; a fifth JFET transistor; a resistor string, the resistor string including a first resistor, a second resistor and a third resistor, the resistor string and the fifth JFET transistor forming a voltage reference circuit having a reference voltage; and a voltage divider, the voltage divider including a fourth resistor and a fifth resistor, wherein the voltage divider allows an input-output resistance at a point of regulation to be halved and an output current rating to be doubled.

5. The voltage regulator of claim 4 wherein the first JFET transistor, the second JFET transistor, the third JFET transistor, the fourth JFET transistor and the fifth JFET transistor, are N-channel JFET transistors.

6. The voltage regulator of claim 4 wherein the first JFET transistor, the second JFET transistor, the third JFET transistor, the fourth JFET transistor and the fifth JFET transistor are P-channel JFET transistors.

7. A voltage regulator comprising: an input voltage; a first JFET transistor, the input voltage being applied to a drain of the first JFET transistor; a second JFET transistor; a third JFET transistor, the first JFET transistor, the second JFET transistor the third JFET transistor being connected in series; a fourth JFET transistor; a resistor string, the resistor string including a first resistor, a second resistor and a third resistor, the resistor string and the fourth JFET transistor forming a voltage reference circuit having a reference voltage; a first voltage divider, the voltage divider including a fourth resistor and a fifth resistor, the fourth resistor and the fifth resistor being connected between the input voltage and a source of the second JFET transistor, and a second voltage divider, the second voltage divider including a sixth resistor and a seventh resistor, the second voltage divider being connected between a source of the first JFET transistor and a source of the third JFET transistor, wherein the first voltage divider and the second voltage divider are used to force approximately equal voltage sharing between the series of the first JFET transistor, the second JFET transistor the third JFET transistor.

8. The voltage regulator of claim 7 wherein the first JFET transistor, the second JFET transistor, the third JFET transistor and the fourth JFET transistor are N-channel JFET transistors.

9. The voltage regulator of claim 7 wherein the first JFET transistor, the second JFET transistor, the third JFET transistor and the fourth JFET transistor are P-channel JFET transistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram for a linear regulator of the disclosed technology according to a first implementation:

(2) FIG. 2 is a circuit diagram for a linear regulator of the disclosed technology according to a second implementation;

(3) FIG. 3 is a circuit diagram for a linear regulator of the disclosed technology according to a third implementation;

(4) FIG. 4 is a circuit diagram for a linear regulator of the disclosed technology according to a fourth implementation; and

(5) FIG. 5 is a circuit diagram for a linear regulator of the disclosed technology according to a fifth implementation.

DETAILED DESCRIPTION

(6) The disclosed technology is directed towards a cryogenic operation, radiation tolerant, low quiescent current, low drop out voltage regulator.

(7) In one implementation, as shown in FIG. 1, the voltage regulator can include an input voltage V.sub.IN that can be applied to (1) a drain of an N channel JFET transistor Q13 and (2) a drain of an N channel JFET transistor Q14. The N channel JFET transistor Q14 along with a resistor string forms of a voltage reference circuit. The resistor string can comprise resistors R22, R23 and R24.

(8) In use, the voltage across the resistors R22 and R23 can be approximately equal to a pinch-off voltage of the N channel JFET transistor Q14 (a pinch-off voltage is a threshold voltage below which a J FET transistor turns off). In turn, since the current drawn by the N channel JFET transistor gates Q13 and Q14 is so low, the current through the resistor string is essentially constant. This current, multiplied by the ohmic value of the resistor string, applies a constant reference voltage to the gate of JFET transistor Q13.

(9) In some implementations, the output voltage, V.sub.OUT, which is the source voltage of JFET transistor Q13, is approximately the sum of the reference voltage, V.sub.REF, plus the pinch-off voltage of JFET transistor Q13.

(10) Furthermore, at the point that the input voltage V.sub.IN is close to a desired output voltage set point, JFET transistor Q13 is fully enhanced. Therefore, the output voltage V.sub.OUT is approximately equal to the input voltage V.sub.IN, less a voltage drop across a channel resistance of JFET transistor Q13.

(11) In some implementation, it may be desired to adjust the output voltage set point higher in which a value of resistor R24 can be increased. In some implementation, it may be desired to adjust the output voltage set point lower in which a value of resistor of resistor R22 can be increased.

(12) In some implementation, the temperature coefficient of the reference voltage V.sub.REF may be compensated by selecting a temperature-compensated resistor of a known value in the lower position.

(13) Some advantages to using a reference voltage generated by Q14's pinch-off voltage instead of using a Zener diode include, but are not limited to: (1) the reference voltage being adjustable by selecting the appropriate resistor in the R22, R23 and R24 string, (2) commonly available Zener diodes have higher current requirements than the JFET reference circuit thus using a Zener diode reference would likely cause a higher quiescent current drain and (3) the quiescent current drawn by the circuit of FIG. 1, at no load, is essentially the current drawn for the voltage reference circuit (based on the characteristics of the JFETs used, this current can be as low as several microamperes as compared to several milliamperes for a typical Zener rectifier).

(14) Higher Input Voltage VersionFIG. 2

(15) FIG. 2 shows a modification of the FIG. 1 circuit in the event the drain to source voltage rating of the JFETs is not high enough to withstand the maximum value of the input voltage.

(16) Input voltage V.sub.IN, can be applied to a series of N channel JFET transistors Q1 and Q2. A voltage reference circuit can be powered from the series of N channel JFET transistors at a midpoint between JFET transistors Q1 and Q2. The voltage reference circuit includes N channel JFET transistors Q3 and a resistor string comprised of resistors R3, R4. R5. When the input voltage V.sub.IN is near a desired output voltage set point, both JFET transistors Q1 and Q2 are enhanced. Therefore, the output voltage V.sub.OUT is approximately equal to the input voltage V.sub.IN, less a voltage drop across the channel resistance of the JFET transistor Q1/Q2 series.

(17) As the input voltage VI is increased above the output voltage set point, resistors R1 and R2 divide the difference between the input voltage V.sub.IN and the output voltage V.sub.OUT. The gate of the upper JFET transistor Q1 is at a value of the voltage divider. The source of the upper JFET transistor Q1 is at a gate voltage plus the pinch off voltage of the JFET transistor Q1. In some implementations, if resistors R1 and R2 are approximately the same value, the input to output voltage is equal to half the amount of the input to output voltage, plus the pinch off voltage of JFET transistor Q1.

(18) By using the circuit configuration of FIG. 2, the input to output voltage stress on the JFET transistors Q1 and Q2 is shared, and the circuit may be used at input voltages as much as twice the drain-source voltage rating of each individual JFET.

(19) Also, since the voltage reference V.sub.REF generated by the voltage reference circuit is fed from a midpoint between JFET transistors Q1 and Q2, the voltage stress on the JFET transistor Q3 is also reduced.

(20) The advantage of the disclosed circuit is that the quiescent current drawn by the circuits of FIG. 2 through FIG. 5, at no load, is essentially the current drawn for the voltage reference circuit plus the current drawn through the voltage divider resistors. In the circuits of FIGS. 2 through 5, a minimum load must be used in order to prevent the current flowing through the voltage dividers from raising the output voltage higher than the desired set point. If the voltage divider resistors have high values and based on the characteristics of the JFETs used, this quiescent current can be as low as several microamperes.

(21) Higher Output Current VersionFIG. 3

(22) FIG. 3 shows a modification of the FIG. 2 circuit that can deliver more current, based on similar JFET capability. Input voltage V.sub.IN can be applied to two JFET transistors series that are in parallel to each other. That is, N channel JFET transistors Q8 and Q10 connected in series and N channel JFET transistors Q9 and Q11 connected in series are connected in parallel to each other. That is, the JFET transistors Q8/Q10 series is connected in parallel to the JFET transistor Q9/Q11 series. A voltage reference circuit is powered from the paralleled JFET configuration Q8/Q9/Q10/Q11 at a midpoint between JFET transistors Q8 and Q10 and JFET transistors Q9 and Q11. The voltage reference circuit includes N channel JFET transistors Q12 and a resistor string comprised of resistors R18, R19, R20.

(23) The paralleled JFET configuration Q8/Q9/Q10/Q11 includes a resistor divider comprising resistors R15 and R17. The resistor divider divides the difference between the input voltage V.sub.IN and the output voltage V.sub.OUT. When paralleled JFETs are used, compared to single JFETs, the input output resistance at the point of regulation is halved and the output current rating is doubled.

(24) For the paralleled JFET configuration, each parallel pair of JFETs is matched for pinch-off voltage. As in FIG. 2, the voltage reference circuit of Q12, R18, R19 and R20 is powered from the midpoint of the two pairs of series connected JFETs.

(25) Even Higher Input Voltage VersionFIG. 4

(26) FIG. 4 shows a variation of FIG. 2 for even higher input voltages, wherein three series connected JFETs are used for a higher voltage rating. In this circuit, the input to output voltage drop is shared among three series connected JFETs.

(27) Input voltage V.sub.IN can be applied to N channel JFET transistors Q4, Q5 and Q6 connected in series. A voltage reference circuit is powered from the JFET transistors Q4/Q5/Q6 series at a midpoint between JFET transistors Q5 and Q6. The voltage reference circuit includes N channel JFET transistors Q7 and a resistor string comprised of resistors R12, R13, R14.

(28) Two sets of resistor voltage dividers are used to force approximately equal voltage sharing between the three series connected JFET transistors (Q4, Q5 and Q6). A first resistor divider can comprise resistors R7, R8 connected between the input voltage V.sub.IN and a source of the JFET transistor Q5. This generates a gate voltage for JFET transistor Q4. A second resistor divider can comprise resistors R9, R10 connected between a source of the JFET transistor Q4 and a source of the JFET transistor Q6. This generates a gate voltage for the JFET transistor Q5.

(29) The reference voltage, generated by the JFET transistor Q7 and resistors R12, R13 and R14, is powered from the drain of the JFET transistor Q6 and feeds the gate of the JFET transistor Q6.

(30) In some implementations, this circuit can be adapted for even higher input voltages, by connecting additional JFETs in series and feeding each additional JFET gate from a two-resistor voltage divider.

(31) Negative Input, Negative Output VersionFIG. 5

(32) FIG. 5 shows a negative input, negative output voltage regulator circuit using P channel JFETs. It is similar to the circuit of FIG. 2, except the input and output voltages are negative. In some implementations, the circuits shown in FIGS. 1, 3 and 4 can also be implemented with P channel JFETs for negative input, negative output applications.

(33) As shown in FIG. 5, negative input voltage V.sub.IN is applied to P channel JFET transistors Q5 and Q16 connected in series. A voltage reference circuit is powered from the JFET transistors Q15/Q16 series at a midpoint between JFET transistors Q15 and Q16. The voltage reference circuit includes P channel JFET transistors Q17 and a resistor string comprised of resistors R28, R29, R30.

(34) A negative input voltage can be applied to JFETs Q15 and Q16 connected in series with the voltage reference circuit being powered from a midpoint between Q15 and Q16. When the input voltage is near the desired output voltage set point, both Q15 and Q16 are enhanced. Therefore, the output voltage is approximately equal to the input voltage, less the voltage drop across the channel resistance of Q15 and Q16 in series.

(35) As the input voltage is increased above the output voltage set point, resistors R25 and R27 divide the difference between the input voltage and the output voltage. The gate of upper JFET Q15 is at the value of the voltage divider. The source of upper JFET Q15 is at the gate voltage plus the pinch-off voltage of Q15. If Resistors R25 and R27 are approximately the same value, the input to output voltage is equal to half the amount of the input to output voltage, plus the pinch-off voltage of Q15.

(36) By using the circuit configuration of FIG. 5, the input to output voltage stress on JFETs Q15 and Q16 is shared, and the circuit may be used at input voltages as much as twice the drain-source voltage rating of each individual JFET.

(37) Since the voltage reference generating JFET Q17 is fed from the Q15-Q16 mid-point connection, its voltage stress is also reduced.

(38) The foregoing Detailed Description is to be understood as being in every respect illustrative and exemplary, but not restrictive, and the scope of the disclosed technology disclosed herein is not to be determined from the Detailed Description, but rather from the claims as interpreted according to the full breadth permitted by the patent laws. It is to be understood that the embodiments shown and described herein are only illustrative of the principles of the disclosed technology and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the disclosed technology. Those skilled in the art could implement various other feature combinations without departing from the scope and spirit of the disclosed technology. Although the embodiments of the present disclosure have been described with specific examples, it is to be understood that the disclosure is not limited to those specific examples and that various other changes, combinations and modifications will be apparent to one of ordinary skill in the art without departing from the scope and spirit of the disclosed technology which is to be determined with reference to the following claims.