Arrangement for Diverting Voltage Surges

Abstract

An arrangement for diverting voltage surges is disclosed. In an embodiment an arrangement for arresting overvoltages includes a series circuit including a plurality of gas-filled surge arresters between a first potential node and a reference-ground potential node and at least one RC element comprising a capacitor and a resistor connected in parallel, the RC element being coupled from at least one potential node between the surge arresters directly to the reference-ground potential node.

Claims

1-9. (canceled)

10. An arrangement for arresting overvoltages comprising: a series circuit comprising a plurality of gas-filled surge arresters between a first potential node and a reference-ground potential node; and at least one RC element comprising a capacitor and a resistor connected in parallel, the RC element being coupled from at least one potential node between the surge arresters directly to the reference-ground potential node.

11. The arrangement according to claim 10, wherein the at least one RC element comprises a plurality of RC elements, and wherein each RC element is coupled from a potential node between two adjacent surge arresters directly to the reference-ground potential node.

12. The arrangement according to claim 10, wherein the arrangement comprises groups of surge arresters, wherein the at least one RC element comprises a plurality of RC elements, and wherein each RC element is coupled from a potential node between the individual groups directly to the reference-ground potential node.

13. The arrangement according claim 10, wherein a time constant of the RC element is less than or equal to 1 ms.

14. The arrangement according to claim 10, wherein the capacitance C of the capacitor is greater than or equal to 1 nF and less than or equal to 40 nF.

15. The arrangement according to claim 10, wherein a rated value of the resistor is greater than or equal to 1 k and less than or equal to 100 k.

16. The arrangement according to claim 10, wherein the arrangement is placed in an electronic device.

17. The arrangement according to claim 10, wherein the arrangement is placed in an electrical grid.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described below are not to be seen as true to scale but instead the individual dimensions of the illustrations may be illustrated in an enlarged, reduced or even distorted manner.

[0022] In the drawings:

[0023] FIG. 1a shows a circuit diagram for an arrangement for arresting overvoltages in accordance with the prior art;

[0024] FIG. 1b shows a perspective view of an arrangement for arresting overvoltages in accordance with the prior art;

[0025] FIG. 2a shows a circuit diagram for an arrangement for arresting overvoltages; and

[0026] FIG. 2b shows a perspective view of an arrangement for arresting overvoltages.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0027] FIG. 1a shows a circuit diagram for an arrangement 1 for arresting overvoltages in accordance with the prior art. FIG. 1b shows a perspective view of the arrangement 1 for arresting overvoltages in accordance with the prior art.

[0028] The arrangement 1 has a plurality of gas-filled surge arresters, gas arresters 2 for short. The gas arresters 2 are connected in series. The gas arresters 2 are stacked one above the other in the arrangement 1, as can be seen from FIG. 1b. The arrangement 1 is a so-called multiple stack arrester. A DC voltage can be applied to the series circuit of the gas arresters 2 via a first potential node 6 (L conductor) and a reference-ground potential node 5 (neutral conductor).

[0029] After the current surge has subsided, the so-called follow current flows from the grid, between L and N conductors 6,5. It is necessary to stop or even prevent said follow current as quickly as possible. To achieve this, multiple stack arresters are used. The arc voltage of the individual gas arresters 2 are thus added. The follow current is stopped. This produces the negative side effect that the response surge voltage increases with the number of individual gas arresters 2 (paths) in the stack. The limiting voltage protection level of the multiple stack arrester becomes too high. For this reason, capacitors 3 are connected in parallel with the individual gas arresters 2. In particular, a capacitor 3 connected in parallel is in each case coupled from a potential node 7 between the individual gas arresters 2 to the reference-ground potential node 5.

[0030] The capacitors 3 make the faster turn-on response of the gas arresters 2 in the stack possible.

[0031] After the multiple stack arrester has extinguished the follow current and has returned back to the high-impedance state, the capacitors 3, however, remain partially charged, which minimizes the effect of the capacitor 3 in the case of the next overvoltage. To prevent this, in accordance with the invention, a resistor is used in parallel with the capacitor, as can be seen from FIGS. 2a and 2b.

[0032] FIG. 2a shows a circuit diagram for an arrangement 1 for arresting overvoltages.

[0033] FIG. 2b further shows a perspective view of an arrangement 1 for arresting overvoltages.

[0034] The arrangement 1 has a plurality of gas-filled surge arresters, gas arresters for short, 2. According to this embodiment, the arrangement 1 has between four and ten gas arresters 2. However, other numbers N of gas arresters 2, for example, 15, 20 or 30 gas arresters 2, are also conceivable. The number of gas arresters 2 shown is consequently to be seen purely as exemplary.

[0035] The gas arresters 2 are stacked one above the other (FIG. 2b). The gas arresters 2 are connected in series. In particular, the gas arresters 2 are in series between a first potential node 6 (L conductor) and a reference-ground potential node 5 (neutral conductor).

[0036] A capacitor 3 is connected in parallel with at least some of the gas arresters 2. A resistor 4 is connected in parallel with the respective capacitor 3. According to the embodiment shown in FIG. 2a, an RC element having a resistor 4 connected in parallel and a capacitor 3 is in each case coupled from a potential node 7 between the individual gas arresters 2 to the reference-ground potential node 5. If the arrangement 1 thus has N gas arresters 2, in accordance with the embodiment shown, N1 RC elements are provided in the arrangement 1.

[0037] As an alternative thereto, in a further embodiment, the number of gas arresters 2 may, however, also correspond to the number of RC elements in the arrangement 1 (not explicitly illustrated). Given N gas arresters 2, there are therefore N RC elements too.

[0038] As an alternative thereto, in a further embodiment (not explicitly illustrated), an RC element may be associated with a group of gas arresters 2 connected in series, for exaample, a group of two, three, four or five gas arresters 2. In this case, the arrangement i can have a plurality of groups, for example, two or three groups, of gas arresters 2. An RC element having a resistor 4 connected in parallel and a capacitor 3 is then in each case coupled from a potential node between the individual groups to the reference-ground potential node 5.

[0039] The arrangement i is designed in such a way that the respective capacitor 3 is discharged via the respective resistor 4, and the response surge voltage is thus kept low. The respective capacitor 3 is discharged by the resistor 4 within a few milliseconds (ms) after the surge current. The response surge voltage consequently remains constantly low. Furthermore, the response surge voltage is lower with the capacitor-resistor combination, even in the case of the first response, than without the resistor 4.

[0040] The respective RC element is coupled directly and, in particular, without further interconnected electronic components to the reference-ground potential node 5. The respective RC element is preferably selected in such a way that the time constant =R.Math.C is in the millisecond range, wherein R specifies the rated value of the resistor 4 and C specifies the capacitance of the capacitor 3. Preferably, 1 ms holds true, for example, 0.9 ms or 0.5 ms.

[0041] The capacitors 3 have a capacitance C in the range between 1 nF and 40 nF, wherein the respective end points of the range are included. The capacitance C of the respective capacitor 3 is preferably less than 20 nF, for example, 15 nF or 10 nF. In this case, with a higher capacitance C, the turn-on time (the reaction time) of the respective gas arrester 2 increases. The response surge voltage decreases.

[0042] The resistors 4 have a rated value R in the range between 1 k and loo k, wherein the respective end points of the range are included. The rated value R of the respective resistor 4 is preferably less than 100 k, preferably less than 90 k, for example, 85 k or 82 k. The lower the resistance value, the longer it takes to charge the capacitor 3 during the current pulse. The turn-on time increases.

[0043] The capacitor-resistor combination of 10 nF and 82 k has been found to be particularly advantageous.

[0044] By using the resistor 4, the number of individual gas arresters 2 in the arrangement 1 can be increased and the extinguishing properties of the arrangement 1 can be improved without the response voltage becoming too high.

[0045] The description of the subjects specified here is not limited to the individual specific embodiments. Rather, the features of the individual embodimentsinsofar as it makes technical sensecan be combined with one another arbitrarily.