V-band digital control bandpass amplifier

Abstract

A digitally controlled amplifier (DCA) has a drive (e.g., bipolar junction) transistor with a base to accept an input signal and a collector to supply an output signal. The DCA also includes n switchable gain amplifier networks (SGANs). Each SGAN has a signal input connected to the collector of the drive transistor, an input to accept a logic signal, and a signal output to supply a switchable gain AC output signal to a load in response to the logic signal. The SGAN signal outputs are connected together, typically in parallel, to supply a digitally controlled AC output gain. An auxiliary SGAN may be connected to supply a constant gain AC output signal. Each of the SGANs may have an identical switchable AC gain and accept an independent logic signal to supply (n+1) levels of digitally controlled AC output gain.

Claims

1. A switchable gain amplifier network (SGAN) comprising: a first transistor having a first terminal to accept an input alternating current (AC) signal, a second terminal to supply an AC output signal to a load, and a control terminal; a second transistor having a first terminal connected to the first terminal of the first transistor, a second terminal to accept a direct current (DC) supply voltage, and a control terminal; a first transmission gate having an input to accept a first bias voltage and an output connected to the control terminal of the first transistor, to supply the first bias voltage in response to receiving a logic signal; and, a second transmission gate having an input to accept the a second bias voltage and an output connected to the control terminal of the second transistor, to supply the second bias voltage in response to receiving a complementary logic signal, opposite in polarity to the logic signal.

2. The SGAN of claim 1 further comprising: a first bypass capacitor having a first terminal connected to the control terminal of the first transistor and a second terminal connected to a first reference voltage; and, a second bypass capacitor having a first terminal connected to the control terminal of the second transistor and a second terminal connected to a second reference voltage.

3. The SGAN of claim 1 wherein the first transmission gate comprises: a first n-channel metal-oxide-semiconductor field effect transistor (NMOS) having a first source/drain (S/D) accepting the first bias voltage, a second S/D connected to the control terminal of the first transistor, and a gate accepting a first binary logic signal; a first p-channel metal-oxide-semiconductor field effect transistor (PMOS) having a first S/D accepting the first bias voltage, a second S/D connected to the control terminal of the first transistor, and a gate accepting a second binary logic signal, opposite in polarity to the first binary logic signal; wherein the second transmission gate comprises: a second NMOS having a first S/D accepting the second bias voltage, a second S/D connected to the control terminal of the second transistor, and a gate accepting the second binary logic signal; and, a second PMOS having a first S/D accepting the second bias voltage, a second S/D connected to the control terminal of the second transistor, and a gate accepting the first binary logic signal.

4. The SGAN of claim 3 wherein the first NMOS and first PMOS are a first complementary MOS (CMOS) device; and, wherein the second NMOS and second PMOS are a second CMOS device.

5. The SGAN of claim 1 wherein the first and second transistors are selected from the group consisting of bipolar junction transistors or field effect transistors.

6. A digitally controlled amplifier comprising: a drive transistor with a control terminal to accept an input alternating current (AC) signal and a first terminal to supply a first stage AC output signal; a plurality of switchable gain amplifier networks (SGANs), each SGAN having a signal input connected to the first terminal of the drive transistor, an input to accept a logic signal, and a signal output to supply a switchable gain AC output signal to a load in response to the logic signal; wherein the plurality of SGAN signal outputs are connected together to supply a digitally controlled AC output gain; wherein each SGAN comprises: a first transistor having a first terminal to accept the first stage AC output signal, a second terminal to supply the switchable gain AC output signal, and a control terminal; a second transistor having a first terminal connected to the first terminal of the first transistor, a second terminal to accept a direct current (DC) supply voltage, and a control terminal; a first transmission gate having an input to accept a first bias voltage and an output connected to the control terminal of the first transistor, to supply the first bias voltage in response to receiving a logic signal; and, a second transmission gate having an input to accept a second bias voltage and an output connected to the control terminal of the second transistor, to supply the second bias voltage in response to receiving a complementary logic signal, opposite in polarity to the logic signal.

7. The digitally controlled amplifier of claim 6 further comprising: an auxiliary SGAN having a signal input connected to the first terminal of the drive transistor, an input to accept a non-varying enabling logic signal, and a signal output to supply a constant gain AC output signal, and wherein the auxiliary SGAN signal output is connected to the plurality of SGAN signal outputs.

8. The digitally controlled amplifier of claim 6 wherein the plurality of SGAN signal outputs are connected in parallel.

9. The digitally controlled amplifier of claim 8 wherein the plurality of SGANs equals n number of SGANs, with each SGAN having an identical switchable AC high-gain, with each SGAN accepting an independent logic signal, and wherein n is an integer greater than 1; and, wherein the n SGAN signal outputs are summed together to supply (n+1) levels of digitally controlled AC output gain.

10. The digitally controlled amplifier of claim 6 wherein the drive transistor is a common emitter bipolar junction transistor (BJT) with a base control terminal, a collector first terminal, and an emitter connected to a reference voltage.

11. The digitally controlled amplifier of claim 6 wherein each SGAN further comprises: a first bypass capacitor having a first terminal connected to the control terminal of the first transistor and a second terminal connected to a first reference voltage; and, a second bypass capacitor having a first terminal connected to the control terminal of the second transistor and a second terminal connected to a second reference voltage.

12. The digitally controlled amplifier of claim 6 wherein the first transmission gate comprises: a first n-channel metal-oxide-semiconductor field effect transistor (NMOS) having a first source/drain (S/D) accepting the first bias voltage, a second S/D connected to the control terminal of the first transistor, and a gate accepting a first binary logic signal; a first p-channel metal-oxide-semiconductor field effect transistor (PMOS) having a first S/D accepting the first bias voltage, a second S/D connected to the control terminal of the first transistor, and a gate accepting a second binary logic signal, opposite in polarity to the first binary logic signal; wherein the second transmission gate comprises: a second NMOS having a first S/D accepting the second bias voltage, a second S/D connected to the control terminal of the second transistor, and a gate accepting the second binary logic signal; and, a second PMOS having a first S/D accepting the second bias voltage, a second S/D connected to the control terminal of the second transistor, and a gate accepting the first binary logic signal.

13. The digitally controlled amplifier of claim 12 wherein the first NMOS and first PMOS are a first complementary MOS (CMOS) device; and, wherein the second NMOS and second PMOS are a second CMOS device.

14. The digitally controlled amplifier of claim 6 wherein the first and second transistors are selected from the group consisting of bipolar junction transistors or field effect transistors.

15. The digitally controlled amplifier of claim 6 further comprising: a digital-to-thermometer decoder having an input to accept a binary coded digital signal and outputs to supply thermometer coded logic signals for switching the AC gain of each SGAN.

16. A method for digitally controlling the gain of an amplifier network, the method comprising: providing a switchable gain amplifier network (SGAN) comprising: first and second transistors having connected first terminals to accept an input alternating current (AC) signal, control terminals to accept bias voltages, a first transistor second terminal to supply an AC output signal to a load, and a second transistor second terminal to accept a direct current (DC) supply voltage; first and second transmission gates respectively connected to the first and second transistor control terminals; in response to the first transmission gate accepting a logic signal, connecting an enabling bias voltage to the first transistor control terminal; in response the second transmission gate accepting a complementary logic signal, connecting a disabling bias voltage to the second transistor control terminal; and, the first transistor second terminal supplying a high-gain AC output signal.

17. The method of claim 16 further comprising: in response to the first transmission gate accepting the complementary logic signal, connecting a disabling bias voltage to the first transistor control terminal; in response to the second transmission gate simultaneously accepting the logic signal, connecting an enabling bias voltage to the second transistor control terminal; and, the first transistor second terminal supplying a low-gain AC output signal, lower in gain than the high-gain AC output signal.

18. The method of claim 17 wherein providing the SGAN includes providing a plurality of n SGANs, where n is an integer greater than 1, with the n SGANs having their first terminals connected together, and with the n SGANs having their first transistor second terminals connected together; wherein accepting the logic and complementary logic signals includes accepting an independent logic/complementary logic signal for each SGAN; and, wherein supplying the high-gain and low-gain AC output signals includes supplying (n+1) levels of selectable AC output signal gain.

19. The method of claim 16 wherein accepting the logic and complementary logic signal includes converting a binary coded digital word to a thermometer code.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic block diagram of a switchable gain amplifier network (SGAN).

(2) FIG. 2 is a schematic block diagram depicting the SGAN of FIG. 1 in greater detail.

(3) FIG. 3 is a schematic block diagram of a digitally controlled amplifier.

(4) FIG. 4 is a schematic diagram of a digital gain control bandpass amplifier enabled through the use of the above-described digitally controlled amplifier.

(5) FIG. 5 is a schematic diagram depicting the small-signal model of a common emitter transistor having emitter degeneration impedance Z.sub.e.

(6) FIGS. 6A through 6D are schematic diagrams of a Tapped-C impedance transform.

(7) FIGS. 7A and 7B depict an alternative pair of transforms.

(8) FIGS. 8A through 8E depict impedance transforms used in designing the first filter.

(9) FIG. 9 is a plot of s.sub.11 return loss of the first stage filter.

(10) FIGS. 10A through 10C are schematics depicting filter designs.

(11) FIG. 11 depicts an exemplary V-band digital gain control amplifier.

(12) FIG. 12 is a schematic block diagram depicting DCA 1102 in greater detail, except in excluding the drive transistor, which is shown in FIG. 11.

(13) FIG. 13A depicts a table cross-referencing digital control, thermometer code, and SGAN gain. FIG. 13B is a plot depicting three levels of DCA gain.

(14) FIG. 14 is a plot depicting gain through the V-band digital gain control bandpass amplifier.

(15) FIG. 15 is a flowchart illustrating method for digitally controlling the gain of an amplifier network.

DETAILED DESCRIPTION

(16) FIG. 1 is a schematic block diagram of a switchable gain amplifier network (SGAN). The SGAN 100 comprises a first transistor 102 having a first terminal on line 104 to accept an input alternating current (AC) signal (Vin), a second terminal on line 106 to supply an AC output signal (Vout) to an AC load, represented in part by inductor (L) 112. Also shown is a control terminal on line 110, a direct current (DC) supply voltage (Vcc) connected to L 112, and output port 116. A second transistor 118 has a first terminal connected to the first terminal of the first transistor on line 104, a second terminal on line 120 to accept a DC supply voltage (e.g., Vcc), and a control terminal on line 122. A first transmission gate 124 has an input on line 126 to accept a first bias voltage (B1) and an output connected to the control terminal of the first transistor on line 110, to supply the first bias voltage in response to receiving a logic signal on line 128. A second transmission gate 130 has an input on line 132 to accept the a second bias voltage (B2) and an output connected to the control terminal of the second transistor on line 122, to supply the second bias voltage in response to receiving a complementary logic signal on line 134, opposite in polarity to the logic signal. In one aspect, the first and second bias voltages are the same value.

(17) In an optional aspect, as shown, a first bypass capacitor 136 has a first terminal connected to the control terminal of the first transistor on line 110 and a second terminal connected to a first reference voltage (R1) on line 138. A second bypass capacitor 140 has a first terminal connected to the control terminal of the second transistor on line 122 and a second terminal connected to a second reference voltage (R2) on line 142. Typically, the first and reference voltages are a DC voltage or ground. It is also typical that the first and second references voltage be the same voltage. Bypass capacitors 136 and 140 keep the control voltages relatively constant despite the high frequency signal on lines 104 and 106. They are chosen to be as large as practical without taking up too much silicon area. For example, a size of 0.5 pF bypass capacitor typically meets this tradeoff and significantly improves the operation, as compared to when they are not included.

(18) FIG. 2 is a schematic block diagram depicting the SGAN of FIG. 1 in greater detail. In this example, the first transistor 102 and second transistor 118 are depicted as bipolar junction transistors (BJTs), in which case their first terminals are emitters, their second terminals are collectors, and their control terminals are bases. Alternatively but not shown, the first and second transistors may be field effect transistors (FETs). In the case of BJTs, the first and second bias voltages might be more specifically referred to as bias currents or bias signals. The first transmission gate 124 comprises a first n-channel metal-oxide-semiconductor field effect transistor (NMOS) 200 having a first source/drain (S/D) on line 126 accepting the first bias voltage, a second S/D connected to the control terminal of the first transistor on line 110, and a gate accepting a first binary logic signal on line 128. A first p-channel metal-oxide-semiconductor field effect transistor (PMOS) 202 has a first S/D accepting the first bias voltage on line 126, a second S/D connected to the control terminal of the first transistor on line 110, and a gate accepting a second binary logic signal on line 134, opposite in polarity to the first binary logic signal.

(19) The second transmission gate 130 comprises a second NMOS 204 having a first S/D accepting the second bias voltage on line 132, a second S/D connected to the control terminal of the second transistor on line 122, and a gate accepting the second binary logic signal on line 134. A second PMOS 206 has a first S/D accepting the second bias voltage on line 132, a second S/D connected to the control terminal of the second transistor on line 122, and a gate accepting the first binary logic signal on line 128. Inverters 208 and 210 are shown, used to convert the first binary logic signal to the second binary logic signal. In one aspect, the first NMOS 200 and first PMOS 202 are a first complementary MOS (CMOS) device. Likewise, the second NMOS 204 and second PMOS 206 may be a second CMOS device.

(20) FIG. 3 is a schematic block diagram of a digitally controlled amplifier. The digitally controlled amplifier 300 comprises a drive transistor 302 with a control terminal on line 304 to accept an input AC signal (V1) and a first terminal on line 104 to supply a first stage AC output signal (Vin). In one aspect, as shown, the drive transistor 302 is a common emitter BJT with a base control terminal, a collector first terminal, and an emitter connected to a reference voltage (R3) on line 306. Alternatively but not shown, the drive transistor may be a FET. The digitally controlled amplifier also comprises a plurality of SGANs. SGANs 100-1 through 100-n are shown, where n is an integer not limited to any particular value, except that it is typically greater than 1. Each SGAN 100-1 through 100-n has a signal input connected to the first terminal of the drive transistor on line 104. SGANs 100-1 through 100-n respectively have inputs 308-1 through 308-n to accept a logic signal, and they each have a signal output on line 106 to supply a switchable gain AC output signal to a load (not shown) in response to the logic signals. Details of the SGAN are presented in the explanations of FIGS. 1 and 2, and are not repeated here in the interest of brevity. The plurality of SGAN signal outputs are connected together, typically in parallel as shown on line 106, to supply a digitally controlled AC output gain.

(21) In an optional aspect as shown, the digitally controlled amplifier 300 further comprises an auxiliary SGAN 310 having a signal input connected to the first terminal of the drive transistor on line 104, an input to accept a non-varying enabling logic signal 312, and a signal output to supply a constant gain AC output signal. Alternative stated, and briefly referring to FIG. 2, transistor 102 is always enabled in the auxiliary SGAN, and transistor 118 is always disabled. Returning to FIG. 3, the auxiliary SGAN signal output is connected to the plurality of SGAN signal outputs on line 106.

(22) In one aspect, each SGAN 100-1 through 100-n, as well as auxiliary SGAN 310 if included, has an identical switchable AC high-gain. Further, SGANs 100-1 through 100-n respectively accept independent logic signals 308-1 through 308-n. If n SGAN signal outputs are summed together, they potentially supply (n+1) levels of digitally controlled AC output gain. In a different aspect, the high-gain level of each SGAN may be different, in which case the digitally controlled amplifier could potential provide many more gain levels than (n+1).

(23) Also shown is a digital-to-thermometer decoder 314 having an input on line 316 to accept a binary coded digital signal and thermometer code outputs on lines 308-1 through 308-n. For example, if n=7, then a 3-bit digital word can be used to create a thermometer code of 8 values (n+1), assuming all SGANs have the same high-gain level. In one aspect not shown, the decoder 314 may supply both the logic and complementary logic signals. Alternatively, as shown in FIG. 2, each SGAN can create its own complementary logic signal.

(24) FIG. 4 is a schematic diagram of a digital gain control bandpass amplifier enabled through the use of the above-described digitally controlled amplifier. The digital gain control bandpass amplifier 400 uses two digitally controlled amplifiers (DCAs) 300-1 and 300-2. In front of the first and second digitally controlled amplifiers, and after the second DCA 300-2 are fourth-order filters (when considered along with the input impedance of the common-emitter drive transistors), respectively labeled 400-1, 400-2, and 400-3. Separate bias blocks 402 and 404 are used to set the current levels and bias voltages.

(25) A specific example of a V-band digital gain control bandpass amplifier is presented below. The V-band digital gain control bandpass amplifier, DCA, and SGAN were initially derived through extensive modeling.

(26) Circuit Model for Common Emitter Transistor with Emitter Degeneration

(27) FIG. 5 is a schematic diagram depicting the small-signal model of a common emitter transistor having emitter degeneration impedance Z.sub.e.

(28) We have
v.sub.b(sC.sub.be)v.sub.be=i.sub.b(1)
and
v.sub.e(Y.sub.E+sC.sub.be)v.sub.bsC.sub.be=g.sub.m(v.sub.bv.sub.e)(2)
Combining (1) and (2), and solving for Z.sub.in=v.sub.b/i.sub.b gives

(29) $\begin{array}{cc}{Z}_{\mathrm{in}}=\frac{v_b}{i_b}=\frac{{\mathrm{sC}}_b+g_m+Y_E}{{\mathrm{sC}}_{\mathrm{be}}{Y}_E}& \left(3\right)\end{array}$
For the special case of Y.sub.E=1/(sL.sub.E), we have

(30) $\begin{array}{cc}{Z}_{\mathrm{in}}={\mathrm{sL}}_E+\frac{1}{\left({\mathrm{sC}}_{\mathrm{be}}\right)}+\frac{g_m{L}_E}{C_{\mathrm{be}}}& \left(4\right)\end{array}$
Noting that .sub.t=g.sub.m/C.sub.be, (4) may be re-written as

(31) $\begin{array}{cc}{Z}_{\mathrm{in}}={\mathrm{sL}}_E+\frac{1}{\left({\mathrm{sC}}_{\mathrm{be}}\right)}+{}_t{L}_E& \left(5\right)\end{array}$

(32) Alternative designs might have an additional inductor L.sub.b placed in series with the base; for this case we have

(33) $\begin{array}{cc}{Z}_{\mathrm{in}}=s\left(L_b+L_E\right)+\frac{1}{\left({\mathrm{sC}}_{\mathrm{be}}\right)}+{}_t{L}_E& \left(6\right)\end{array}$
and we see that at resonance, the input impedance is real and equal to .sub.tL.sub.E. Furthermore, the frequency of resonance is given by

(34) $\begin{array}{cc}{}_0=\frac{1}{\sqrt{C_{\mathrm{be}}\left(L_b+L_E\right)}}& \left(7\right)\end{array}$
Impedance Transforms.

(35) FIGS. 6A through 6D are schematic diagrams of a Tapped-C impedance transform. In designing the filters for the variable gain receiver, a number of impedance transforms were used. When going from FIGS. 6A to 6B, the resistance and reactance of the two networks is identical at.sub.0 if the circuits have the same Q-factors. This results in

(36) $\begin{array}{cc}{R}_2=\frac{R_1}{1+Q_1^2}& 8)\end{array}$

(37) and

(38) $\begin{array}{cc}{C}_2=C_1\frac{1+Q_1^2}{Q_1^2}& 9)\end{array}$

(39) When going from FIGS. 6B to 6C, C.sub.2 is replaced by two series capacitors (C.sub.3, C.sub.4) where the value of the series combination is equal to C.sub.2. We now have

(40) $\begin{array}{cc}{Q}_2=\frac{1}{{}_0{R}_2{C}_4}& 10)\end{array}$

(41) where Q.sub.2 is less than Q.sub.1. We then use the same transformation as used when going from FIGS. 6A to 6B, but now in the opposite direction. The circuit of FIG. 6D has

(42) $\begin{array}{cc}{R}_3=R_1\frac{1+Q_2^2}{1+Q_1^2}& 11)\end{array}$

(43) The value of Q.sub.2 is chosen to get the desired ratio of R.sub.3/R.sub.1. This transform was used when designing the filter in front of the first stage.

(44) FIGS. 7A and 7B depict an alternative pair of transforms. Norton's first transform is applied to a capacitor in FIG. 7A and Norton's second transform is applied for an arbitrary impedance in FIG. 7B. These transforms can be used to replace either a series element (which is often either a capacitor or an inductor) and an ideal transformer by a pi network having the same type of components, or a shunt component by a T-network. The transformer is obtained by impedance transforming all components to the right of the original series or shunt component. When K>1 the impedances become smaller by 1/K.sup.2. If the series element is a capacitor, this means the capacitance values become larger. In addition, for K>1, the left element of the pi network is negative and must be absorbed by a positive capacitor to the left of the series network. When replacing a shunt component, the right component of the resulting T-network is negative and must be absorbed by a positive component to its right.

(45) First-Stage Filter.

(46) FIGS. 8A through 8E depict impedance transforms used in designing the first filter. The first-stage filter is based on first designing a second-order low-pass filter, having a maximally-flat pass-band (i.e. Q=1/{square root over (2)}) and then transforming this filter to a pass-band filter. This transform can be applied directly to the components of the low-pass filter. An inductor in the low-pass filter, L.sub.1 transforms to the series combination of an inductor, L.sub.2, and a capacitor C.sub.2, where
L.sub.2=L.sub.1/B
C.sub.2=1/(.sub.0.sup.2L.sub.1)12)

(47) With B being the bandwidth in radians, and .sub.0 being the center frequency of the bandpass filter (in radians). Similarly, a capacitor, C.sub.1, in the low-pass filter transforms to the parallel combination of L.sub.2 and C.sub.2 where now
L.sub.2=1/(.sub.0.sup.2C.sub.1)
C.sub.2=C.sub.1/B13)

(48) The process for designing the first filter is as follows:

(49) 1. Design a second-order low-pass at .sub.3 dB=1 rad. The low-pass prototype was designed to have a bandwidth of 12 GHz, and somewhat arbitrarily to have equal input and output impedances of 50 ohms. These were later modified in a second iteration, which is explained below. Next the low-pass prototype was transformed to the bandpass domain. The resulting network is shown in FIG. 8A.

(50) The values are:
L.sub.1=116.2 pH C.sub.1=103.0 fC
L.sub.2=3414.3 pH C.sub.2=3.506fC14)

(51) Next the tapped-C impedance transform is applied when going from FIG. 8A to FIG. 8D. It was decided to choose C.sub.3=2C.sub.2; this results in Q.sub.2=Q.sub.1/2. Knowing this fact, then using (11), we see that if we want to end up at circuit (e) having R.sub.3=50, we need to start with R.sub.1=182.04, as Q.sub.1 was found to be 5.42115. When going from the circuit in FIG. 8C to 8D, C.sub.3 originally having a value of 213.10 femto-farads (fF) transformed to a value of 187.57 fF using (9).

(52) 2. In the next step, Norton's First Transform was applied to the series inductor (L.sub.2) to transform R.sub.L from 182.04 to 50 using K={square root over ((182.04/50))}=1.9080. This also transformed the series capacitor from 3.506 femto-coulombs (fC) to 12.764 fC. In the resulting inductive pi network, the left most inductor was negative; this was combined with the parallel inductor (L.sub.1) to give L.sub.3=119.88 pico-Henrys (pH).

(53) 3. The series capacitor C.sub.h is realized by the filter capacitor combined with the capacitance looking into the base of the drive transistor of the first stage. This capacitance (C.sub.be) was found from simulation by isolating the base (by setting C.sub.6 to 0) and injecting an ac current source having a value of unity. The imaginary part of the voltage across the ac current source (z.sub.be) is used to find C.sub.be using

(54) 0$\begin{array}{cc}{C}_{\mathrm{be}}=\frac{-1}{{}_0{z}_{\mathrm{be}}}& \left(15\right)\end{array}$

(55) FIG. 9 is a plot of s.sub.11 return loss of the first stage filter.

(56) Once C.sub.be was found, the capacitance added was chosen so the series combination of C.sub.be and the capacitance added was equal to 12.764 fC, the ideal size of the capacitor.

(57) 4. Next, the inductor in series with the emitter was adjusted so that at 46 Gz, the real part of the admittance looking into the base was exactly 50 and the capacitor added was also adjusted so the reactance was equal to that of an ideal 12.765 fC capacitor.

(58) 5. The reflection coefficient (s.sub.11) was found using the formula

(59) $\begin{array}{cc}{s}_{11}=V_{\mathrm{in}}\frac{Z_{\mathrm{in}}-R_s}{Z_{\mathrm{in}}+R_s}=V_{\mathrm{in}}\frac{2Z_{\mathrm{in}}}{Z_{\mathrm{in}}+R_s}-V_{\mathrm{in}}& 16)\end{array}$

(60) Which can be implemented using two ac voltage sources with the first one having a value of 2 connected to R.sub.s and the second one connected between the right side of R.sub.s and to a node named s11 (the negative side of the second source). A plot of S.sub.11 shown in FIG. 9 illustrates the success of this matching process.

(61) Second and Third Filters

(62) FIGS. 10A through 10C are schematics depicting filter designs. The second and third filters are based on singly-terminated low-pass prototypes. The low-pass prototype is shown in FIG. 10A.

(63) The impedance chosen was 350 ohms. This is transformed to 46 GHz with a 12 GHz bandwidth resulting in the filter shown in FIG. 10B. Next, the output capacitance of the first stage is found using simulation to be 21.338 fF. This is subtracted from the original value for C.sub.1 (of 42.872 fF) to give a C.sub.1 of 21.534 fF. This value of C.sub.1 is then used with Norton's Second Transform to impedance scale the load resistance to 50 as shown in FIG. 10C. The negative capacitor (C.sub.5) is left intact for now, as the T-network and L.sub.1 resonate at 46 GHz including the output capacitance of the first stage. This resonance is adjusted using the simulator to be exact by adjusting L.sub.1. After this step is completed, the negative capacitance is then combined with C.sub.6 to get a single capacitor of 48.97 fF. Next, the actual capacitance is adjusted so the input impedance looking into the second stage including the capacitor is equal to 50 in series with 48.97 fF which adjusts the resonance of the second pole of the filter.

(64) After the filters are added to the over-all variable gain receiver, the sizes of L.sub.1 are adjusted smaller to give a flat passband while keeping the two filters matched.

(65) Digitally Controlled Amplifier (DCA)

(66) The DCA was designed by replacing the cascode transistor with a switching network that can shunt current away to the power supply. This changes the gain amplifiers to being variable gain amplifiers. In one example, the switch networks are realized using one always on switch, and seven switches that could be turned on or off using a binary to thermometer decoder. The schematic of a single switch is shown in FIGS. 1 and 2. The use of transmission gates and bypass capacitors minimizes errors caused by the on-resistance of n-channel only gates.

(67) FIG. 11 depicts the exemplary V-band digital gain control amplifier 1100. In this design there are 2 DCAs, DCA 1102 and 1104. It is assumed that the source resistor RS is 50 and that the output resistance being driven is also 50. The results of the design are listed in Table 1.

(68) TABLE-US-00001 TABLE 1 Gain 3.1 dB-40.5 dB Power 26 mW Supply Voltage 1.8 V Center Frequencies 46 GHz Noise Figure 1.9 dB IIP3 (gain =3.1 dB) 1.5 dBm OIP3 1.6 dBm 1 dB Bandwidth 8 GHz 3 dB Bandwidth 10 GHz FOM 49.6

(69) FIG. 12 is a schematic block diagram depicting DCA 1102 in greater detail, except in excluding the drive transistor, which is shown in FIG. 11. DCA 1102 (and 1104 not shown) comprises 8 SGANs. Each of the DCAs is implemented with a cascode architecture. This was done to minimize the effects of the base-collector capacitance (C.sub.bc) as the cascode transistor minimizes the gain from the base to the collector of the drive transistor. In addition, inductive emitter degeneration was used to improve the noise figure. One (auxiliary) SGAN 310 is always ON, the other switches 100-1 through 100-7 can be ON or OFF as determined by a 3-bit digital control. The 3-bit digital control (D[2:0]) on line 316 is decoded into 7 digital thermometer code bits (S[7:0]) 308-1 through 308-7. The number of digital thermometer bits high is equal to the binary value of the 3-bit digital control signal. The 7 digital thermometer code bits control the switches in the DCA. When a thermometer control bit is high, the switch sends its emitter current to the output where it contributes to the gain. Otherwise, the emitter current is switched to the positive output supply.

(70) As shown in FIG. 2, each of the 7 digital thermometer code bits controls two transmission gates inside each switch. One of the transmission gates is on (or at low impedance), and the other one is off or at high impedance. When the digital thermometer code bit is high, then the transmission gate connected to line 110 is a low impedance, connecting line 110 to reference voltage B1, which is nominally 1.55V. In this case, the transmission gate connected to line 122 is off or low impedance. Thus, the base current to transistor 118 is zero, and line 122 falls to a nominal voltage of 1.13V. In this case, transistor 102 is ON and transistor 118 is OFF, and all the emitter current goes through transistor 102 to the output contributing to the signal gain.

(71) When the digital thermometer code is low, then line 110 is at 1.13V and transistor 102 is OFF. The voltage on line 122 is 1.55V and transistor 118 is ON. In this case, all the emitter current is shunted through transistor 118 to the positive power supply voltage, and the emitter current does not contribute to the DCA gain.

(72) FIG. 13A depicts a table cross-referencing digital control, thermometer code, and SGAN gain. FIG. 13B is a plot depicting three levels of DCA gain. Each SGAN nominally contributes a gain of 3.29. For example, if the 3-bit digital control has a value of 3, then 3 of the 7 digital thermometer code bits are high. This means 4 switches contribute to the gain current (as one switch is always ON). Since each switch nominally contributes a gain of 3.29, with 4 switches contributing to the gain, the nominal gain is 43.29=13.15. This is the same as 22.4 dB.

(73) Simulation Results

(74) FIG. 14 is a plot depicting gain through the V-band digital gain control bandpass amplifier. The same digital inputs were used for each of the decoders and the values were stepped from the smallest value to the highest. It is seen that the gain range is 3.5 dB to 40.5 dB.

(75) The noise figure was found by turning all noise sources off except for Rs, and running a noise simulation. Next all the noise sources were turned on and the noise simulation was re-run. The difference between the spectral density of the noise at 46 GHz was 1.9 dB.

(76) The output third intercept point (OIP3) and input third intercept point (IIP3) simulations were found by using transient simulations with two sinusoidal inputs, one at 46 GHz, and a second with equal amplitude at 47.25 GHz. Ten periods of the beat frequency (the beat frequency is 1.25 GHz, ten periods is 8 nanoseconds (ns)) were analyzed using a 65536 point fast Fourier transform (FFT). The distortion products were clearly visible. These analyses were done at different input levels and attenuation settings. A typical value with the input power levels at 30 dBm and the minimum gain settings gave OIP3=1.6 dBm, and IIP3=1.5 dBm.

(77) The figure of merit (FOM) is given by
FOM=NF+IIP310 log(PWR)+GN.sub.dB+10 log(F0)+10 log(BW)(17)

(78) where NF is the Noise Figure in dB, IIP3 is the input-referred IP3 in dBm, PWR is the Power in mW, GN.sub.dB is the Gain in dB from the input of the V-band amplifier to the output, F0 is the center frequency of the pass-band in GHz, and BW is the pass-band Bandwidth, again in GHz. This FOM is different than most others in that it includes a factor for the bandwidth, as the larger the bandwidth, the more difficult it is to achieve good impedance matching at the input. A different weighting might be considered; for example, it might be argued that the IIP3 and NF terms should be weighted more highly. Since, the design being reported is very good in both these respects, this would favor it even more highly than other designs. The combination of large gain, low noise figure, and high IIP3 give an over-all figure-of-merit of 49.6 which is considerably better than the next best figure-of-merit found in the literature (to date) of 25.6. Many designs reported in the literature are missing critical aspects included in the figure of merit. Many designs realized in a similar silicon-germanium (SiGe) technology, with all parameters reported, have FOMs of around 15-25, considerably less than the reported design.

(79) FIG. 15 is a flowchart illustrating method for digitally controlling the gain of an amplifier network. Although the method is depicted as a sequence of numbered steps for clarity, the numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, repeated, or performed without the requirement of maintaining a strict order of sequence. Generally however, the method follows the numeric order of the depicted steps, and the details of the method are supported by the explanations of the figures above. The method starts at Step 1500.

(80) Step 1502 provides a SGAN comprising first and second transistors having connected first terminals to accept an input AC signal, and control terminals to accept bias voltages. The first transistor second terminal supplies an AC output signal to a load, and the second transistor second terminal accepts a DC supply voltage. Step 1502 also provides first and second transmission gates respectively connected to the first and second transistor control terminals. Examples of such a SGAN have been presented above in the explanations of FIGS. 1 and 2.

(81) In response to the first transmission gate accepting a logic signal, Step 1504 connects an enabling bias voltage to the first transistor control terminal. In response the second transmission gate accepting a complementary logic signal, Step 1506 connects a disabling bias voltage to the second transistor control terminal. In Step 1508 the first transistor second terminal supplies a high-gain AC output signal. In one aspect, accepting the logic and complementary logic signal in Steps 1504 and 1506 includes converting a binary coded digital word to a thermometer code.

(82) Alternatively, if the first transmission gate accepts the complementary logic signal, Step 1510 connects a disabling bias voltage to the first transistor control terminal. In response to the second transmission gate simultaneously accepting the logic signal, Step 1512 connects an enabling bias voltage to the second transistor control terminal. In Step 1514 the first transistor second terminal supply a low-gain AC output signal, lower in gain than the high-gain AC output signal. In one aspect, the low-gain is equal to no gain.

(83) In another aspect, Step 1502 provides a plurality of n SGANs, where n is an integer greater than 1. The n SGANs have their first terminals connected together, and the n SGANs have their first transistor second terminals connected together, as represented in FIGS. 3 and 12. Then, accepting the logic and complementary logic signals in Steps 1504, 1506, 1510, and 1512 includes accepting an independent logic/complementary logic signal for each SGAN. As a result, supplying the high-gain and low-gain AC output signals in Steps 1508 and 1514 includes supplying (n+1) levels of selectable AC output signal gain.

(84) A system and method have been provided for a digitally controlled amplifier enabled by a switchable gain amplifier network. Examples of particular structures, circuit topographies, and device types have been presented to illustrate the invention. However, the invention is not limited to merely these examples. Other variations and embodiments of the invention will occur to those skilled in the art.