Multi-level adiabatic charging methods, devices and systems

Abstract

A method for adiabatic charging of a capacitive load sequentially connects outer switches between a voltage V.sub.DD and ground and inner switches to at least one capacitance that self-balances between V.sub.DD and ground. A voltage waveform is provided to the capacitive load from a common node of the outer switches and the inner switches. An adiabatic charging circuit includes outer transistor switches between a voltage V.sub.DD and ground. Inner transistor switches are connected to at least one capacitance that self-balances between V.sub.DD and ground. A control signal generating circuit generates control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at a common node of the inner and outer transistor switches.

Claims

1. An adiabatic charging circuit, comprising: outer transistor switches between a voltage VDD and ground; inner transistor switches connected to at least one capacitance self-balanced at a level between VDD and ground; a common node of the outer and inner transistor switches and a capacitive load; and a control signal generating circuit to generate control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at the common node, wherein the outer transistor switches comprise a first inverter and a second inverter whose outputs are tied together at the common node, the first inverter being powered between the voltage V.sub.DD and ground and the second inverter being connected to the at least one capacitance, and wherein the at least one capacitance comprises two separate capacitances self-balanced at two different levels between V.sub.DD and ground, and the separate capacitances respectively charge to voltages of 2/3 V.sub.DD and 1/3 V.sub.DD.

2. An adiabatic charging circuit, comprising: outer transistor switches between a voltage VDD and ground; inner transistor switches connected to at least one capacitance self-balanced at a level between VDD and ground; a common node of the outer and inner transistor switches and a capacitive load; and a control signal generating circuit to generate control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at the common node, wherein the outer transistor switches comprise a first inverter and a second inverter whose outputs are tied together at the common node, the first inverter being powered between the voltage V.sub.DD and ground and the second inverter being connected to the at least one capacitance, and wherein the second inverter comprises NMOS transistors sized 3 of NMOS transistors in the first inverter.

3. An adiabatic charging circuit, comprising: outer transistor switches between a voltage VDD and ground; inner transistor switches connected to at least one capacitance self-balanced at a level between VDD and ground; a common node of the outer and inner transistor switches and a capacitive load; and a control signal generating circuit to generate control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at the common node, wherein the capacitive load comprises one of an on-chip pad, an off-chip PCB trace or a neural stimulation electrode.

4. The charging circuit of claim 3, wherein the outer transistor switches comprise a first inverter and a second inverter whose outputs are tied together at the common node, the first inverter being powered between the voltage V.sub.DD and ground and the second inverter being connected to the at least one capacitance.

5. The charging circuit of claim 3, wherein the at least one capacitance consists of one or more passive capacitors.

6. An adiabatic charging circuit, comprising: outer transistor switches between a voltage VDD and ground; inner transistor switches connected to at least one capacitance self-balanced at a level between VDD and ground; a common node of the outer and inner transistor switches and a capacitive load; and a control signal generating circuit to generate control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at the common node, wherein the control generating circuit comprises a tunable chain of inverters producing three signals, A, B, and C, with equal delay times, t, and a timing gate that receives A, B, and C and generates four sequential control signals for the inner and outer transistor switches.

7. The charging circuit of claim 6, wherein the timing gate comprises a House-of-Cards timing gate.

8. The charging circuit of claim 6, consisting of the inner and outer switches, the common node, the at least one capacitance, and the control signal generating circuit.

9. An adiabatic charging circuit, comprising: outer transistor switches between a voltage VDD and ground; inner transistor switches connected to at least one capacitance self-balanced at a level between VDD and ground; a common node of the outer and inner transistor switches and a capacitive load; and a control signal generating circuit to generate control signals for the inner and outer transistor switches that sequentially turn the inner and outer switches on and off to create a multi-level voltage staircase waveform at the common node, wherein the capacitive load comprises an H-clock tree.

10. The charging circuit of claim 9, wherein the outer transistor switches consist of a first inverter and a second inverter whose outputs are tied together at the common node, the first inverter being powered between the voltage V.sub.DD and ground and the second inverter being connected to the at least one capacitance.

11. An adiabatic charging circuit for charging a capacitive load connected to a node, comprising: first means for providing voltage to the node from a voltage source V.sub.DD; second means for providing no voltage to the node; third means for providing a capacitive stored voltage to the node; and means for sequencing the first means, second means and the third means to create a staircase voltage waveform at the node, the capacitive load comprising means for distributing a clock signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1A-1C (prior art) respectively illustrate prior resonant clocking, intermittent resonant clocking and quasi-resonant clocking approaches for aiding capacitive load charging of a clock tree;

(2) FIGS. 2A and 2B respectively illustrate a preferred on-chip adiabatic multi-level charging circuit and the switching states for stepwise charging and discharging of a load, such as a clock tree having a C.sub.CLK capacitance;

(3) FIGS. 3A-3D illustrates a preferred reconfigurable 4-level inverter to implement the FIG. 2A adiabatic multi-level circuit and waveforms for 4-Level and 3-Level Clock modes

(4) FIGS. 4A-4C illustrate a preferred prototype implementation of the FIGS. 3A-3D reconfigurable inverter;

(5) FIGS. 5A-5C compare performance of the prototype to conventional clock signal generation approaches;

(6) FIGS. 6A-6B are respectively performance comparison data and example waveforms of the prototype; and

(7) FIG. 7 is a table that compares performance of the prototype to state-of-the art prior clock generation circuits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(8) Preferred embodiments of the invention provide adiabatic charging via multiple levels in a small, efficient structure via a switched-capacitor circuit and method. The present inventors believe that this is the first practical approach that enables adiabatic charging in a practical solution. Experiments have demonstrated the multi-level adiabatic charging in a clocking application, while artisans will appreciate the general applicability to arbitrary capacitive loads. An example application of the invention demonstrates a fully-integrated adiabatic clocking scheme that efficiently synthesizes n-step clock waveforms from 1 MHz to 2 GHz via a switched-capacitor DC-AC multi-level inverter topology, theoretically reducing power by 1/n without using any magnetic components.

(9) Preferred embodiments are used as on-chip adiabatic charging circuits, and are especially advantageous to on-chip implementations. However, the present invention is applicable in other circuits. Additional applications include on-chip pads, off-chip PCB traces, a neural stimulation electrodesand any other applications that require a circuit to drive a capacitor via a voltage source.

(10) Preferred embodiments of the invention will now be discussed with respect to the drawings and experimental devices. The drawings may include schematic representations, which will be understood by artisans in view of the general knowledge in the art and the description that follows. Features may be exaggerated in the drawings for emphasis, and features may not be to scale.

(11) FIGS. 2A-2B illustrates a preferred on-chip integrated circuit for adiabatic charging. Unlike the prior approaches, clock power is reduced in the present approach through an adiabatic stepwise charging technique implemented using a 4-level switched-capacitor DC-AC inverter topology. In this approach, the CLK capacitance (C.sub.CLK) (for example a clock tree, an on-chip pad, off-chip PCB trace, a neural stimulation electrodesor another capacitive load) is step-wise charged by sequentially turning on switches s1, s2, s3, and s4, which creates a 4-level voltage staircase (more generally a multi-level staircase can be used) whose levels are set by GND, self-balanced capacitors C.sub.1 and C.sub.2, and V.sub.DD. More levels can be added to the staircase by adding additional self-balanced capacitors and corresponding switches. Afterwards, CLK is brought down stepwise to GND in the reverse order. The switching sequence is illustrated in FIG. 2B. Theoretically, 4-level adiabatic charging reduces CLK power by 3. By repeating the same operation periodically at f.sub.CLK, a KVL-constrained multi-phase switched network is established, which inherently enforces V.sub.L2=V.sub.DD/3 and V.sub.L3=2/3V.sub.DD without any explicit DC-DC converter. Both capacitors C.sub.1 and C.sub.2 are preferably on-chip capacitors, and no inductors or separate high-overhead timing circuits are required. The FIGS. 2A-2B adiabatic charging circuit is operable over a wide frequency range, for example from 1 MHz to 2 GHz.

(12) FIG. 3A illustrates an implementation of the FIG. 2A adiabatic charging circuit, which includes (and preferably consists of) two standard CMOS inverters 10 and 12 whose outputs are tied together: the outer power inverter 10 powered between V.sub.DD and GND, and the inner power inverter 12 with a floating supply and ground at 2/3V.sub.DD and 1/3V.sub.DD, respectively. The outer inverter is controlled by signals P and N, periodically connecting its output to V.sub.DD or GND, while the inner inverter is controlled by signals Pi and Ni, periodically connecting its output to 2/3V.sub.DD or V.sub.DD/3. This ratio changes with different numbers of self-balancing capacitors, for example, connecting C1 and C2 together reduces the number of voltage steps available to three steps, and the ratio is then 1/2V.sub.DD. Increasing to 5 steps, requires another capacitor C3 (not shown) and another switch s5 (not shown), and the ratios would then be multiples of 1/4V.sub.DD. Increasing to 6 steps similarly creates ratios of multiples of 1/5V.sub.DD. Other switched-capacitor topologies are also possible to generate other ratios.

(13) In a preferred embodiment shown in FIG. 3B, the four P, N, Pi, Ni control signals are generated by passing the input clock through a tunable chain of inverters, producing three signals, A, B, and C, with equal delay times between the three signals, t, and passing these signals through a House-of-Cards (HoC) timing gate 14 (whose operation is logically represented by 8 combinational gates in FIG. 3). To enable adiabatic charging, the switch's R.sub.on/W.sub.sw (switches s1-s4) should be set such that the RC.sub.CLK time constant, T, is less than t/1.4. In FIG. 3B, the inverter providing the outer voltage inverter 10 is 1 and the inverter providing the inner voltage inverter 12 is 3.3, indicating that the NMOS devices in the 3.3 inverter 12 are 3.3 times larger than the transistors in the 1 inverter 10. A design guideline for the 4-level voltage inverter is a total of 6.7C.sub.CLK of self-balancing capacitance, which is 1.8 lower than the capacitance required in conventional resonant schemes. By 4-level, this means that there are four steps in the staircase rise and file of the charging CLK output, as shown in the timing diagram of FIG. 3C. The 4-level inverter can be operated as a 3-level inverter by overlapping pulses Ni, Pi, as shown in FIG. 3D, coarsely decreasing the 10-90% rise/fall time from 0.83t to 0.82t; fine rise/fall time configuration can be adjusted via the tunable delay chain. The 4-level inverter can also be operated as a standard 2-level CMOS inverter by disabling the inner inverter.

(14) FIG. 4A shows an example prototype implementation of the HoC timing gate 14, optimized to generate the inverse of N, Ni, Pi, and P at respective nodes 20, 22, 24, and 26 with non-overlapping properties in minimal area and power. With reference to the 0 side, the common root is the 6 A transistor, and the transistors above it are its leaves. Similarly, the transistor with input B and size 4 can be considered a root to transistors above it. Non-overlapping pulses are inherently generated in the HoC 14 gate since, when the leaves of the HoC tree turn on, the output pulses must wait until the common root in the tree is charged or discharged. For instance, suppose that ABC=110, thereby Ni=0. Then, if C transitions from 0.fwdarw.1, C.sub.p1 and C.sub.p (C.sub.p3 and C.sub.p4) are already discharged (charged) when the C/C edge arrives, and hence all controlling pulses (N, Ni, Pi, P) are synchronized without overlap. The HoC gate can be folded to support 4-, 3-, or 2-level timing signals via configuration bits R1 and R0, per the truth table. Respectively 1, 1 is typical inverter operations, 1, 0 is 3-Level operation (FIG. 3D), and 0, 0 is the 4-Level operation (FIG. 3C).

(15) FIG. 4B shows an overall architecture of the preferred example adiabatic clocking prototype. A 4b programmable-strength reconfigurable 4-level power inverter 30 is implemented having 16 slices, where all 16 slices share the same V.sub.L2 and V.sub.L3 nodes, each connected to 50 pF of on-chip thick-oxide capacitance and providing the clock CLK to a clock tree 32, which has the interdigitated form 34 of a 5-level H-tree spanning 550550 m to provide low inductance up to 10 GHz operation with an ESR of 1.03. Slices were used for experimental purposes, and to allow reconfiguring the drive strength (i.e., the size the transistors in the inverters) on the fly, for example to reduce switching losses, or to drive different amounts of capacitance. An on-chip current starved oscillator 38 in FIG. 4C, locked through an off-chip PLL 40 is employed as the clock source. To ensure sufficient rise/fall time for adiabatic operation up to 2 GHz, phases A, B, C are provided from the first 3 stages in the 5-stage ring oscillator 38 such that the adiabatic CLK 10-90% (20-80%) rise/fall time is <<24% (<<18%) of the CLK period. The 4-level inverter drives the clock tree 32 that is 32 pipelined array of 64b MACs (multiplyaccumulate circuits used as a test circuit). Capacitance from digital logic, CLK wiring, and drain parasitics of the driver totals C.sub.CLK15 pF (2:1:1).

(16) Fabricated in 9M 45 nm SOI the prototype global clock distribution, spanning A.sub.LOAD=550550 m.sup.2, takes the form of a tree-driven grid. The clock tree and grid (as well as the power distribution) occupy the top 2 UT metals M9 and M8, respectively. Each line of the 5-level H-tree is split into multiple fingers in the interdigitated form 34 as shown in FIG. 4B to reduce inductance and enable rigid operation up to 10 GHz. The adiabatic driver, including self-balancing capacitors, occupies only 0.0187 mm.sup.2 (<6.2% of A.sub.LOAD). To quantify the improvement over conventional clocking, the driver is configured into the 2-level mode with reduced drive strength for identical rise/fall time to the 3/4-level modes, while multi-level overhead circuits are off.

(17) Measurement results at 1V in FIG. 5A indicate 4-level (3-level) clock power savings of at least 42% (28.4%) from 10 MHz-2 GHz while successfully operating a digital load, with 55.6% (45.5%) peak savings at 10 MHz where adiabatic clocking overhead is minimal At 0.4V near-threshold operation (FIG. 5B), 4-level (3-level) clocking successfully achieves a measured power savings of at least 34.4% (22.5%) from 1 MHz-267 MHz. FIG. 5C shows the measured CLK driver energy under DVFS operation between 0.4-1V, showing above 39.4% savings across the entire DVFS range, with 46.5% peak savings.

(18) FIG. 6A shows the measured power savings across all possible voltages and frequencies, indicating a 41.8% average savings across a 2000 dynamic frequency range. The measured transient waveforms of the 4-level operation at 10 MHz from a 1V supply is shown in FIG. 6B, via both a common-source PMOS analog buffer (open-drain driver) biased by 25 (50 on PCB and 50 input of a sampling scope) for 0.75 V/V gain, and a cascaded inverter chain. FIG. 7 compares the present prototype to the state-of-the-art clocking schemes, demonstrating the widest adiabatic frequency and supply voltage dynamic ranges with the highest clock power savings, all with minimal overhead. The state-of-the art examples [1]-[4] of the table in FIG. 7 are listed in the reference list below.

(19) While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.

(20) Various features of the invention are set forth in the appended claims.

REFERENCES

(21) [1] S. Chan et al., A 4.6 GHz Resonant Global Clock Distribution Network, ISSCC Dig. Tech. Papers, 2004. [2] P. Restle et al., Wide-Frequency-Range Resonant Clock with On-The-Fly Mode Changing for the POWER8 Microprocessor, ISSCC Dig. Tech. Papers, 2014. [3] H. Fuketa et al., Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for 0.37v 980 khz Near-Threshold Logic Circuits, ISSCC Dig. Tech. Papers, 2013. [4] F. Rahman et al., Voltage-Scalable Frequency-Independent Quasi-Resonant Clocking Implementation of a 0.7-to-1.2V DVFS System, ISSCC Dig. Tech. Papers, 2016.