High efficiency ghost illumination cancelation in emissive and non-emissive display panels

Abstract

Disclosed herein is a method of operating a display panel having a matrix of display elements. The method includes ordered steps of: (1) causing flow of current from a source of power, into an anode of a given display element, out of a cathode of the given display element to ground, wherein the flow of current into the anode and out the cathode to ground results in charging of a parasitic capacitance associated with the anode, (2) transferring charge from a storage capacitor to a parasitic capacitance associated with the cathode, and (3) stopping the flow of current, and then transferring charge from the parasitic capacitance associated with the anode to the storage capacitor.

Claims

1. A method of operating a display panel having a matrix of display elements arranged into rows and columns, the method comprising steps of: a) activating a row driver associated with a given row and a column driver associated with a given column such that a current flows through a display element having an anode terminal connected to an anode supply line for the given row and a cathode terminal connected to a cathode supply line for the given column, wherein the current charges a parasitic capacitance associated with the anode supply line for the given row; b) transferring charge from a storage capacitor to the cathode supply line for the given column to pre-charge a parasitic capacitance associated with the cathode supply line; c) deactivating the row driver associated with the given row; and d) transferring charge from the parasitic capacitance associated with the anode supply line to the storage capacitor to prevent a first ghosting type that could otherwise be caused by discharge of the parasitic capacitance associated with the anode supply line through the display element to the column driver associated with the given column; wherein the pre-charge of the parasitic capacitance associated with the cathode supply line prevents a second ghosting type that could otherwise be caused by discharge of the parasitic capacitance associated with the anode supply line through the display element to the parasitic capacitance associated with the cathode supply line.

2. The method of claim 1, further comprising pre-charging the storage capacitor prior to step b).

3. A method of operating a display panel having a matrix of display elements arranged into rows and columns, the method comprising steps of: a) activating a column driver associated with a given column and a row driver associated with a given row such that current flows through a display element having an anode terminal connected to an anode supply line for the given column and a cathode terminal connected to a cathode supply line for the given row, wherein the current flow charges a parasitic capacitance associated with the anode supply line for the given column; b) transferring charge from a storage capacitor to the cathode supply line for the given row to pre-charge a parasitic capacitance associated with the cathode supply line; c) deactivating the column driver associated with the given column; and d) transferring charge from the parasitic capacitance associated with the anode supply line to the storage capacitor to prevent a first ghosting type that could otherwise be caused by discharge of the parasitic capacitance associated with the anode supply line through the display element to the row driver associated with the given row; wherein the pre-charge of the parasitic capacitance associated with the cathode supply line prevents a second ghosting type that could otherwise be caused by discharge of the parasitic capacitance associated with the anode supply line through the display element to the parasitic capacitance associated with the cathode supply line.

4. The method of claim 3, further comprising pre-charging the storage capacitor prior to step b).

5. A display, comprising: a matrix of display elements arranged into rows and columns, with each row having a row driver associated therewith, and with each column having a column driver associated therewith; wherein each display element has an anode terminal and a cathode terminal; wherein each row has an anode supply line coupled to the row driver for that row, and coupled to the anode terminals for the display elements in that row; wherein each column has a cathode supply line coupled to the column driver for that row, and coupled to the cathode terminals for the display elements in that column; a switch for each anode supply line selectively coupling that anode supply line to a storage capacitor; a switch for each cathode supply line selectively coupling that cathode supply line to the storage capacitor; a display driver configured to activate the row driver for a given row and activate the column driver for a given column resulting in current flowing from that row driver, through the anode supply line for that row, into the anode terminal of the display element associated with both the given row and the given column, and out from the cathode terminal of that display element, through the cathode supply line for that column to its column driver, thereby charging a parasitic capacitance associated with the given row; and a switch driver configured to close the switch for the cathode supply line for the given column to thereby transfer charge from the storage capacitor to a parasitic capacitance associated with the given column, and then open the switch for that cathode supply line; wherein the display driver is further configured to deactivate the row driver for the given row, after closing of the switch for the cathode supply line for the given column; and wherein the switch driver is further configured to close the switch for the anode supply line for the given row to thereby transfer charge from a parasitic capacitance associated with the given row to the storage capacitor.

6. The display of claim 5, further comprising a switch for selectively coupling the storage capacitor to a supply voltage; and wherein the switch driver is further configured to, prior to closing the switch for the cathode supply line for the given column, close the switch for selectively coupling the storage capacitor to the supply voltage to pre-charge the storage capacitor prior to charge transfer from the storage capacitor to the parasitic capacitance associated with the given column.

7. The display of claim 5, wherein each display element comprises an emissive pixel comprised of a plurality of sub-pixels, such that the display is an emissive display.

8. The display of claim 5, wherein each display element comprises an emissive zone comprised of a plurality of light emitting diodes arranged to emit light through a plurality of liquid crystals, such that the display is a non-emissive display.

9. A display, comprising: a matrix of display elements arranged into rows and columns, with each row having a row driver associated therewith, and with each column having a column driver associated therewith; wherein each display element has an anode terminal and a cathode terminal; wherein each row has a cathode supply line coupled to the row driver for that row, and coupled to the cathode terminals for the display elements in that row; wherein each column has an anode supply line coupled to the column driver for that row, and coupled to the anode terminals for the display elements in that column; a switch for each cathode supply line selectively coupling that cathode supply line to a storage capacitor; a switch for each anode supply line selectively coupling that anode supply line to the storage capacitor; a display driver configured to activate the column driver for a given column and activate the row driver for a given row resulting in current flowing from that column driver, through the anode supply line for that column, into the anode terminal of the display element associated with both the given row and the given column, and out from the cathode terminal of that display element, through the cathode supply line for that row to its row driver, thereby charging a parasitic capacitance associated with the given column; and a switch driver configured to close the switch for the cathode supply line for the given row to thereby transfer charge from the storage capacitor to a parasitic capacitance associated with the given row, and then open the switch for that cathode supply line; wherein the display driver is further configured to deactivate the column driver for the given column, after closing of the switch for the cathode supply line for the given row; and wherein the switch driver is further configured to close the switch for the anode supply line for the given column to thereby transfer charge from a parasitic capacitance associated with the given column to the storage capacitor.

10. The display of claim 9, further comprising a switch for selectively coupling the storage capacitor to a supply voltage; and wherein the switch driver is further configured to, prior to closing the switch for the cathode supply line for the given row, close the switch for selectively coupling the storage capacitor to the supply voltage to pre-charge the storage capacitor prior to charge transfer from the storage capacitor to the parasitic capacitance associated with the given row.

11. The display of claim 9, wherein each display element comprises an emissive pixel comprised of a plurality of sub-pixels, such that the display is an emissive display.

12. The display of claim 9, wherein each display element comprises an emissive zone comprised of a plurality of light emitting diodes arranged to emit light through a plurality of liquid crystals, such that the display is a non-emissive display.

13. A method of operating a display panel having a matrix of display elements, the method comprising steps of: a) causing flow of current from a source of power, into an anode of a given display element, out of a cathode of the given display element to ground; wherein the flow of current into the anode and out the cathode to ground results in charging of a parasitic capacitance associated with the anode; b) transferring charge from a storage capacitor to a parasitic capacitance associated with the cathode; and c) stopping the flow of current, and then transferring charge from the parasitic capacitance associated with the anode to the storage capacitor.

14. The method of claim 13, further comprising repeating a), b), and c) for each display element within the matrix.

15. The method of claim 13, further comprising, prior to transferring of charge from the storage capacitor to the parasitic capacitance associated with the cathode, at least partially charging the storage capacitor from a power source.

16. The method of claim 13, wherein the transfer of charge from the storage capacitor to the parasitic capacitance associated with the cathode serves to prevent a ghosting type that could otherwise be caused by discharge of the parasitic capacitance associated with the anode to the parasitic capacitance associated with the cathode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a diagrammatical representation of a known non-emissive display.

(2) FIG. 1B is a diagrammatical representation of cross section of the non-emissive display of FIG. 1A.

(3) FIG. 2A is a diagrammatical representation of a known non-emissive display.

(4) FIG. 2B is a diagrammatical representation of cross section of the non-emissive display of FIG. 2A.

(5) FIG. 3 is a block diagram of a display matrix of the display of either FIG. 1A or FIG. 1B.

(6) FIG. 4 is a block diagram of a display disclosed herein including a non-emissive display panel that eliminates ghosting.

(7) FIG. 5 is a block diagram of a display disclosed herein including an emissive display panel that eliminates ghosting.

(8) FIG. 6 is a diagrammatical representation of a display matrix of the display of either FIG. 4 or FIG. 5.

(9) FIG. 7 is a diagrammatical representation of time division operation of the display matrix of FIG. 6.

(10) FIG. 8 is a schematic block diagram of the display matrix of the display of either FIG. 4 or FIG. 5, in a common cathode arrangement, in which the circuitry that eliminates ghosting is shown.

(11) FIG. 9 is a timing diagram showing the display matrix of FIG. 8 in operation.

(12) FIG. 10 is a schematic block diagram of the display matrix of the display of either FIG. 4 or FIG. 5, in a common anode arrangement, in which the circuitry that eliminates ghosting is shown.

(13) FIG. 11 is a timing diagram showing the display matrix of FIG. 10 in operation.

DETAILED DESCRIPTION

(14) The following disclosure enables a person skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein. Do note that in the below description, any described resistor or resistance is a discrete device unless the contrary is stated, and is not simply an electrical lead between two points. Thus, any described resistor or resistance coupled between two points has a greater resistance than a lead between those two points would have, and such resistor or resistance cannot be interpreted to be a lead. Similarly, any described capacitor or capacitance is a discrete device unless the contrary is stated, and is not a parasitic unless the contrary is stated. Moreover, any described inductor or inductance is a discrete device unless the contrary is stated, and is not a parasitic unless the contrary is stated.

(15) A design for a display 30 utilizing a non-emissive display panel 40 is now described with reference to FIG. 4. The display 30 includes an interface controller 33 that receives input from an external device 27, such as a system-on-a-chip (SOC) or microcontroller including an input processor 28 (such as a GPU) and a system memory 29 in bidirectional communication with the input processor 28. The input processor 28 receives input image information and cooperates with the system memory 29 to generate an output to the interface controller 33 indicating the next frame of image data to be displayed on the liquid crystal layer 38 of the display panel 40. The interface controller 33 processes the output from the input processor 28, and provides outputs to a timing controller 34 and display power management circuitry 37. The timing controller 34 coordinates with the backlight controller 35 to provide control signals to the row drivers RD1, . . . , RDn and column drivers CD1, . . . , CDm associated with the backlight panel 14, and the LCD display drivers 36 to provide control signals to the liquid crystals 38, to enable coordination between the backlight panel 14 and the liquid crystals 38 so as to achieve image display. The display panel 40 includes a switch driver 99 for controlling switches within the display panel 40.

(16) Each of the illustrated zones within the backlight panel 14 may include multiple serially connected LEDs, and those LED strings may be connected in parallel with one another.

(17) Note that in some instances the row drivers RD1, . . . , RDn may be incorporated into one or more row drivers, and the column drivers CD1, . . . , CDm may be incorporated into one or more column drivers, and that these one or more row drivers and one or more column drivers may be integrated in or on the backlight panel 14.

(18) The details of the interconnections and switches within the display circuitry 40 that accomplish the elimination or reduction of ghosting will be described below, but first, since such details are equally applicable to a display utilizing an emissive display panel, such a display utilizing an emissive display panel will be described.

(19) A design for a display 50 utilizing an emissive display panel 60 is now described with reference to FIG. 5. The display 50 includes an interface controller 53 that receives input from an external device 57, such as a system-on-a-chip (SOC) or microcontroller including an input processor 51 (such as a GPU) and a system memory 52 in bidirectional communication with the input processor. The input processor 51 receives input image information, and cooperates with the system memory 52 to generate an output to the interface controller 53 indicating the next frame of image data to be displayed on the display matrix 24. The display matrix 24 is emissive, and may generate colored RGB light from the sub-pixels of each pixel, and additionally or alternatively may generate different light colors other than RGB from the sub-pixels of each pixels. The interface controller 53 processes the output from the input processor 51, and provides outputs to a timing controller 54 and display power management circuitry 57. The timing controller 54 coordinates with the display driver 56 to provide control signals to the row drivers RD1, . . . , RDn and column drivers CD1, . . . , CDm associated with the display panel 24 to provide control signals so as to achieve image display. The display panel 60 includes a switch driver 99 for controlling switches within the display panel 60.

(20) Each of the illustrated pixels within the display matrix 24 includes sub-pixels of different colors (for example, red, green, blue, and/or other colors), and each such sub-pixel may include multiple serially connected LEDs of the appropriate color, and those multiple LED strings may be connected in parallel with one another.

(21) Note that in some instances the row drivers RD1, . . . , RDn may be incorporated into one or more row drivers, and the column drivers CD1, . . . , CDm may be incorporated into one or more column drivers, and that these one or more row drivers and one or more column drivers may be integrated in or on the display matrix 24.

(22) Now described with reference to FIG. 6 is a block diagram of the display panel 40 or 60 showing the interconnections between the different pixels/zones. Shown is an M×N matrix of pixels/zones, with a respective row driver RD1, . . . , RDn coupled to a respective anode-supply line for each row, and a respective column driver CD1, . . . , CDm coupled to a respective cathode-supply line for each column. It is to be recognized that M and N may be any integer numbers.

(23) The electrical arrangement may be such each row driver RD1, . . . , RDn is coupled to the anodes of the LEDs within its own row, and such that each column driver CD1, . . . , CDm is coupled to the cathodes of the LEDs within its own column; conversely, the electrical arrangement may be such that each row driver is coupled to the cathode of the pixels within its own row, and such that each column driver is coupled to the anode of the pixels within its own column.

(24) Operation of the display panel 40 and 60 may be according to a time multiplexing scheme shown in FIG. 7, which is organized into image frames. During each image frame, each row driver RD1, . . . , RDn is successively activated, and during the activation of each row driver, all column drivers CD1, . . . , CDm are activated. Note that the order activation of the row drivers RD1, . . . , RDn during each image frame is configurable and may be changed on the fly during operation through operation of the backlight controller 35 (for non-emissive displays 40) or operation of the display drivers 56 (for emissive displays 60). Also, one or more rows may not be activated during a given image frame, or may be activated more than one time during a given image frame, and this is also configurable through operation of the backlight controller 35 or display drivers 56.

(25) Now shown in FIG. 8 is a block diagram of the display panel 40 or 60 having an M×N matrix of pixels/zones, in which each row driver RD1, . . . , RDn is coupled to the anodes of the pixels/zones of its own row by a respective anode-supply line, and in which each column driver CD1, . . . , CDm is coupled to the cathodes of the pixels/zones of its own column by a respective cathode-supply line. Each row has a respective parasitic capacitance Cpr1, . . . , Cprn associated therewith, and each column has a respective parasitic capacitance Cpc1, . . . , Cpcm associated therewith. M and N may be any integer numbers, and thus the display panel 40 or 60 may have any number of rows or columns.

(26) Each anode-supply line is selectively coupled to a storage capacitor Cstorage by a respective switch SWr, . . . , SWrm. The storage capacitor Cstorage is selectively coupled to the parasitic capacitance Cpc1 by a switch SWc1 and is selectively coupled to the parasitic capacitance Cpcm by a switch SWcn. An optional switch SWd selectively couples the storage capacitor to a supply voltage Vdd. The switches SWr, . . . , SWrm, the switches SWc1, . . . , SWcn, and SWd are controlled by a switch driver 99, which causes the switching of those switches described below. Note that the switch driver 99 may be integrated into one or more of the row drivers RD1, . . . , RDm, or may be integrated into one or more of the column drivers CD1, . . . CDn, or may be integrated into any suitable external circuitry.

(27) Operation is now described with additional reference to FIG. 9. Assume for this example that ghost cancelation is being performed for row 1 and column 1. Also, for purposes of this example, the switch SWr1 will be referred to as the discharge switch for the parasitic capacitance Cpr1 for row 1, and the switch SWc1 will be referred to as the pre-charge switch for the parasitic capacitance Cpc1 for column 1.

(28) Prior to time T1, charge has been transferred from the row parasitic capacitance Cpr1 to the storage capacitor Cstorage.

(29) At time T1, where switch SWr1 is opened, switch SWc1 is open, optional switch SWd is open, and the row driver RD1 and column driver CD1 are activated. The voltage on the anode-supply line for row 1 increases accordingly, and at time T2, current begins to flow through the pixel/zone[1,1] to the column driver CD1, causing emission of light. This current flow also has the effect of charging up the row parasitic capacitance Cpr1.

(30) Ignore the operation of the optional switch SWd for the moment. At time T5, the column driver CD1 is deactivated, and the pre-charge switch SWc1 is closed, thereby pre-charging the column parasitic capacitance Cpc1 due to charge sharing between the storage capacitor Cstorage and the column parasitic capacitance Cpc1.

(31) At time T6, the pre-charge switch SWc1 is opened, and the discharge switch SWr1 is closed, with the result being that the row parasitic capacitance Cpr1 is discharged to the storage capacitor Cstorage due to charge sharing.

(32) In this way of transferring the charge from the parasitic row capacitance Cpr1 to the storage capacitor Cstorage upon the deactivation of the row driver RD1, “upper ghosting” is eliminated, since the discharge of the parasitic row capacitance Cpr1 is to the storage capacitor Cstorage instead of through the pixel/zone[1,1].

(33) Moreover, in this way of pre-charging parasitic column capacitance Cpc1 prior to deactivation of the row driver RD1, “lower ghosting” is eliminated, since there is no path for charge to flow from the parasitic row capacitance Cpr1 through the pixel/zone[1,1] to the parasitic column capacitance Cpc1 (since Cpc1 will already be charged).

(34) This technique not only eliminates upper ghosting, but saves power, because instead of the parasitic row capacitance Cpr1 discharging through the pixel/done, through the column driver, to ground, the charge from the parasitic row capacitance Cpr1 is transferred to the storage capacitor Cstorage, and then used to pre-charge the parasitic column capacitance Cpc1.

(35) Returning now to the optional switch SWd, this switch may be closed between times T3 and T4 to thereby charge the storage capacitor Cstorage to a desired amount. This may be desirable depending on the capacitance value of the column parasitic capacitance Cpc1, so as to ensure that prior to time T5, Cstorage holds sufficient charge to fully pre-charge the column parasitic capacitance Cpc1.

(36) The above operation has been described for one pixel/zone, and is repeated for each pixel/zone, with the difference being for those operations that the discharge switch SWr for the currently activated row is opened between times T1 and T6, that the pre-charge switch SWc for the currently activated column is closed between times T5 and T6, and that the discharge switch SWr for the currently activated row is closed between times T6 and the activation of the next row driver.

(37) Now shown in FIG. 10 is a block diagram of the display panel 40′ or 60′ having an M×N matrix of pixels/zones, in which each row driver RD1, . . . , RDn is coupled to the cathodes of the pixels/zones of its own row by a respective cathode-supply line, and in which each column driver CD1, . . . , CDm is coupled to the anodes of the pixels/zones of its own column by a respective anode-supply line. Each row has a respective parasitic capacitance Cpr1, . . . , Cprn associated therewith, and each column has a respective parasitic capacitance Cpc1, . . . , Cpcm associated therewith. M and N may be any integer numbers, and thus the display panel 40′ or 60′ may have any number of rows or columns.

(38) Each anode-supply line is selectively coupled to a storage capacitor Cstorage by a respective switch SWc1, . . . , SWcn. The storage capacitor Cstorage is selectively coupled to the parasitic capacitance Cpr1 by a switch SWr1 and is selectively coupled to the parasitic capacitance Cprn by a switch SWrm. An optional switch SWd selectively couples the storage capacitor Cstorage to a supply voltage Vdd. The switches SWr, . . . , SWrm, the switches SWc1, . . . , SWcn, and SWd are controlled by a switch driver 99, which causes the switching of those switches described below.

(39) Operation is now described with additional reference to FIG. 11. Assume for this example that ghost cancelation is being performed for row 1 and column 1. Also, for purposes of this example, the switch SWc1 will be referred to as the discharge switch for the parasitic capacitance Cpc1 for column 1, and the switch SWr1 will be referred to as the pre-charge switch for the parasitic capacitance Cpr1 for row 1.

(40) Prior to time T1, charge has been transferred from the column parasitic capacitance Cpc1 to the storage capacitor Cstorage.

(41) At time T1, where switch SWc1 is opened, switch SWr1 is open, optional switch SWd is open, and the row driver RD1 and column driver CD1 are activated. The voltage on the cathode-supply line for column 1 decreases accordingly, and at time T2, current begins to flow through the pixel/zone [1,1] from the column driver CD1 to the row driver RD1, causing emission of light. This current flow also has the effect of charging up the column parasitic capacitance Cpc1.

(42) Ignore the operation of the optional switch SWd for the moment. At time T5, the column driver CD1 is deactivated, and the pre-charge switch SWr1 is closed, thereby pre-charging the row parasitic capacitance Cpr1 due to charge sharing between the storage capacitor Cstorage and the row parasitic capacitance Cpr1.

(43) At time T6, the pre-charge switch SWr1 is opened, and the discharge switch SWc1 is closed, with the result being that the column parasitic capacitance Cpc1 is discharged to the storage capacitor Cstorage due to charge sharing.

(44) In this way of transferring the charge from the parasitic column capacitance Cpc1 to the storage capacitor Cstorage upon the deactivation of the column driver CD1, “upper ghosting” is eliminated, since the discharge of the parasitic column capacitance Cpc1 is to the storage capacitor Cstorage instead of through the pixel/zone [1,1].

(45) Moreover, in this way of pre-charging parasitic row capacitance Cpr1 prior to the low to high commutation of the row driver RD1, “lower ghosting” is eliminated, since there is no path for charge to flow from the parasitic column capacitance Cpc1 through the pixel/zone[1,1] to the parasitic row capacitance Cpr1 (since Cpr1 will already be charged).

(46) This technique not only eliminates lower ghosting, but saves power, because instead of the parasitic column capacitance Cpc1 discharging through the pixel/zone[1,1], through the row driver RD1 to ground, the charge from the parasitic column capacitance Cpc1 is transferred to the storage capacitor Cstorage, and then used to pre-charge the parasitic row capacitance Cpr1.

(47) Returning now to the optional switch SWd, this switch may be closed between times T3 and T4 to thereby charge the storage capacitor Cstorage to a desired amount. This may be desirable depending on the capacitance value of the parasitic row capacitance Cpr1, so as to ensure that prior to time T5, Cstorage holds sufficient charge to fully pre-charge the parasitic row capacitance Cpr1.

(48) The above operation has been described for one pixel/zone, and is repeated for each pixel/zone, with the difference being for those operations that the discharge switch SWc for the currently activated column is opened between times T1 and T6, that the pre-charge switch SWr for the currently activated row is closed between times T5 and T6, and that the discharge switch SWc for the currently activated column is closed between times T6 and the activation of the next column driver.

(49) Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of this disclosure, as defined in the annexed claims.

(50) While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be envisioned that do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the disclosure shall be limited only by the attached claims.