SYSTEM AND METHOD FOR TUNABLE PRECISION OF DOT-PRODUCT ENGINE

Abstract

A semiconductor cell comprising a memory element for storing a first binary operand is disclosed. In one aspect, the memory element provides complementary memory outputs, and a multiplication block that is locally and uniquely associated with the memory element. The multiplication block may be configured to receive complementary input signals representing binary input data and the complementary memory outputs of the associated memory element representing the first binary operand, implement a multiplication operation on these signals, and provide an output of the multiplication operation to an output port. An array of semiconductor cells and a neural network circuit comprising such array are also disclosed.

Claims

1. A semiconductor cell, comprising: a memory element for storing a first binary operand, the memory element providing complementary memory outputs, and a multiplication block that is locally and uniquely associated with the memory element, the multiplication block configured to receive complementary input signals representing binary input data and the complementary memory outputs of the associated memory element representing the first binary operand, and further configured to implement a multiplication operation on each signal, and provide an output of the multiplication operation to an output port.

2. The semiconductor cell of claim 1, wherein the multiplication block is adapted to perform an XNOR or XOR logic function between the input data and the stored first binary operand.

3. The semiconductor cell of claim 1, further comprising a select switch for controlling provision of the output of the multiplication operation to an external circuit.

4. The semiconductor cell of claim 1, wherein the memory element is implemented as an SRAM implementation.

5. The semiconductor cell of claim 1, wherein the memory element further comprises at least one input for receiving the first binary operand from a data line and at least one access switch connecting the at least one input to a memory unit of the memory cell, the at least one access switch configured to be driven by a word line for passing the first binary operand to the memory unit.

6. The semiconductor cell of claim 5, further comprising a second access switch, the access switches connecting two inputs to the memory unit and configured to provide complementary data of the first binary operand to the memory unit.

7. An array of semiconductor cells logically arranged in rows and columns, and comprising word lines along the rows of the array and bit lines along the columns thereof, the crossing of a set of word lines and bit lines uniquely identifying a location of at least one semiconductor cell in the array, the semiconductor cells comprising: a memory element for storing a first binary operand, the memory element providing complementary memory outputs, and a multiplication block that is locally and uniquely associated with the memory element, the multiplication block configured to receive complementary input signals representing binary input data and the complementary memory outputs of the associated memory element representing the first binary operand, and further configured to implement a multiplication operation on each signal, and provide an output of the multiplication operation to an output port.

8. The array of claim 7, further comprising word lines configured for delivering complementary input activations to input ports of the semiconductor cells, and comprising read bit lines configured for receiving the outputs of the multiplication operations from the readout ports of the semiconductor cells in the array connected to that read bit line.

9. A neural network circuit comprising: at least one array of semiconductor cells and a plurality of sensing units; the at least one array logically arranged in rows and columns, and comprising word lines along the rows of the array and bit lines along the columns thereof, the crossing of a set of word lines and bit lines uniquely identifying a location of at least one semiconductor cell in the array, wherein each semiconductor cell comprises: a memory element for storing a first binary operand, the memory element providing complementary memory outputs, and a multiplication block that is locally and uniquely associated with the memory element, the multiplication block configured to receive complementary input signals representing binary input data and the complementary memory outputs of the associated memory element representing the first binary operand, and further configured to implement a multiplication operation on each signal, and provide an output of the multiplication operation to an output port, and wherein each sensing unit is shared between different sharing semiconductor cells of at least one column of the at least one array, for reading the outputs of the multiplication blocks of the sharing semiconductor cells, and a plurality of accumulation units, each accumulation unit arranged to sequentially accumulate the outputs of a particular sensing unit corresponding to sequentially selected semiconductor cell of the sharing semiconductor cells.

10. The neural network circuit of claim 9, further comprising a plurality of post-processing units for further processing of the output signals of the accumulation units.

11. The neural network circuit of claim 9, wherein at least two semiconductor cells sharing a single sensing unit are grouped into an enlarged semiconductor unit, the output ports of the at least two semiconductor cells being connected to a switch element, the output of the switch element being connected to the single sensing unit.

12. The neural network circuit of claim 11, wherein the switch element is adapted for allowing multi-bit accumulation of the multiplication result of the at least two semiconductor cells grouped into the enlarged semiconductor unit.

13. The neural network circuit of claim 12, wherein the switch element comprises a first transistor with a first control electrode and a first and second main electrode and a second transistor with a second control electrode and a third and fourth main electrode, the first and third main electrode being coupled together to a first reference voltage, and the second and fourth main electrode being coupled together to the single sensing unit, wherein an output signal of a first semiconductor cell of the at least two grouped semiconductor cells is coupled to the first control electrode, and an output of a second semiconductor cell of the at least two grouped semiconductor cells is coupled to the second control electrode.

14. The neural network circuit of claim 13, wherein the switch element further comprises a third transistor with a third control electrode and a fifth and sixth main electrode and a fourth transistor with a fourth control electrode and a seventh and eighth main electrode coupled in series whereby the sixth main electrode is connected to the seventh main electrode, the fifth main electrode is coupled with the first and third main electrodes, and the eighth main electrode is coupled with the second and fourth main electrodes, the output of the first semiconductor cell being coupled to the third control electrode, and the output of the second semiconductor cell being coupled to the fourth control electrode.

15. The neural network of claim 9, wherein the neural network is configured to perform a clustering, classification or pattern recognition task.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The disclosed technology will now be described further, by way of example, with reference to the accompanying drawings, in which:

[0033] FIG. 1 is a high-level illustration of a neural network;

[0034] FIG. 2 is a bloc-schematic illustration of a semiconductor cell according to embodiments of a first aspect of the disclosed technology;

[0035] FIG. 3 schematically illustrates a neural network according to embodiments of the disclosed technology;

[0036] FIG. 4 schematically illustrates a semiconductor cell according to embodiments of the disclosed technology, located at a cross point of a set of word lines and a set of bit lines;

[0037] FIG. 5 illustrates in more detail the semiconductor cell of FIG. 4;

[0038] FIG. 6 illustrates an SRAM implementation of a semiconductor cell with a select switch according to one embodiment of the disclosed technology;

[0039] FIG. 7 schematically illustrates a semiconductor cell according to embodiments of the disclosed technology, like the embodiment of FIG. 4 but with one word line less;

[0040] FIG. 8 illustrates in more detail the semiconductor cell of FIG. 7;

[0041] FIG. 9 illustrates an SRAM implementation of a semiconductor cell without select switch according to another embodiment of the disclosed technology;

[0042] FIG. 10 schematically illustrates a neural network according to another embodiment of the disclosed technology;

[0043] FIG. 11 schematically illustrates a neural network according to yet another embodiment of the disclosed technology, with enlarged semiconductor units;

[0044] FIG. 12 illustrates one column in an array of cells in the implementation of a neural network as in FIG. 11;

[0045] FIG. 13 schematically illustrates an enlarged semiconductor unit as can be used in a column as illustrated in FIG. 12, with the word lines and bit lines to which it is connected;

[0046] FIG. 14 illustrates in more detail an SRAM implementation of an enlarged semiconductor unit as used in the implementation of FIG. 11, with one type of select switch;

[0047] FIG. 15 illustrates in more detail an SRAM implementation of an enlarged semiconductor unit as used in the implementation of FIG. 11, with another type of select switch;

[0048] FIG. 16 illustrates a neural network with semiconductor units as in FIG. 14;

[0049] FIG. 17 shows Monte Carlo simulation results of a neural network implemented in accordance with FIG. 14;

[0050] FIG. 18 illustrates an alternative to the embodiment illustrated in FIG. 14, which allows to better discriminate between different situations, in NMOS implementation;

[0051] FIG. 19 illustrates an alternative to the embodiment of FIG. 18, in PMOS implementation;

[0052] FIG. 20 shows Monte Carlo simulation results of a neural network implemented in accordance with FIG. 18; and

[0053] FIG. 21 illustrates a sensing unit design for use with embodiments of the disclosed technology.

[0054] The drawings are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the invention.

[0055] Any reference signs in the claims shall not be construed as limiting the scope.

[0056] In the different drawings, the same reference signs refer to the same or analogous elements.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

[0057] The disclosed technology will be described with respect to particular embodiments and with reference to certain drawings but the disclosed technology is not limited thereto but only by the claims.

[0058] The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosed technology described herein are capable of operation in other sequences than described or illustrated herein.

[0059] Moreover, directional terminology such as top, bottom, front, back, leading, trailing, under, over and the like in the description and the claims is used for descriptive purposes with reference to the orientation of the drawings being described, and not necessarily for describing relative positions. Because components of embodiments of the disclosed technology can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only, and is in no way intended to be limiting, unless otherwise indicated. It is, hence, to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosed technology described herein are capable of operation in other orientations than described or illustrated herein.

[0060] Reference throughout this specification to one embodiment or an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosed technology. Thus, appearances of the phrases in one embodiment or in an embodiment in various places throughout this disclosure are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

[0061] Similarly, it should be appreciated that in the description of exemplary embodiments of the disclosed technology, various features of the disclosed technology are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the disclosed technology requires more features than are expressly recited in each claim. Rather, as the claims reflect, inventive aspects may lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the disclosed technology.

[0062] Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the disclosed technology, and form different embodiments, as would be understood by those in the art. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0063] It should be noted that the use of particular terminology when describing certain features or aspects of the disclosed technology should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the disclosed technology with which that terminology is associated.

[0064] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosed technology may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0065] In embodiments of the present invention, semiconductor cells are logically organized in rows and columns. Throughout this description, the terms horizontal and vertical (related to the terms row and column, respectively) are used to provide a co-ordinate system and for ease of explanation only. They do not need to, but may, refer to an actual physical direction of the device. Furthermore, the terms column and row are used to describe sets of array elements, in particular in the disclosed technology semiconductor cells, which are linked together. The linking can be in the form of a Cartesian array of rows and columns; however, the disclosed technology is not limited thereto. As will be understood by those skilled in the art, columns and rows can be easily interchanged and it is intended in this disclosure that these terms be interchangeable. Also, non-Cartesian arrays may be constructed and are included within the scope of the disclosed technology. Accordingly, the terms row and column should be interpreted widely. To facilitate in this wide interpretation, the claims refer to logically organized in rows and columns. By this is meant that sets of semiconductor cells are linked together in a topologically linear intersecting manner; however, that the physical or topographical arrangement need not be so. For example, the rows may be circles and the columns radii of these circles and the circles and radii are described in the disclosure as logically organized rows and columns. Also, specific names of the various lines (e.g., word line and bit line) are intended to be generic names used to facilitate the explanation and to refer to a particular function and this specific choice of words is not intended to in any way limit the disclosed technology. It should be understood that all these terms are used only to facilitate a better understanding of the specific structure being described, and are in no way intended to limit the disclosed technology.

[0066] For the technical description of embodiments of the disclosed technology, the design enablement of a multi-layer perceptron (MLP) with binary weights and activations is used as an illustrative example. A similar description is valid, but not written out in detail, for convolutional neural networks (CNNs), with the appropriate reordering of logic units and the designation of the memory unit as storing binary filter values, instead of binary weight values.

[0067] Artificial neural networks are computing systems inspired by the biological neural networks that constitute human and animal brains. Such systems learn to do tasks by considering examples, generally without task-specific programming.

[0068] FIG. 1 is a schematic illustration of an artificial neural network 10. Such artificial neural network 10 is based on a collection of connected units called artificial neurons 11. In FIG. 1, each circular node represents an artificial neuron 11, and an arrow represents a connection (synapse) 12 from the output of one neuron 11 to the input of another. Each synapse 12 between neurons 11 can transmit a signal from one neuron 11 to another neuron 11. The receiving neuron 11 can process the received signal and then transmit the processed signal to downstream neurons 11 connected to it.

[0069] Typically, neurons 11 are organized in layers. Neurons 11 of different layers may perform different kinds of transformations on their inputs. In FIG. 1, a number L of five layers 131, 132, 133, 134, 135 is illustrated. Signals travel from the first layer (input layer) 131 to the last layer (output layer) 135, possibly after traversing a plurality of intermediate layers, in the embodiment illustrated after traversing three intermediate layers 132, 133, 134.

[0070] The input layer 131 may have a first number N.sub.in of neurons 11, and may hence accept the first number N.sub.in of inputs. There may be a second number N.sub.i of neurons 11 per intermediate layer 132, 133, 134, with N.sub.i dependent on the intermediate layer and on the application. The output layer 135 may have a third number N.sub.out of neurons 11. For training, N.sub.in, N.sub.i and N.sub.out can be any number. For testing or classification, N.sub.out should be smaller than N.sub.in (N.sub.out<N.sub.in). The neural network 10 is dimensioned in terms of N (maximum number of neurons in any of the layers) and L (number of layers).

[0071] Neurons may have a state, generally represented by a real number, typically between 0 and 1. In particular implementations, these states are weights that vary as learning proceeds, which can increase or decrease the strength of the signal that it sends downstream.

[0072] In the particular example of Binary Neural Networks (or Binary MLP), first operands under the form of weights w are stored in the neurons 11, and second operands under the form of input activations x are received by the neurons. They may both be confined in the [1, +1] interval. During training, the weights w and the input activations x are scalar values (w, x[1, +1]). During testing, the weights w and the input activations x may be binary values (w, x{1, +1}).

[0073] As illustrated in FIG. 1, each layer comprises a calculation part (the white box to the left) and it may furthermore comprise a normalization and non-linearity part (the grey box to the right).

[0074] In the example of BNN, the calculation part processes incoming input activations x and locally stored weights w, so as to obtain y.sub.k=.sub.j=0.sup.N1x.sub.jw.sub.kj, with k the neuron in the next layer. This operation is called a dot-product operation. Evaluation of the k.sup.th neuron in a subsequent layer would be the dot-product of 0 to N1 inputs (x) with weights (w). Each neuron in a subsequent layer will have the same inputs but weights will be different.

[0075] The normalization and non-linearity part may process the obtained output values y.sub.k of each neuron as follows, with , , , normalization parameters obtained from training:

[00001]$y^{}=\frac{y-}{}.Math.+$$y^{}=\mathrm{sign}.Math.\left\{y^{}\right\}=\{\begin{array}{cc}+1& \mathrm{if}.Math..Math.y^{}0\\ -1& \mathrm{if}.Math..Math.y^{}<0\end{array}$

[0076] If at test time the weight values w and the input activations x are binary values (w, x{1, +1}), this corresponds in binary logic with w, x{0, 1}. As a result, the dot-product operation corresponds to the following truth table:

TABLE-US-00001 w x Product 1 0 1 0 +1 1 1 0 +1 1 1 0 +1 1 1 0 1 0 +1 1 +1 1 +1 1
Hence the dot-product operation (product between weight w and input activation x) which is the core operation in such neural networks, is actually an XNOR operation. If one of the inputs is swapped in sign, this can be expressed as an XOR operation.

[0077] In a first aspect, the disclosed technology relates to a semiconductor cell 20, as illustrated in FIG. 2, for performing a multiplication operation between a first and a second operand. The semiconductor cell 20 comprises a memory element 21 for storing the first operand. The memory element 21, in some embodiments, may have a single input port for receiving the first operand. The first operand may locally be converted into complementary data. In alternative embodiments, the memory element 21 may have two input ports for receiving complementary data representing the first operand. The memory element 21 has a first output port 211 and a second output port 212, each providing complementary memory outputs, respectively, e.g., Q and Qbar, respectively. The first operand is thus a constant value, which is stored in place in the semiconductor cell 20, more particularly in the memory element 21 thereof.

[0078] The semiconductor cell 20 furthermore comprises a multiplication block 22. The multiplication block 22 is locally and uniquely associated with the memory element 21 of the semiconductor cell 20. The multiplication block 22 has a first input port 221 and a second input port 222, for receiving the complementary memory outputs Q, and Qbar, from the first and second output ports 211, 212 of the memory element 21, respectively. The multiplication block 22 further has a third input port 223 and a fourth input port 224, for receiving the second operand X and its complement Xbar, respectively. The second operand X is a value fed to the semiconductor cell 20, which may be variable, and which may depend on the current input to the semiconductor cell 20, for instance a frame to be classified. The second operands X are sometimes referred to as activations or input activation. In particular embodiments of the disclosed technology, where MLPs are involved, the first operand can be one of the weights that interconnect two MLP layers. In alternative embodiments, where CNNs are involved, the first operand can be one of the filters that are convolved with the input activations, or a weight of a final fully connected layer.

[0079] The multiplication block 22 is configured for implementing a multiplication operation between the first operand stored in its associated memory element 21 and the second operand received by the semiconductor cell 20. The multiplication is done in place, i.e., within the semiconductor cell 20. The multiplication block 22 has an output port 225 for outputting the result Out of the multiplication operation (e.g., a digital output) for instance, for putting this result on a column line.

[0080] In a second aspect, a plurality of such semiconductor cells 20 may be arranged in an array 30, whereby the semiconductor cells are logically arranged in rows and columns, as for instance illustrated in FIG. 3. The semiconductor cells may be semiconductor cells 20 as illustrated in FIG. 2, but the embodiment illustrated in FIG. 3 includes a slightly modified version of semiconductor cells, indicated as semiconductor cells 31. As illustrated in FIG. 5, these semiconductor cells 31 not only include the memory element 21 and the multiplication block 22, but furthermore also include a select switch 32 for coupling the output of the semiconductor cell to a read bit line. In alternative embodiments where semiconductor cells 20, as illustrated in FIG. 2, are arranged in an array 30, a select switch, such as select switch 32, can be provided outside the semiconductor cell 20 for coupling the semiconductor cell 20 to a read bit line.

[0081] In FIG. 3, for simplicity and readability of the figure, the separate blocks (memory element 21, multiplication block 22, select switch 32) of a semiconductor cell 31 according to embodiments of the first aspect of the disclosed technology are not illustrated, but all elements of the array 30 are semiconductor cells 31 of the type according to embodiments of the first aspect of the disclosed technology. These semiconductor cells 31 are indicated as MEXN in the drawing, meaning that a local combination of a memory element 21 and a multiplication block 22 is made, in accordance with embodiments of the first aspect of the disclosed technology, and that furthermore a select switch 32 is provided inside the semiconductor cell 31.

[0082] Such array 30 may comprise word lines configured for delivering second operands (input activations x) to input ports of the semiconductor cells 31. The input ports of the semiconductor cells 31 may coincide with or be linked to the third and fourth input ports 223, 224 of the multiplication block. The array 30 may also comprise read bit lines configured for receiving the outputs of the multiplication operation from readout ports of the semiconductor cells 31 connected to that read bit line. The readout port of a semiconductor cell 31 may coincide with or be linked to the output port 225 of the multiplication block 22.

[0083] FIG. 4 and FIG. 5 illustrate the word and bit lines connected to a particular embodiment of a semiconductor cell 31 according to embodiments of the first aspect of the disclosed technology when organized in an array 30. As illustrated in FIG. 5, the semiconductor cell 31, comprising the memory element 21 and the multiplication block 21, furthermore comprises a select switch 32 for coupling the output of the semiconductor cell to a read bit line.

[0084] It can be seen from FIG. 4 that, for this embodiment, four horizontal word lines are connected to each semiconductor cell 31 in the array 30, as well as three bit lines. The four word lines are: [0085] a first word line WL for activating an access switch 38 for passing a first operand to a memory unit 34 of the memory element 21 for being stored there; the first operand is stored when the access switch 38 is actuated; once the access switch 38 is turned off, the stored operand remains in the memory element 21, [0086] second and third word lines WX and WXbar, respectively, for applying incoming input activations X and Xbar to the multiplication block 22, and [0087] a read word line RWL for activating a select switch 32 for bringing the output of the semiconductor cell 20 to a readout bus (read bit line RBL as indicated below).

[0088] The three vertical bit lines, for this embodiment, are: [0089] a first bit line BL for applying a first operand to an access switch for being passed to the memory unit of the memory element 21 for being stored there. In the particular embodiment illustrated in the drawings, the memory unit is a cross coupled invertor configuration storing complementary versions of the first operand. The first operand may be applied via the first bit line, and a complementary version thereof may be generated inside the semiconductor cell (not illustrated), in which case a single first bit line BL is sufficient. However, in alternative embodiments, the complementary versions of the first operand may be generated outside the semiconductor cell 20, in which case both the first operand and its complement are to be brought to the memory unit, which requires the first bit line BL and a second bit line BLbar, for applying the complementary pair to the memory unit. [0090] a third bit line RBL for accepting an output value of the semiconductor cell, upon activation of the select switch 32 by a corresponding signal on the read word line RWL.

[0091] FIG. 6 illustrates a particular semiconductor cell 20, with the word lines and bit lines as described with reference to FIG. 4 and FIG. 5.

[0092] FIG. 3 illustrates a neural network circuit an array 30 according to embodiments of a third aspect of the disclosed technology. In the embodiment illustrated, each read bit line RBL connecting semiconductor cell 31 logically arranged on a column of the array 30 is connected to a sensing unit (SU) 33, for instance a sense amplifier. A sensing unit 30 is thus shared between different semiconductor cells 31 of the array 30, for reading the outputs of the multiplication blocks 22 of these semiconductor cells 31. In particular embodiments, such as for instance the embodiment illustrated in FIG. 3 and in FIG. 7, one sensing unit 33 is provided for every column of semiconductor cells 31 in the array 30. By doing so, all columns may be simultaneously sensed. The sensing unit 33 senses the values put on the read bit line RBL sequentially by each of the semiconductor cells 31 logically arranged on the column associated with that read bit line RBL. The sharing of the sensing unit 33 by the plurality of semiconductor cells is thus a time sharing. The sequence of putting the values on the read bit line RBL is determined by the signals on the fourth word lines RWL, which activate the select switches 32 of the different rows, such that each semiconductor cell 31 delivers its value in sequence. In alternative embodiments, not illustrated in the drawings, a sensing unit may be shared between semiconductor cells of more than one column of the array.

[0093] The read out values are then accumulated in accumulators 36. If so required, the accumulated values may be further processed in post-processing units 37. The further processing may comprise or consist of normalization and/or non-linear operations. The values so obtained per column can be read out and stored for further use, or can be directly used by further circuitry (not illustrated, and not discussed in further detail).

[0094] In the embodiment illustrated in FIG. 3, the rows of semiconductor cells 31 are accessed in sequence, for instance by a walking one (see the RWL.sub.i signal at the left-hand side of FIG. 3).

[0095] The activation signals X.sub.i (X.sub.i and Xbar.sub.i) are directly fed into the semiconductor cells 31, more particularly they are put on the word lines WX and WXbar providing input to the multiplication block 22.

[0096] In this embodiment, and for the example illustrated, four cycles are needed to read out all multiplication values between the first and the second operands (i.e., one cycle for reading out each row). The read out values are then accumulated per column in accumulators 36, and, if so required, further processed in post-processing units 37. The further processing may comprise or consist of normalization and/or non-linear operations.

[0097] FIG. 7, FIG. 8 and FIG. 9 illustrate an alternative embodiment of what is described in FIG. 4, FIG. 5 and FIG. 6. The difference between both embodiments is that in the second embodiment the select transistor 32 can be left out. This implementation not only reduces one transistor per semiconductor cell, but also removes the need of presence of the read word line RWL. This can be obtained by activating the word lines WX and WXbar only when it is desired to sense the output values.

[0098] A corresponding timing diagram is shown at the left-hand side of FIG. 10, which also includes elements as in FIG. 3, except for the select transistor and its corresponding driving word line RWL.

[0099] In an alternative embodiment of the third aspect, two activation inputs X, are enabled simultaneously, as illustrated in FIG. 11 (see signals at the left-hand side). The sensing of the two outputs after the multiplication operation (e.g., XNOR or XOR operation) may be done under single sensing. This procedure has the advantage that it reduces energy consumption by half, as only half of the read operations are needed. Moreover, also the reading delay is reduced.

[0100] One column 50 of an array 40 according to this embodiment is illustrated in FIG. 12. Two semiconductor cells 20, are combined into an enlarged semiconductor unit 51, indicated MEXN2, for simultaneous readout. Hereto, a switch element 52 is provided between the outputs of the semiconductor cells 20 and the read bitline RBL.

[0101] The connection to word lines and bit lines is illustrated in FIG. 13. It can be seen that, in this case, seven word lines connect to a single enlarged semiconductor unit 51, and three bit lines. The bit lines are as described with respect to FIG. 4. The word lines correspond to twice the bit lines as described with respect to FIG. 4 (one set to each semiconductor cell forming part of the enlarged semiconductor unit 51), minus 1 read word line because both semiconductor cells forming part of the enlarged semiconductor unit 51 are actuated simultaneously, hence via a single word line.

[0102] A detailed implementation example of semiconductor cells 20 and supplementary circuitry for use in the modified neural network circuit 45, enabling two inputs simultaneously, is illustrated in FIG. 14. In this embodiment, the memory element is implemented in SRAM technology.

[0103] Illustrated are two semiconductor cells 20 according to embodiments of the first aspect of the disclosed technology. They are combined together in an enlarged semiconductor unit 51. One semiconductor cell 20, implemented in SRAM technology, is illustrated in more detail at the left-hand side of FIG. 14. It comprises an SRAM memory element 21, and a multiplication block 22. The multiplication block 22 is an XNOR or an XOR block (depending on the input activation signals).

[0104] The word line WL and the bit lines BL, BLbar are provided for writing a value into the memory element 21. The memory element 21 has a first output port 211 and a second output port 212 for delivering the stored value and its complementary value, respectively.

[0105] The multiplication block 22, in the embodiment illustrated as an XNOR block, has an output port 225 for delivering the result of the multiplication operation carried out on the first operand, being the value stored in the memory element 21, and the second operand, being the input activation received by the semiconductor cell 20. The output ports 225 of the two semiconductor cells 20 together forming the enlarged semiconductor unit 51 are fed to a switch element 52.

[0106] The switch element 52 is such that the outputs 225 of the semiconductor cells 20 are each connected to a gate of a transistor T1, T2, the two transistors T1, T2 being coupled in parallel between ground and a read bitline RBL. A switch 53 is provided between the two transistors T1, T2 and the read bitline.

[0107] If the switch 53 is closed (e.g., if this switch is formed by a transistor), by bringing its gate, connected to a read word line RWL, to high, a combined output signal of the two semiconductor cells 20 can be read from the read bitline RBL. The read bitline is charged to high first (pre-charged). If the output of both semiconductor cells is low, the transistors T1 and T2 both do not go in conduction, and the charge brought on the read bitline RBL substantially remains there. When the sensing unit SU (e.g., sense amplifier) senses the charge on the read bitline RBL, it senses a high value, and it determines therefrom that the output of both semiconductor cells 20 being read out is low. If the output of either one of the semiconductor cells 20 is high, the read bitline RBL is pulled to ground, and the charges previously stored there leak away. If the output of both semiconductor cells 20 is high, the read bitline RBL is also pulled to ground and the previously stored charges leak away. This time, this goes even faster.

[0108] In an alternative embodiment to FIG. 14, as illustrated in FIG. 15, similarly to the embodiment illustrated in FIG. 9, the switch 53 can be left out. This way, a switch element 54 is provided, which only comprises the transistors T1 and T2. The outputs 225 of the semiconductor cells 20 are each connected to a gate of a transistor T1, T2, the main electrodes of the two transistors T1, T2 being coupled in parallel between ground and a read bitline RBL. This configuration can only be implemented provided the actuation of the word lines for applying incoming input activations to the multiplication block is accurately timed to happen only when it is desired to sense the value of the semiconductor cell. This implementation reduces one switch (e.g. transistor) per two semiconductor cells, and hence one signal line, and thus reduces energy consumption. However, it will increase leakage as well as capacitance on the read bit line RBL.

[0109] An array of enlarged semiconductor cells MEXN2_B, illustrated in detail in FIG. 15, is illustrated in FIG. 16. Explanation is similar to arrays described before, and a timing diagram can be found at the left-hand side of the drawing. Compared to FIG. 11 it can be seen that the word line for actuating the switch 53 has been omitted, as in this case this actuation is not required.

[0110] It is an advantage of these embodiments of the disclosed technology with enlarged semiconductor units 51 that only one sense operation is required, where previously, to read out the same, two sense operations and a separate combination operation would have been required. Simultaneous reading can now be done on a single bitline. This means lower read energy is required, and the readout throughput has doubled.

[0111] However, this process is illustrated in FIG. 17, which shows Monte Carlo Simulation results with 30 samples. It can be seen that it is hard to make the difference between both semiconductor cells 20 having an output high (11), and one having output high and the other one having output low (10 or 01).

[0112] This can be solved by implementing the switch element differently, as for instance illustrated in FIG. 18. FIG. 18 corresponds to FIG. 14 as far as the enlarged semiconductor unit 51 is concerned. Only the switch element 80 between the enlarged semiconductor unit 51 and the read bitline RBL is different. In the embodiments illustrated, besides the connection between the outputs of the respective semiconductor cells 20 and the gates of the transistors T1 and T2 that are coupled in parallel (see also description of FIG. 14), the outputs of the semiconductor cells 20 are also each coupled to one of the gates of transistors T3 and T4, respectively, that are coupled in series, and this series coupling is coupled in parallel to the transistors T1 and T2 also coupled in parallel. The goal is to enhance the difference between resistance when only one of the transistors T1, T2 go into conduction, compared to when both go into conduction.

[0113] The way of working is similar, in that the read bitline RBL is charged high first, e.g. pre-charged at positive power supply voltage V.sub.DD. If none of the semiconductor cells 20 have an output high, the charge remains on the read bitline RBL, and can be read out as such by the sensing unit SU (e.g., sense amplifier). If either one of the semiconductor cells 20 has an output high, one of the transistors T1 or T2, and only one of the transistors T3 or T4 go into conduction. The charge leaks away from the read bitline RBL and this charge drop can be detected by the sensing unit SU. The charge does not leak away, however, over the series connection of transistors T3 and T4. If, however, both semiconductor cells 20 have an output high, all transistors T1, T2, T3 and T4 go in conduction, and charge leaks away from the read bitline RBL very fast. This fast or slower leaking away of the charge from the read bitline RBL can be detected by the sensing unit SU, which can discriminate this way between the different situations.

[0114] In the embodiment illustrated in FIG. 18, the switch 80 element is implemented in NMOS. Alternatively, this switch element 80 can also be implemented in PMOS, as illustrated in FIG. 19, which would only have implications as to the pre-charging of the read bit line RBL, but which would further be pretty much similar in operation. In this case, the read bit line RBL would be pre-discharged, for instance at ground level. If none of the semiconductor cells 20 have an output high, the charge on the read bitline RBL remains low, and can be read out as such by the sensing unit SU. If either one of the semiconductor cells 20 has an output high, one of the transistors T1 or T2, and only one of the transistors T3 or T4 go into conduction. The read bit line RBL gets charged and this increase in charge on the read bit line RBL can be detected by the sensing unit SU. The read bit line RBL is not charged, however, over the series connection of transistors T3 and T4. If, however, both semiconductor cells 20 have an output high, all transistors T1, T2, T3 and T4 go into conduction, and the read bit line RBL is charged very fast. This fast or slower charging away of the read bitline RBL can be detected by the sensing unit SU, which can discriminate this way between the different situations.

[0115] This is illustrated in the simulation results shown in FIG. 20.

[0116] The sense amplifier design is as illustrated in FIG. 21. The first sense amplifier SA I corresponds to the typical implementation of memory. However, if it is desired to sense three levels, it is impossible to do this with only one sense amplifier with one reference VrefI. Therefore, a second sense amplifier SA II is used for sensing the third level, based on a second reference VrefII. The first sense amplifier SA I may for instance discriminate between 00 and anything else. The second sense amplifier SA II may then for instance discriminate between 01 or 10 and 11. The second sense amplifier SA II is only used when precision is needed. The output of the first sense amplifier SA I enables the second sense amplifier SA II.

[0117] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways. The invention is not limited to the disclosed embodiments. For example, the invention does not need to be implemented with SRAM memory elements, but can make use of any type of non-volatile memory.