BUMP PLANARITY CONTROL

Abstract

A method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an IC die to an external circuit. The method also includes depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit.

Claims

1. A method for manufacturing an integrated circuit (IC) package, comprising: depositing a first layer of metal at a location of a first metal post that is capable of electrically connecting to an IC die; and concurrently depositing a second layer of metal on the first layer of metal, and the first layer of metal at a location of a second metal post that is capable of electrically connecting to the IC die.

2. The method of claim 1, wherein, after depositing the second layer of metal, a height of the first metal post is substantially the same as a height of the second metal post, the height of the first metal post and the height of the second metal post including all the layers of metal deposited on each of the first metal post and the second metal post.

3. The method of claim 1, further comprising, prior to depositing the first layer of metal, applying a layer of photoresist material to the location of the first metal post and the location of the second metal post.

4. The method of claim 3, further comprising: removing the photoresist from the location of the first metal post; and retaining the photoresist at the location of the second metal post.

5. The method of claim 1, further comprising, after depositing the first layer of metal, applying a layer of photoresist material to the location of the first metal post and the location of the second metal post.

6. The method of claim 5, further comprising: removing the photoresist from the location of the first metal post; and removing the photoresist from the location of the second metal post.

7. The method of claim 1, wherein a volume of the second metal post is greater than a volume of the first metal post.

8. The method of claim 1, wherein each of the first layer of metal at the location of the first metal post and the second layer of metal at the location of the first metal post is a layer of copper.

9. The method of claim 1, where the first metal post is round in cross section and the second metal post is oval in cross section.

10. The method of claim 1, further comprising: forming a redistribution layer on the IC die, the forming comprising: depositing a first layer of photoresist material on the IC die; removing the first layer of photoresist material from input/output pads of the IC die; depositing a third layer of metal on the photoresist material and the input/output pads of the IC die; depositing a second layer of photoresist material on the third layer of metal; removing the second layer of photoresist material to expose portions of the third layer of metal; etching the third layer of metal to form connections between a first of the input/output pads of the IC die and the location of the first metal post, and a second of the input/output pads of the IC die and the location of the second metal post; and depositing a second layer of photoresist material on the IC die after the etching; removing the second layer of photoresist material from the location of the first metal post and the location of the second metal post; and depositing tin/silver solder at an end of the first metal post and the second metal post.

11. An integrated circuit (IC) package, comprising: a redistribution layer; and a plurality of conductive bumps formed on the redistribution layer to connect an IC die to an external circuit, a first of the bumps comprising: a metal post comprising: a first layer of copper extending from the redistribution layer; and a second layer of copper deposited on and extending from the first metal layer.

12. The IC package of claim 11, wherein a second of the bumps comprises a metal post, the metal post comprising a single layer of copper.

13. The IC package of claim 12, wherein the metal post of the first of the bumps and the metal post of the second of the bumps are substantially a same height.

14. The IC package of claim 12, wherein a cross-sectional area of the metal post of the first of the bumps is smaller than a cross-sectional area of the metal post of the second of the bumps.

15. The IC package of claim 12, wherein a volume of the metal post of the first of the bumps is less than a volume of the metal post of the second of the bumps.

16. The IC package of claim 11, wherein the first metal layer is copper and the second metal layer is copper.

17. The IC package of claim 11, wherein the redistribution layer is formed on the IC die, the redistribution layer comprising: a first layer of photoresist material deposited on the IC die; a layer of metal disposed on the first layer of photoresist, the first layer of metal patterned to form conductors that connect a first input/output pad of the IC die and the first of the bumps, and that connect a second input/output pad of the IC die and the second of the bumps; a second layer of photoresist material deposited on the layer of metal; a first opening in the second layer of photoresist at a location of the first of the bumps; a second opening the second layer of photoresist at a location of the second of the bumps; and tin/silver solder disposed at an end of the first of the bumps and an end of the second of the bumps.

18-20. (canceled)

21. A method for manufacturing an integrated circuit (IC) package, comprising: depositing a first layer of metal at a location of a first metal post of an IC die; depositing a second layer of metal on the first layer of metal, and the first layer of metal at a location of a second metal post of the IC die; and depositing solder on the second layer of metal and the first layer of metal.

22. The method of claim 18, wherein depositing a second layer of metal on the first layer of metal, and the first layer of metal at a location of a second metal post of the IC die includes depositing the second layer of metal and the first layer of metal concurrently.

23. The method of claim 18, where a cross-sectional area of the first metal post is smaller than a cross-sectional area of the second metal post.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0006] FIG. 1 shows a flow diagram for a method for manufacturing an integrated circuit with bump height equalization in accordance with various examples;

[0007] FIG. 2 shows an integrated circuit die prepared for construction of bumps of different sizes in accordance with various examples;

[0008] FIG. 3 shows a photoresist material applied to the die in preparation for application of first layer of metal to the bumps in accordance with various examples;

[0009] FIG. 4 shows the die with photoresist material removed from bump locations selected for plating with layer of metal in accordance with various examples;

[0010] FIG. 5 shows the die with a layer of metal applied to the selected bump locations in accordance with various examples;

[0011] FIG. 6 shows the die stripped of photoresist material after deposition of the metal layer in accordance with various examples;

[0012] FIG. 7 shows a photoresist material applied to the die in preparation for application of second layer of metal to the bumps in accordance with various examples;

[0013] FIG. 8 shows the die with photoresist material removed from all bump locations for plating with a layer of metal in accordance with various examples;

[0014] FIG. 9 shows the die with a layer of metal applied to all bump locations in accordance with various examples;

[0015] FIG. 10 shows a layer of solder applied to all bump locations in accordance with various examples;

[0016] FIG. 11 shows the die with photoresist material removed to expose bumps in accordance with various examples;

[0017] FIG. 12 shows varying bump height caused by different cross-sectional bump areas;

[0018] FIG. 13 shows bumps with different cross-sectional areas and a same height in accordance with various examples;

[0019] FIG. 14 shows a reticle pattern applied to remove the photoresist material from selected bump locations in accordance with various examples;

[0020] FIG. 15 shows a reticle pattern applied to remove the photoresist material from all bump locations in accordance with various examples;

[0021] FIG. 16 shows a flow diagram for a method for packaging an integrated circuit in accordance with various examples; and

[0022] FIG. 17 shows a singulated integrated circuit with completed bumps in accordance with various examples.

DETAILED DESCRIPTION

[0023] Certain terms have been used throughout this description and claims to refer to particular system components. As one skilled in the art will appreciate, different parties may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In this disclosure and claims, the terms including and comprising are used in an open-ended fashion, and thus should be interpreted to mean including, but not limited to . . . . Also, the term couple or couples is intended to mean either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation based on is intended to mean based at least in part on. Therefore, if X is based on Y, X may be a function of Y and any number of other factors.

[0024] While integrated circuit input/output using bump terminals provides a number of advantages, use of bump terminals is not without issue. Many assembly and reliability issues are caused by tilted dies, solder voids and non-wets. These defects are in turn often caused by the condition of the wafers during bumping. Bump feature size is one factor that affects plating thickness. As bump feature size increases, plated thickness also increases. Given that a die includes multiple bump feature sizes, the plating thickness associated with the different feature sizes varies, and the device bumps can consequently exhibit planarity issues that cause die tilt, solder voids, etc. Thus, poor bump planarity is one cause of poor package reliability.

[0025] Implementations of the present disclosure include methods for manufacturing an integrated circuit with equalized bump height. Implementations apply multiple layers of metal to construct bump terminals. At least one layer of the multiple layers of metal is applied to compensate for the difference in bump height attributable to different bump feature sizes of the integrated circuit. By equalizing the height of the various bumps of the integrated circuit, Implementations avoid the solder voids and other problems associated with poor bump planarity.

[0026] FIG. 1 shows a flow diagram for a method 100 for manufacturing an integrated circuit with bump height equalization in accordance with various examples. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some Implementations may perform only some of the actions shown.

[0027] In block 102, an integrated circuit die has been prepared for bump formation. FIG. 2 shows the integrated circuit die 200 prepared for construction of bumps of different sizes in accordance with various examples. The integrated circuit die 200 may include a redistribution layer 202 on which the bumps are to be formed, and a polyimide layer polyimide layer 204 that isolates the redistribution layer 202. An opening 206 in the polyimide layer 204 allows for formation of a first bump and an opening 208 in the polyimide layer 204 allows for formation of a second bump. The area of the opening 208 is greater than the area of the opening 206. Consequently, the cross-sectional area of a bump formed at the opening 208 will be greater than the cross-sectional area of a bump formed at the opening 206. As a result in the difference in cross-sectional area, the height of a bump formed at the opening 208 will be greater than the height of a bump formed at the opening 206 by deposition of a single layer of metal. The method 100 compensates for the difference in bump height produced by conventional IC processing. While FIG. 2 illustrates a single opening 206 and a single opening 208, in practice the integrated circuit die 200 may include any number of openings 206 and any number of openings 208 each corresponding to a bump.

[0028] In preparation for construction of bumps on the integrated circuit die 200, a layer of photoresist material is applied to the integrated circuit die 200. FIG. 3 shows the photoresist material 312 applied to the integrated circuit die 200 in preparation for application of first layer of metal.

[0029] In block 104, the photoresist material 312 applied to the integrated circuit die 200 in block 102 is removed from the opening 206 to allow addition of metal at the opening 206. FIG. 4 shows the photoresist material 312 removed from the opening 206. The opening 208 remains covered by the photoresist material 312 to prevent addition of metal at the opening 208.

[0030] FIG. 14 shows an example of a reticle pattern 1400 that may be applied to remove the photoresist material 312 from the opening 206 and any number of additional bump locations of a same area as the opening 206 while leaving the opening 208 and any number of additional bump locations of a same area as the opening 208 covered by the photoresist material 312. The reticle pattern 1400 includes an opening 1402 that corresponds to the opening 206 and lacks an opening corresponding to the opening 208.

[0031] In block 106, a layer of metal is deposited at the opening 206 to form a bump (i.e., a metal post) at the opening 206. FIG. 5 shows a layer of metal 502 deposited at the opening 206. The layer of metal 502 is copper is some implementations. The thickness of the layer of metal 502 is selected to compensate for the difference in height of a bump formed at the opening 206 and a bump formed at the opening 208 if a single layer of metal is applied to the integrated circuit die 200 that produces a bump of a given height at the opening 208. The photoresist material 312 prevents deposition of metal at the opening 208.

[0032] In block 108, the photoresist material 312 deposited on the integrated circuit die 200 in block 102 is removed from the integrated circuit die 200. FIG. 6 shows the integrated circuit die 200 stripped of the photoresist material 312 after deposition of the layer of metal 502.

[0033] In block 110, a second layer of photoresist material is deposited on the integrated circuit die 200. The second layer of photoresist material may be thicker than the layer of photoresist material applied in block 102. FIG. 7 shows the second layer of photoresist material 702 applied to the integrated circuit die 200. The photoresist material 702 covers the opening 208 and covers the layer of metal 502 at the opening 206. The thickness of the second layer of photoresist material 702 may be greater than the thickness of the photoresist material 312.

[0034] In block 112, the photoresist material 702 applied in block 110 is removed from the opening 208 and from the layer of metal 502 at the opening 206 to allow addition of metal at the opening 208 and to the layer of metal 502 at the opening 206. FIG. 8 shows the photoresist material 702 removed from the opening 208 and from the layer of metal 502 at the opening 206 for plating with a layer of metal. In practice, the photoresist material 702 may be removed from all bump locations on the integrated circuit die 200.

[0035] FIG. 15 shows an example of a reticle pattern 1500 that may be applied to remove the photoresist material 702 from all bump locations (e.g., opening 206 and opening 208) of the integrated circuit die 200. The reticle pattern 1500 includes opening 1502 that corresponds to the opening 206 and opening 1504 that corresponds to the opening 208.

[0036] In block 114, a layer of metal is deposited at the opening 208 and on the layer of metal 502 at the opening 206 to form a bump (i.e., a metal post) at the opening 208 and to increase the height of the bump (i.e., the metal post) at the opening 206. FIG. 9 shows a layer of metal 902 deposited at the opening 208 and on the layer of metal 502 at the opening 206. The layer of metal 902 is a same metal as the layer of metal 502. For example, the layer of metal 502 and the layer of metal 902 are copper in some Implementations. The thickness of the layer of metal 902 is selected to produce a bump at the opening 208 of a given height. Because of the layer of metal 902 adds to the layer of metal 502, the bump formed at the opening 206 is substantially the same height as (e.g., coplanar with) the bump formed at the opening 208, while the volume of the bump formed at the opening 208 is greater than the volume of the bump formed at the opening 206.

[0037] A layer of solder may be deposited atop the layer of metal 902 to facilitate conductive connection of the die 200 to other circuits when the solder is reflowed. FIG. 10 shows a layer of solder 1002 deposited top the layer of metal 902 at the opening 206 and the opening 208.

[0038] In block 116, the photoresist material 702 is removed from the integrated circuit die 200 to expose the bumps formed at the opening 206 and the opening 208. FIG. 11 shows the photoresist material 702 removed from the die 200 to expose the bumps formed at the opening 206 and the opening 208.

[0039] FIG. 12 shows a die 1200 that was not manufactured in accordance with the method 100 after solder reflow. The cross-sectional area of the bump 1202 is smaller than the cross-sectional area of the bump 1204. Consequently, the height of the bump 1202 is less than the height of the bump 1204 which may result in misconnection of the bump 1202 to an underlying pad or cause the die 1200 to be tilted relative to the underlying substrate.

[0040] FIG. 13 shows a die 1300 that was manufactured in accordance with the method 100 after solder reflow. Even though the cross-sectional area of the bump 1302 is smaller than the cross-sectional area of the bump 1304, the height of the bump 1302 is the same as the height of the bump 1304 due to the compensation provided by the method 100. As a result, misconnection of the bump 1302 to an underlying pad or tilt of the die 1300 relative to the underlying substrate is avoided.

[0041] FIG. 16 shows a flow diagram for a method 1600 for bump completion and singulation in accordance with various examples. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some Implementations may perform only some of the actions shown.

[0042] In block 1602, a semiconductor wafer is received. For example, a semiconductor wafer produced in a semiconductor wafer factory may be received by a semiconductor packaging facility that is to package the die provided on the semiconductor wafer.

[0043] In block 1604, a redistribution layer is deposited on the semiconductor wafer. The redistribution layer provides conductors for connecting the input/output pads of each die of the semiconductor wafer to a location at which a bump is to be deposited. Deposition of the redistribution layer may include depositing a layer of photoresist material on the semiconductor wafer, and applying lithography to remove the photoresist material from the locations of input/output pads of each die formed on the semiconductor wafer. A layer of metal is deposited on the photoresist material. A layer of photoresist material is deposited on the metal layer and lithography is applied to pattern the photoresist material for formation of conductive traces that connect the input/output pads of each die to a location at which a bump is to be deposited. The layer of photoresist material and the layer of metal are removed in accordance with the pattern applied to the photoresist to form the conductive traces that connect the input/output pads of each die to a location at which a bump is to be constructed.

[0044] In block 1606, a layer of photoresist material (e.g., a layer of polyimide) is deposited on the semiconductor wafer. Lithography is applied to pattern the photoresist material for exposure of the metal deposited in block 1604 at the locations at which each bump is to be constructed. The photoresist is removed from each location at which a bump is to be constructed.

[0045] In block 1608, bumps are deposited on the semiconductor wafer in accordance with the method 100. By applying the method 100 to deposit the bumps, the height of the bumps is consistent with varying cross-sectional area.

[0046] In block 1610, the dice are singulated from the semiconductor wafer.

[0047] After singulation of the dice from the wafer, each die may be attached (e.g., by reflow of the bumps, to a substrate, and encapsulated in a mold compound.

[0048] FIG. 17 shows an integrated circuit package 1700 in accordance with various examples. The integrated circuit package 1700 includes an integrated circuit die 1702, a redistribution layer 1704, a polyimide layer 1706, bumps 1714 having a first cross-sectional area, and bumps 1716 having a second cross-sectional area. The cross-sectional area of bumps 1716 is greater than the cross-sectional area of bumps 1714. The polyimide layer 1706 is disposed over the metal of the redistribution layer 1704.

[0049] The bump 1714 includes a first copper layer 1708 and a second copper layer 1710 deposited on the redistribution layer 1704. The bump 1716 includes the second copper layer 1710 deposited on the redistribution layer 1704 (i.e., the bump 1716 does not include the first copper layer 1708). The bumps 1714 and 1716 include solder 1712 (e.g., tin/silver solder) deposited on the second copper layer 1710.

[0050] The above discussion is meant to be illustrative of the principles and various examples of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.