Printed circuit board and manufacturing method thereof, and semiconductor package including the printed circuit board

Abstract

Disclosed herein are a printed circuit board, a manufacturing method thereof, and a semiconductor package including the printed circuit board. The printed circuit board includes a base substrate including a plurality of circuit patterns, a cavity formed above the base substrate, a pad embedded in the base substrate and being exposed through the substrate bottom surface of the cavity, and an electronic component mounted in the cavity and electrically connected to the pad. According to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.

Claims

1. A printed circuit board comprising: a first insulating layer forming one surface of a base substrate; an embedded circuit pattern embedded in the first insulating layer and exposed through the one surface of the base substrate; a second insulating layer comprising a circuit and laminated on the one surface of the base substrate and having a cavity formed therein, the second insulating layer being exposed through the cavity; and a metal layer disposed on the one surface of the base substrate and exposed through an inner wall of the cavity, wherein the metal layer is disposed on and abuts the surface of the base substrate, and the second insulating layer partially embeds the metal layer.

2. The printed circuit board as set forth in claim 1, wherein an upper surface of the embedded circuit pattern is disposed on the one surface of the base substrate.

3. The printed circuit board as set forth in claim 1, wherein the embedded circuit pattern comprises an embedded pad exposed through the cavity.

4. The printed circuit board as set forth in claim 1, further comprising a via formed in the second insulating layer and connected with the embedded circuit pattern.

5. The printed circuit pattern as set forth in claim 4, further comprising an exposed circuit pattern connected with the via and exposed to an outside on the second insulating layer.

6. The printed circuit board as set forth in claim 1, further comprising an electronic component installed in the cavity.

7. The printed circuit board as set forth in claim 1, wherein the embedded circuit pattern is disposed below the metal layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a view illustrating an example of a typical semiconductor package having a PoP structure;

(2) FIG. 2 is a view illustrating another example of a typical semiconductor package having a PoP structure;

(3) FIG. 3 is a cross-sectional view showing a structure of a printed circuit board according to an exemplary embodiment of the present invention;

(4) FIG. 4 is a view of a semiconductor package including the printed circuit board according to the exemplary embodiment shown in FIG. 3;

(5) FIG. 5 is a flowchart illustrating a manufacturing method of the printed circuit board according to the exemplary embodiment of the present invention;

(6) FIGS. 6A to 6E are views sequentially illustrating the manufacturing processes according to the manufacturing method of the printed circuit board according to the exemplary embodiment of the present invention; and

(7) FIGS. 7A and 7B are partially enlarged views of portion A of FIG. 6.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(8) Terms and words used in the present specification and claims are not to be construed as a general or dictionary meaning, but are to be construed as meaning and concepts meeting the technical ideas of the present invention based on a principle that the inventors can appropriately define the concepts of terms in order to describe their own inventions in the best mode.

(9) Throughout the present specification, unless explicitly described to the contrary, comprising any components will be understood to imply the inclusion of other elements rather than the exclusion of any other elements. A term part, module, device, or the like, described in the specification means a unit of processing at least one function or operation and may be implemented by hardware or software or a combination of hardware and software.

(10) Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(11) FIG. 3 is a view showing a structure of a printed circuit board according to an exemplary embodiment of the present invention.

(12) Referring to FIG. 3, the printed circuit board 320 according to the exemplary embodiment of the present invention is configured to include a base substrate 321, a cavity 321c, pads 322p and an electronic component 330. Here, the printed circuit board 320 including the electronic component 330 is substantially identical to a lower semiconductor package 320 of a semiconductor package to be described below.

(13) The base substrate 321 includes a plurality of circuit patterns 322, 606 and 607. The base substrate 321 may have a single layer or multi layer structure. In the exemplary embodiment, the base substrate 321 of a multi layer structure will be described. Further, the circuit patterns 322, 606 and 607 are formed on at least one of the upper surface and the lower surface, or the inside of the base substrate 321. As shown in the drawing, in the base substrate 321 employed in the present invention, the circuit patterns 322, 606 and 607 are formed on all of the upper and lower surfaces and the inside of the base substrate 321.

(14) The cavity 321c is formed above the base substrate 321. The cavity 321c serves to mount an electronic component 330 (e.g., a semiconductor chip) therein. Further, an alignment pattern 601 may be formed on the lower portion of the sidewall of the cavity 321c for forming the cavity (see FIG. 7A). The alignment pattern 601 is the remaining part of the protective layer 601 during the manufacturing process of the printed circuit board to be described below. The detailed description of which will be given below. The dimensions of the cavity 321c, that is, the width and depth are variable depending on the width and depth of an electronic component 330 mounted therein and on the manufacturing specifications of a semiconductor package to be described below.

(15) The pads 322p are exposed through the substrate bottom surface of the cavity 321c and are embedded in the base substrate 321. The pads 322p exposed through the bottom surface of the substrate are the top surfaces of the respective circuit patterns 322. The upper surfaces of the pads 322p and the bottom surface of the cavity 321c are in the same plane. The detailed description of which will be given below.

(16) The electronic component 330 is mounted in the cavity 321c and is electrically connected to the pads 322p. Here, the electronic component 330 includes external terminals and is mounted in a face-down position in which the external terminals face the pads 322p.

(17) The printed circuit board according to the exemplary embodiment the present invention is preferably formed in the inside of the base substrate 321, and may further include vias 323, 604 and 605 electrically connecting the circuit patterns 322, 606 and 607 to each other and the pads 322p to the circuit patterns 322, 606 and 607.

(18) Now, a manufacturing method of the printed circuit board according to the exemplary embodiment will be described.

(19) For the sake of easy understating, FIG. 4 which illustrates a semiconductor package will be described after FIG. 5 and FIGS. 6A to 6E are described, which relate to a manufacturing method of the printed circuit board.

(20) FIG. 5 is a flowchart illustrating a manufacturing method of the printed circuit board according to the exemplary embodiment, and FIGS. 6A to 6E are views sequentially illustrating the manufacturing processes of the manufacturing method of the printed circuit board according to the present invention.

(21) Referring to FIG. 5 and FIGS. 6A to 6E, in a manufacturing method of a printed circuit board according to the present invention, firstly, a first protective layer 601 for protecting circuits is formed on a predetermined region of an upper surface of a base substrate 321 (S501, FIG. 6A). The base substrate 321 may have circuit patterns 322 formed on its upper and lower surfaces and its inside, and vias 323 connecting the upper and lower circuit patterns 322 formed therein.

(22) The first protective layer 601 may be formed by removing the protective layer formed on both surfaces of a detach core used in the early process, leaving only a predetermined region for forming the cavity 321c to be described. Alternatively, the first protective layer 601 may be formed only on a predetermined region where the cavity 321c is to be formed, including the circuit patterns on the upper surface of the base substrate 321 and adjacent insulating portion. As the material for the protective layer, a single metal or an alloy may be used. In some cases, non-metal material may also be used.

(23) After the first protective layer 601 is formed, insulating layers 602 and 603 are formed on the upper surface where the first protective layer 601 is formed and on the lower surface, respectively (S502, FIG. 6B). As the material for the insulating layers 602 and 603, synthetic resins (epoxy resins, polyester resins, urea resins, phenolic resins) may be used.

(24) After the insulating layers 602 and 603 are formed, vias 604 and 605 are formed through the upper and lower insulators 602 and 603, and then circuits 606 and 607 are formed on the upper surface of the upper insulator 602 and on the lower surface of the lower insulator 603, respectively (S503, FIG. 6C). The vias 604 and 605 may be formed by forming holes in the upper and lower insulating layers 602 and 603 using a laser drill and then filling the holes with metal material (e.g., copper) by electrical plating. The circuits 606 and 607 formed on the upper and lower surfaces of the insulating layers 602 and 603 may be formed by performing photolithography using a mask.

(25) After the circuits 606 and 607 are formed on the upper and lower surfaces of the insulators 602 and 603, second protective layers 608 and 609 for protecting circuits may be formed, at the gaps between the circuits 606 and 607, respectively (S504, FIG. 6D). As the material for the second protective layers 608 and 609, solder resist may be used. Again, photolithography using a mask may be used for forming the second protective layers 608 and 609.

(26) After the second protective layers 608 and 609 are formed, a cavity 321c for mounting an electronic component 330 (shown in FIG. 3) is formed at a position in the upper insulating layer 602 where the first protective layer 601 has been formed (S505, FIG. 6E). Any one of wet etching and dry etching, preferably dry etching may be used for forming the cavity 321c.

(27) In forming of the cavity 321c, the first protective layer 601 embedded in the upper insulating layer 602 is also removed, such that the top surfaces of the circuit patterns 322 exposed through the bottom of the cavity 321c are in the same plane with the bottom surface of the cavity 321c with no difference in level.

(28) Since the plane of the circuits 322 exposed through the bottom of the cavity 321c where the electronic component 330 is mounted is flat with the plane of the bottom of the cavity 321c, an insulation distance may be formed high so that the electronic component 330 may be inserted into the cavity 321c. Accordingly, it is easy to obtain the depth of the cavity 321c with relatively wide ranges (e.g., 40 to 150 m) in the upper insulating layer 602.

(29) Further, in forming the cavity 321c, as shown in FIG. 7A, a part of the first protective layer 601 may remain at the lower portion of the sidewall of the cavity 321c. The remaining part of the first protective layer 601 may be used as an alignment mark to allow the electronic component 330 to be accurately mounted when the electronic component 330 is mounted in the cavity 321c in the process of manufacturing a semiconductor package. As appreciated, the first protective layer 601 may be completely removed when the cavity 321c is formed as shown in FIG. 7B.

(30) Now, a description will be made referring back to FIG. 4.

(31) FIG. 4 is a view of a semiconductor package including the printed circuit board according to the exemplary embodiment shown in FIG. 3.

(32) Referring to FIG. 4, the semiconductor package including the printed circuit board according to the exemplary embodiment of the present invention has a PoP structure that an upper semiconductor package 310 is stacked on an lower semiconductor package 320.

(33) The lower semiconductor package 320 includes a printed circuit board 320 having a cavity 321c of a predetermined size formed on a part of the upper surface, and an electronic component 330 mounted in the cavity 321c.

(34) Further, the printed circuit board 320 is the one described above with reference to FIG. 3.

(35) That is, the printed circuit board 320 includes the base substrate 321, the cavity 321c and the pads 322p.

(36) The base substrate 321 includes a plurality of circuit patterns 322, 606 and 607. The base substrate 321 may have a single layer or multi layer structure. Further, the circuit patterns 322, 606 and 607 are formed on at least one of the upper surface and the lower surface, or the inside of the base substrate 321. As shown in the drawing, in the base substrate 321 employed in the present invention, the circuit patterns 322, 606 and 607 are formed on all of the upper and lower surfaces and the inside of the base substrate 321.

(37) The cavity 321c is formed above the base substrate 321. The cavity 321c is formed to mount an electronic component 330 (e.g., a semiconductor chip) therein. Further, an alignment pattern 601 may be formed on the lower portion of the sidewall of the cavity 321c for forming the cavity. The alignment pattern 601 is the remaining part of the protective layer 601 during the manufacturing process of the printed circuit board. The dimensions of the cavity 321c, that is, the width and depth are variable depending on the width and depth of an electronic component 330 mounted therein and on the manufacturing specifications of a semiconductor package to be described below.

(38) The pads 322p are exposed through the substrate bottom surface of the cavity 321c and embedded in the base substrate 321. The pads 322p exposed through the bottom surface of the substrate are the top surfaces of the respective circuit patterns 322. The upper surfaces of the pads 322p and the bottom surface of the cavity 321c are in the same plane.

(39) The electronic component 330 is mounted in the cavity 321c and electrically connected to the pads 322p. Here, the electronic component 330 includes external terminals and is mounted in a face-down position in which the external terminals face the pads 322p.

(40) The printed circuit board 320 according to the exemplary embodiment the present invention is preferably formed in the inside of the base substrate 321, and may further include vias 323, 604 and 605 electrically connecting the circuit patterns 322, 606 and 607 to each other and the pads 322p to the circuit patterns 322, 606 and 607.

(41) As described above, according to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.

(42) Further, since the plane of circuits exposed through the bottom surface of the cavity in which an electronic component is mounted is flat with the bottom surface of the cavity, an insulation distance may be formed high so that the electronic component may be inserted into the cavity. Accordingly, it is easy to obtain the depth of the cavity with relatively wide ranges in the upper insulating layer.

(43) As stated above, according to the present invention, a cavity having a predetermined depth is formed in a base substrate of a printed circuit board so as to mount an electronic component therein, such that a gap between an upper semiconductor package and a lower semiconductor package may be obtained even if pitches between the balls are decreased for high density and high performance of the upper semiconductor package in the manufacturing of a semiconductor package having a PoP structure.

(44) Although the exemplary embodiments of the present invention have been disclosed for illustrative purposes, the present invention is not limited thereto, but those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. Therefore, the true scope of the present invention to be protected should be defined only by the appended claims and it is apparent to those skilled in the art that technical ideas equivalent thereto are within the scope of the present invention.